Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.26 97.70 90.58 57.52 76.92 94.94 98.34 17.78


Total test records in report: 307
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T255 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1102138099 May 04 12:45:14 PM PDT 24 May 04 12:45:16 PM PDT 24 20418599 ps
T256 /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.895226549 May 04 12:45:25 PM PDT 24 May 04 12:45:27 PM PDT 24 10197880 ps
T257 /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.75233133 May 04 12:44:51 PM PDT 24 May 04 12:44:52 PM PDT 24 10661737 ps
T258 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1672582870 May 04 12:44:37 PM PDT 24 May 04 12:44:40 PM PDT 24 190740476 ps
T259 /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.501528576 May 04 12:45:13 PM PDT 24 May 04 12:45:17 PM PDT 24 214721502 ps
T260 /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.1031099246 May 04 12:45:21 PM PDT 24 May 04 12:45:24 PM PDT 24 533331940 ps
T261 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.2039195375 May 04 12:45:00 PM PDT 24 May 04 12:45:03 PM PDT 24 114934425 ps
T262 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.2763111026 May 04 12:44:27 PM PDT 24 May 04 12:44:30 PM PDT 24 100078623 ps
T263 /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.3482870144 May 04 12:45:02 PM PDT 24 May 04 12:45:04 PM PDT 24 45809686 ps
T264 /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.775006590 May 04 12:45:01 PM PDT 24 May 04 12:45:05 PM PDT 24 146627460 ps
T265 /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.1897619291 May 04 12:45:26 PM PDT 24 May 04 12:45:27 PM PDT 24 23458236 ps
T51 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.4043704745 May 04 12:44:58 PM PDT 24 May 04 12:45:02 PM PDT 24 527780471 ps
T266 /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.2290193176 May 04 12:44:46 PM PDT 24 May 04 12:44:47 PM PDT 24 35987500 ps
T267 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.931816262 May 04 12:45:23 PM PDT 24 May 04 12:45:26 PM PDT 24 134842021 ps
T268 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.1785465611 May 04 12:45:27 PM PDT 24 May 04 12:45:29 PM PDT 24 18012355 ps
T269 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.914386259 May 04 12:44:39 PM PDT 24 May 04 12:44:40 PM PDT 24 105961729 ps
T270 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.3311375360 May 04 12:44:59 PM PDT 24 May 04 12:45:03 PM PDT 24 45994976 ps
T271 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.1007389396 May 04 12:45:22 PM PDT 24 May 04 12:45:25 PM PDT 24 95541114 ps
T272 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.3384529323 May 04 12:44:59 PM PDT 24 May 04 12:45:00 PM PDT 24 95999454 ps
T40 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.676801223 May 04 12:45:12 PM PDT 24 May 04 12:45:17 PM PDT 24 131340696 ps
T273 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.74220099 May 04 12:44:39 PM PDT 24 May 04 12:44:40 PM PDT 24 133240110 ps
T274 /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.3583707181 May 04 12:44:38 PM PDT 24 May 04 12:44:40 PM PDT 24 7855034 ps
T275 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.1791344014 May 04 12:44:58 PM PDT 24 May 04 12:45:00 PM PDT 24 23978447 ps
T276 /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.2286936310 May 04 12:45:19 PM PDT 24 May 04 12:45:20 PM PDT 24 36578122 ps
T50 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.353251552 May 04 12:44:59 PM PDT 24 May 04 12:45:07 PM PDT 24 173809340 ps
T277 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.4287337085 May 04 12:45:21 PM PDT 24 May 04 12:45:22 PM PDT 24 9817879 ps
T278 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3779613008 May 04 12:45:03 PM PDT 24 May 04 12:45:05 PM PDT 24 20807099 ps
T279 /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.4235628408 May 04 12:45:21 PM PDT 24 May 04 12:45:24 PM PDT 24 34030251 ps
T280 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.3588754607 May 04 12:44:36 PM PDT 24 May 04 12:44:38 PM PDT 24 19005131 ps
T281 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.371542721 May 04 12:45:23 PM PDT 24 May 04 12:45:25 PM PDT 24 62568479 ps
T282 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.4005213886 May 04 12:44:40 PM PDT 24 May 04 12:44:42 PM PDT 24 75237583 ps
T283 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.1758663256 May 04 12:44:46 PM PDT 24 May 04 12:44:49 PM PDT 24 398680071 ps
T284 /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.856165618 May 04 12:45:13 PM PDT 24 May 04 12:45:16 PM PDT 24 94235245 ps
T285 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1109876681 May 04 12:44:26 PM PDT 24 May 04 12:44:36 PM PDT 24 606240858 ps
T286 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.4019595407 May 04 12:45:01 PM PDT 24 May 04 12:45:02 PM PDT 24 22656781 ps
T287 /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.3406586313 May 04 12:44:18 PM PDT 24 May 04 12:44:20 PM PDT 24 100202585 ps
T288 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.570519217 May 04 12:44:34 PM PDT 24 May 04 12:44:40 PM PDT 24 144995193 ps
T289 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.2183456093 May 04 12:45:20 PM PDT 24 May 04 12:45:24 PM PDT 24 95590434 ps
T290 /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.2426669592 May 04 12:45:00 PM PDT 24 May 04 12:45:02 PM PDT 24 15199261 ps
T291 /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2332068070 May 04 12:45:20 PM PDT 24 May 04 12:45:21 PM PDT 24 7587589 ps
T292 /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.1162965456 May 04 12:45:26 PM PDT 24 May 04 12:45:27 PM PDT 24 15683161 ps
T293 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.417590756 May 04 12:45:24 PM PDT 24 May 04 12:45:29 PM PDT 24 200626449 ps
T294 /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.2268583333 May 04 12:44:35 PM PDT 24 May 04 12:44:36 PM PDT 24 14881387 ps
T295 /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.3912187941 May 04 12:45:28 PM PDT 24 May 04 12:45:29 PM PDT 24 42847755 ps
T296 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.603431715 May 04 12:45:12 PM PDT 24 May 04 12:45:13 PM PDT 24 43993727 ps
T297 /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.714549308 May 04 12:44:20 PM PDT 24 May 04 12:44:23 PM PDT 24 468220247 ps
T298 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.2517680474 May 04 12:45:03 PM PDT 24 May 04 12:45:05 PM PDT 24 106084849 ps
T299 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.623197684 May 04 12:44:59 PM PDT 24 May 04 12:45:05 PM PDT 24 171131573 ps
T45 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.1911917656 May 04 12:45:21 PM PDT 24 May 04 12:45:30 PM PDT 24 332220064 ps
T300 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.869681243 May 04 12:45:19 PM PDT 24 May 04 12:45:20 PM PDT 24 125032517 ps
T301 /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.3083013453 May 04 12:45:20 PM PDT 24 May 04 12:45:24 PM PDT 24 202492119 ps
T302 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.3640880894 May 04 12:44:35 PM PDT 24 May 04 12:44:37 PM PDT 24 273627112 ps
T303 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.3472581127 May 04 12:44:19 PM PDT 24 May 04 12:44:42 PM PDT 24 3701393828 ps
T304 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.4267986962 May 04 12:45:11 PM PDT 24 May 04 12:45:14 PM PDT 24 214603888 ps
T305 /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.1006444358 May 04 12:45:25 PM PDT 24 May 04 12:45:26 PM PDT 24 11699196 ps
T306 /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1302393308 May 04 12:45:06 PM PDT 24 May 04 12:45:09 PM PDT 24 414884778 ps
T307 /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.3540800096 May 04 12:45:18 PM PDT 24 May 04 12:45:20 PM PDT 24 119267414 ps

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.2331267359
Short name T7
Test name
Test status
Simulation time 17919060391 ps
CPU time 150.62 seconds
Started May 04 01:34:57 PM PDT 24
Finished May 04 01:37:28 PM PDT 24
Peak memory 208284 kb
Host smart-75657c95-9b5a-4596-b237-4815fc4e4e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331267359 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.2331267359
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.570227142
Short name T38
Test name
Test status
Simulation time 586467014 ps
CPU time 6.16 seconds
Started May 04 12:44:28 PM PDT 24
Finished May 04 12:44:35 PM PDT 24
Peak memory 221060 kb
Host smart-cc9f0e6f-126d-4f50-b1a8-261a5b44ae6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570227142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.570227142
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.3081072039
Short name T1
Test name
Test status
Simulation time 1082353741 ps
CPU time 9.7 seconds
Started May 04 01:34:43 PM PDT 24
Finished May 04 01:34:53 PM PDT 24
Peak memory 230208 kb
Host smart-ad931483-bb32-4da7-84fb-c4853637367f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081072039 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.3081072039
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.271440132
Short name T26
Test name
Test status
Simulation time 109035701 ps
CPU time 3.04 seconds
Started May 04 12:44:36 PM PDT 24
Finished May 04 12:44:40 PM PDT 24
Peak memory 212692 kb
Host smart-2d67e0c6-57e6-46ea-9fbb-dcead0fc9057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271440132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.271440132
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.3304452758
Short name T13
Test name
Test status
Simulation time 16378205012 ps
CPU time 60.55 seconds
Started May 04 01:34:47 PM PDT 24
Finished May 04 01:35:48 PM PDT 24
Peak memory 207740 kb
Host smart-baeeae03-468c-4377-b714-bc8c643d20fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304452758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.3304452758
Directory /workspace/9.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.2661745752
Short name T61
Test name
Test status
Simulation time 13876921 ps
CPU time 0.94 seconds
Started May 04 12:45:07 PM PDT 24
Finished May 04 12:45:08 PM PDT 24
Peak memory 204352 kb
Host smart-c7272ae2-fab8-4310-a1cd-313f45ecffde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661745752 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
2661745752
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.1350514834
Short name T20
Test name
Test status
Simulation time 557780092 ps
CPU time 2.82 seconds
Started May 04 12:44:22 PM PDT 24
Finished May 04 12:44:26 PM PDT 24
Peak memory 213772 kb
Host smart-5154196e-85c7-491b-a915-fb31ee6acca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350514834 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.1350514834
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.1876525463
Short name T4
Test name
Test status
Simulation time 786330438 ps
CPU time 14.54 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:35:05 PM PDT 24
Peak memory 207560 kb
Host smart-6e9be9d4-680a-43a9-91f9-43519deed90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876525463 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.1876525463
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.1409075815
Short name T16
Test name
Test status
Simulation time 10483261 ps
CPU time 0.74 seconds
Started May 04 01:34:45 PM PDT 24
Finished May 04 01:34:46 PM PDT 24
Peak memory 205244 kb
Host smart-88094361-fee8-4f41-b9e5-f09e72163572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409075815 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.1
409075815
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.2406323496
Short name T29
Test name
Test status
Simulation time 721295366 ps
CPU time 7.14 seconds
Started May 04 12:45:03 PM PDT 24
Finished May 04 12:45:11 PM PDT 24
Peak memory 212976 kb
Host smart-679f193a-98cb-4fc6-989c-7285d789edc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406323496 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.2406323496
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.676801223
Short name T40
Test name
Test status
Simulation time 131340696 ps
CPU time 4.57 seconds
Started May 04 12:45:12 PM PDT 24
Finished May 04 12:45:17 PM PDT 24
Peak memory 213724 kb
Host smart-624fa12e-e558-4694-8f28-32c1f9e6d90b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676801223 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe
_tl_intg_err.676801223
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.624549423
Short name T19
Test name
Test status
Simulation time 180906232 ps
CPU time 2.36 seconds
Started May 04 12:44:22 PM PDT 24
Finished May 04 12:44:25 PM PDT 24
Peak memory 215868 kb
Host smart-dba733d0-62c5-450e-8e2a-38ea44735d12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624549423 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.624549423
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.751602454
Short name T27
Test name
Test status
Simulation time 331330257 ps
CPU time 3.56 seconds
Started May 04 12:44:38 PM PDT 24
Finished May 04 12:44:42 PM PDT 24
Peak memory 212604 kb
Host smart-0d617611-9b4f-4f3c-b13f-19d7b3df84ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751602454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_
tl_intg_err.751602454
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.3958998502
Short name T37
Test name
Test status
Simulation time 179794558 ps
CPU time 7.03 seconds
Started May 04 12:45:16 PM PDT 24
Finished May 04 12:45:24 PM PDT 24
Peak memory 212528 kb
Host smart-cdcba01e-9601-4ef0-8df1-5565f28894be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958998502 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.3958998502
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.573276880
Short name T6
Test name
Test status
Simulation time 1021071223 ps
CPU time 10.51 seconds
Started May 04 01:34:41 PM PDT 24
Finished May 04 01:34:51 PM PDT 24
Peak memory 233512 kb
Host smart-e4d86af2-a20c-43d7-9c73-02476e041db5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573276880 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.573276880
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2295297770
Short name T52
Test name
Test status
Simulation time 27076252 ps
CPU time 1.59 seconds
Started May 04 12:44:59 PM PDT 24
Finished May 04 12:45:01 PM PDT 24
Peak memory 212588 kb
Host smart-6b0308ca-997c-421f-9d35-5703bcdbeab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295297770 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.2295297770
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.2382856333
Short name T49
Test name
Test status
Simulation time 183079847 ps
CPU time 5.98 seconds
Started May 04 12:45:07 PM PDT 24
Finished May 04 12:45:13 PM PDT 24
Peak memory 212564 kb
Host smart-775fc2a9-b39f-4a77-bce4-10d65c93037c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382856333 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.2382856333
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.2803495328
Short name T28
Test name
Test status
Simulation time 117463663 ps
CPU time 3.28 seconds
Started May 04 12:45:18 PM PDT 24
Finished May 04 12:45:22 PM PDT 24
Peak memory 213628 kb
Host smart-f8365778-1aa6-4851-93c6-22b878239331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803495328 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.2803495328
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.2558338835
Short name T46
Test name
Test status
Simulation time 344297829 ps
CPU time 2.88 seconds
Started May 04 12:44:35 PM PDT 24
Finished May 04 12:44:39 PM PDT 24
Peak memory 212580 kb
Host smart-feaaf01d-8f91-4a08-928b-d1a86a150f82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558338835 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.2558338835
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.3507785112
Short name T44
Test name
Test status
Simulation time 858511751 ps
CPU time 2.81 seconds
Started May 04 12:44:39 PM PDT 24
Finished May 04 12:44:42 PM PDT 24
Peak memory 212672 kb
Host smart-67579ef7-1279-4b51-b425-7b6c4e203bac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507785112 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.3507785112
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.4043704745
Short name T51
Test name
Test status
Simulation time 527780471 ps
CPU time 3.56 seconds
Started May 04 12:44:58 PM PDT 24
Finished May 04 12:45:02 PM PDT 24
Peak memory 213612 kb
Host smart-dfb95df3-4acd-45ea-ab56-0cfde453899e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043704745 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.4043704745
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.44748246
Short name T131
Test name
Test status
Simulation time 1218741588 ps
CPU time 22.2 seconds
Started May 04 01:34:47 PM PDT 24
Finished May 04 01:35:10 PM PDT 24
Peak memory 207140 kb
Host smart-d0289dcd-c683-414f-93f5-1aa37ddb74e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44748246 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.44748246
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.292997727
Short name T68
Test name
Test status
Simulation time 36742385735 ps
CPU time 158.29 seconds
Started May 04 01:34:49 PM PDT 24
Finished May 04 01:37:28 PM PDT 24
Peak memory 208436 kb
Host smart-e2750afc-02d2-4a2b-bdba-0a7474ca21a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292997727 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.292997727
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.3644529858
Short name T85
Test name
Test status
Simulation time 6279561992 ps
CPU time 17.45 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:22 PM PDT 24
Peak memory 208132 kb
Host smart-15e1c3e2-b9b0-4041-88cd-245e12823d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644529858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.3644529858
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.1587201645
Short name T107
Test name
Test status
Simulation time 1754937452 ps
CPU time 20.38 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:24 PM PDT 24
Peak memory 207744 kb
Host smart-d9ba2b3a-46ce-436a-a77c-b6eb05f4ad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587201645 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.1587201645
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.3617203899
Short name T98
Test name
Test status
Simulation time 54610809381 ps
CPU time 189.17 seconds
Started May 04 01:34:47 PM PDT 24
Finished May 04 01:37:56 PM PDT 24
Peak memory 208324 kb
Host smart-696057a2-991a-4af9-8187-44ae3f1a5360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617203899 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.3617203899
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.61460337
Short name T99
Test name
Test status
Simulation time 1870404931 ps
CPU time 25.4 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:35:16 PM PDT 24
Peak memory 208024 kb
Host smart-6de9ca5a-2556-4033-82c1-02ecee8da58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61460337 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.61460337
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.3901765347
Short name T100
Test name
Test status
Simulation time 30353164801 ps
CPU time 129.28 seconds
Started May 04 01:34:51 PM PDT 24
Finished May 04 01:37:01 PM PDT 24
Peak memory 208228 kb
Host smart-8664c63e-33b5-48ec-92c5-a98eecfbe30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901765347 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.3901765347
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.3251376425
Short name T103
Test name
Test status
Simulation time 21514711766 ps
CPU time 290.29 seconds
Started May 04 01:34:49 PM PDT 24
Finished May 04 01:39:40 PM PDT 24
Peak memory 207920 kb
Host smart-8a7e035f-62b7-4671-a9a0-e08703bdb1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251376425 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3251376425
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.2623017851
Short name T104
Test name
Test status
Simulation time 9898527821 ps
CPU time 31.7 seconds
Started May 04 01:34:48 PM PDT 24
Finished May 04 01:35:20 PM PDT 24
Peak memory 207840 kb
Host smart-d2cfa5f4-ae71-4b49-913c-23a549723bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623017851 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.2623017851
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.3315523187
Short name T24
Test name
Test status
Simulation time 564274650 ps
CPU time 17.84 seconds
Started May 04 01:34:54 PM PDT 24
Finished May 04 01:35:12 PM PDT 24
Peak memory 207864 kb
Host smart-a8cf61cd-2b93-444a-9f83-6f9ff5102834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315523187 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.3315523187
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.756051252
Short name T105
Test name
Test status
Simulation time 4386523341 ps
CPU time 26.47 seconds
Started May 04 01:34:54 PM PDT 24
Finished May 04 01:35:21 PM PDT 24
Peak memory 207192 kb
Host smart-21067654-763c-40bc-99df-f2325944f417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756051252 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.756051252
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.4192671752
Short name T10
Test name
Test status
Simulation time 45483621654 ps
CPU time 336.86 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:40:39 PM PDT 24
Peak memory 207940 kb
Host smart-bdf4fd36-92ca-4589-b2a7-ed45502746bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192671752 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.4192671752
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.2773591662
Short name T2
Test name
Test status
Simulation time 276396548 ps
CPU time 14.75 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:35:17 PM PDT 24
Peak memory 207852 kb
Host smart-a5635258-21e6-4483-93dc-d6572dedc182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773591662 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.2773591662
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.3986527248
Short name T72
Test name
Test status
Simulation time 5799581337 ps
CPU time 22.49 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:26 PM PDT 24
Peak memory 207336 kb
Host smart-4acfe9b3-940f-439b-a68f-91c405adc810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986527248 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.3986527248
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.2511274122
Short name T245
Test name
Test status
Simulation time 308489534 ps
CPU time 7.51 seconds
Started May 04 12:44:21 PM PDT 24
Finished May 04 12:44:29 PM PDT 24
Peak memory 204416 kb
Host smart-f1aa644c-270f-44d5-9630-96c80298106b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511274122 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.2511274122
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.3472581127
Short name T303
Test name
Test status
Simulation time 3701393828 ps
CPU time 22.13 seconds
Started May 04 12:44:19 PM PDT 24
Finished May 04 12:44:42 PM PDT 24
Peak memory 204356 kb
Host smart-184822f4-187a-411e-9f3e-1bbc75a3f466
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472581127 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.3472581127
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2219946887
Short name T31
Test name
Test status
Simulation time 17796228 ps
CPU time 1.03 seconds
Started May 04 12:44:22 PM PDT 24
Finished May 04 12:44:24 PM PDT 24
Peak memory 204280 kb
Host smart-fda34eb4-9fff-4b0c-b771-ce15f35bba1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219946887 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.2219946887
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.3038026909
Short name T88
Test name
Test status
Simulation time 154688613 ps
CPU time 1.14 seconds
Started May 04 12:44:19 PM PDT 24
Finished May 04 12:44:20 PM PDT 24
Peak memory 220380 kb
Host smart-cc947356-386b-424d-ad43-169a9e689f2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038026909 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.3038026909
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.1807608904
Short name T185
Test name
Test status
Simulation time 13565119 ps
CPU time 1 seconds
Started May 04 12:44:21 PM PDT 24
Finished May 04 12:44:23 PM PDT 24
Peak memory 204388 kb
Host smart-a9309ba3-82d0-4fcf-86fe-aaaf1f5677ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807608904 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.1
807608904
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2181720550
Short name T228
Test name
Test status
Simulation time 49086306 ps
CPU time 0.73 seconds
Started May 04 12:44:22 PM PDT 24
Finished May 04 12:44:23 PM PDT 24
Peak memory 204188 kb
Host smart-04ce821c-d23d-4a8e-9052-dee6c8415746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181720550 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.2
181720550
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.3406586313
Short name T287
Test name
Test status
Simulation time 100202585 ps
CPU time 1.8 seconds
Started May 04 12:44:18 PM PDT 24
Finished May 04 12:44:20 PM PDT 24
Peak memory 204356 kb
Host smart-e0965a12-b3b2-4663-8ed8-216b6e870984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406586313 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.3406586313
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.3574497776
Short name T56
Test name
Test status
Simulation time 428225391 ps
CPU time 2.16 seconds
Started May 04 12:44:16 PM PDT 24
Finished May 04 12:44:19 PM PDT 24
Peak memory 213024 kb
Host smart-88f0b2f1-b840-4295-9fb4-46b05966f865
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574497776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.3574497776
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.3117623706
Short name T231
Test name
Test status
Simulation time 172996155 ps
CPU time 4.38 seconds
Started May 04 12:44:19 PM PDT 24
Finished May 04 12:44:24 PM PDT 24
Peak memory 212916 kb
Host smart-0cb035c5-d61e-4da3-8816-c1515fdffdaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117623706 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.3117623706
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.3206935145
Short name T244
Test name
Test status
Simulation time 130178215 ps
CPU time 2.2 seconds
Started May 04 12:44:19 PM PDT 24
Finished May 04 12:44:22 PM PDT 24
Peak memory 212588 kb
Host smart-80bbfc61-a65e-4afd-b70c-1c17c8d96e56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206935145 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.3
206935145
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3226431505
Short name T252
Test name
Test status
Simulation time 222830684 ps
CPU time 2.92 seconds
Started May 04 12:44:20 PM PDT 24
Finished May 04 12:44:24 PM PDT 24
Peak memory 212496 kb
Host smart-2f6bbee8-3b7f-4d5f-b676-3f02e0bc39e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226431505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.3226431505
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.953948316
Short name T242
Test name
Test status
Simulation time 180832193 ps
CPU time 3.14 seconds
Started May 04 12:44:28 PM PDT 24
Finished May 04 12:44:31 PM PDT 24
Peak memory 204344 kb
Host smart-3273ee3f-6d09-4688-813b-d9a50dac561e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953948316 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_aliasing.953948316
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1109876681
Short name T285
Test name
Test status
Simulation time 606240858 ps
CPU time 8.98 seconds
Started May 04 12:44:26 PM PDT 24
Finished May 04 12:44:36 PM PDT 24
Peak memory 204360 kb
Host smart-ffae5687-a807-446a-afb7-2a4fed4fda33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109876681 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.1109876681
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.3984971272
Short name T63
Test name
Test status
Simulation time 14778836 ps
CPU time 0.88 seconds
Started May 04 12:44:19 PM PDT 24
Finished May 04 12:44:21 PM PDT 24
Peak memory 204276 kb
Host smart-c6c8e867-67c2-42fa-a3da-84e27524eb84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984971272 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.3984971272
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.3678902547
Short name T57
Test name
Test status
Simulation time 81379132 ps
CPU time 1.25 seconds
Started May 04 12:44:28 PM PDT 24
Finished May 04 12:44:29 PM PDT 24
Peak memory 220624 kb
Host smart-78ce73cf-fab6-4775-ac9d-e0dd7c0e05db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678902547 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.3678902547
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.3819931353
Short name T93
Test name
Test status
Simulation time 47205806 ps
CPU time 1.03 seconds
Started May 04 12:44:27 PM PDT 24
Finished May 04 12:44:28 PM PDT 24
Peak memory 204372 kb
Host smart-b209ef7e-d455-475a-9585-5f69109e49c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819931353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.3
819931353
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.2744478049
Short name T168
Test name
Test status
Simulation time 10823432 ps
CPU time 0.81 seconds
Started May 04 12:44:21 PM PDT 24
Finished May 04 12:44:23 PM PDT 24
Peak memory 204164 kb
Host smart-b20dde55-153d-4663-896a-38ae1a3d639a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744478049 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.2
744478049
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.3684263578
Short name T79
Test name
Test status
Simulation time 183501698 ps
CPU time 2.14 seconds
Started May 04 12:44:36 PM PDT 24
Finished May 04 12:44:39 PM PDT 24
Peak memory 204392 kb
Host smart-3cf495e5-814c-4a30-b6d2-0bce6854f026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684263578 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.3684263578
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.714549308
Short name T297
Test name
Test status
Simulation time 468220247 ps
CPU time 2.3 seconds
Started May 04 12:44:20 PM PDT 24
Finished May 04 12:44:23 PM PDT 24
Peak memory 212936 kb
Host smart-0108e3a7-a91b-4424-935d-8a6b43159748
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714549308 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymg
r_dpe_shadow_reg_errors.714549308
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1463929319
Short name T229
Test name
Test status
Simulation time 226199149 ps
CPU time 4.5 seconds
Started May 04 12:44:20 PM PDT 24
Finished May 04 12:44:26 PM PDT 24
Peak memory 221076 kb
Host smart-00b5ca3d-46ca-40f1-b0a0-f0ba30788d92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463929319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1463929319
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.4019595407
Short name T286
Test name
Test status
Simulation time 22656781 ps
CPU time 1 seconds
Started May 04 12:45:01 PM PDT 24
Finished May 04 12:45:02 PM PDT 24
Peak memory 204168 kb
Host smart-d8de9e57-ca9c-4329-8e42-31b6d1e4391a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019595407 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
4019595407
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.2426669592
Short name T290
Test name
Test status
Simulation time 15199261 ps
CPU time 0.88 seconds
Started May 04 12:45:00 PM PDT 24
Finished May 04 12:45:02 PM PDT 24
Peak memory 204336 kb
Host smart-3b716ae5-d055-4c18-8a13-86d52abbf3ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426669592 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
2426669592
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.4233197607
Short name T209
Test name
Test status
Simulation time 237337976 ps
CPU time 2.14 seconds
Started May 04 12:45:00 PM PDT 24
Finished May 04 12:45:02 PM PDT 24
Peak memory 204348 kb
Host smart-708780d4-9b8a-46ff-b452-241dcd24ec60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233197607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.4233197607
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.1560723997
Short name T215
Test name
Test status
Simulation time 69598011 ps
CPU time 1.78 seconds
Started May 04 12:45:00 PM PDT 24
Finished May 04 12:45:02 PM PDT 24
Peak memory 212984 kb
Host smart-03015066-6ec0-4e79-b232-c7908dee9dab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560723997 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.1560723997
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.419718280
Short name T227
Test name
Test status
Simulation time 379640059 ps
CPU time 3.29 seconds
Started May 04 12:45:00 PM PDT 24
Finished May 04 12:45:04 PM PDT 24
Peak memory 212952 kb
Host smart-905d5c92-7a1b-4c07-aa70-2cb0ad4db7f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419718280 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.419718280
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.3311375360
Short name T270
Test name
Test status
Simulation time 45994976 ps
CPU time 2.96 seconds
Started May 04 12:44:59 PM PDT 24
Finished May 04 12:45:03 PM PDT 24
Peak memory 212652 kb
Host smart-2c86dacb-3c8f-4b86-ae25-5d2c3eb822ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311375360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
3311375360
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.353251552
Short name T50
Test name
Test status
Simulation time 173809340 ps
CPU time 6.64 seconds
Started May 04 12:44:59 PM PDT 24
Finished May 04 12:45:07 PM PDT 24
Peak memory 212664 kb
Host smart-027877c1-837b-4d83-8636-844de35372fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353251552 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe
_tl_intg_err.353251552
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.1321832976
Short name T86
Test name
Test status
Simulation time 185057036 ps
CPU time 1.68 seconds
Started May 04 12:44:59 PM PDT 24
Finished May 04 12:45:01 PM PDT 24
Peak memory 212664 kb
Host smart-41c2107d-915e-477c-a8d9-95ba90f25056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321832976 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.1321832976
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.3384529323
Short name T272
Test name
Test status
Simulation time 95999454 ps
CPU time 1 seconds
Started May 04 12:44:59 PM PDT 24
Finished May 04 12:45:00 PM PDT 24
Peak memory 204272 kb
Host smart-3d989e50-8af6-4632-ad71-3a9883656f58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384529323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
3384529323
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1889534612
Short name T109
Test name
Test status
Simulation time 71526170 ps
CPU time 0.84 seconds
Started May 04 12:44:58 PM PDT 24
Finished May 04 12:44:59 PM PDT 24
Peak memory 204252 kb
Host smart-7e611ebf-4504-4122-89cf-9f42c16d487c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889534612 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
1889534612
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.2423447839
Short name T178
Test name
Test status
Simulation time 32907355 ps
CPU time 1.12 seconds
Started May 04 12:44:58 PM PDT 24
Finished May 04 12:45:00 PM PDT 24
Peak memory 204440 kb
Host smart-77f2a420-6282-4225-8b0b-8d265ea9ccef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423447839 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.2423447839
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.3279352353
Short name T204
Test name
Test status
Simulation time 60579196 ps
CPU time 2.14 seconds
Started May 04 12:44:57 PM PDT 24
Finished May 04 12:45:00 PM PDT 24
Peak memory 212880 kb
Host smart-24ae9b6e-569d-4a13-bae6-17b97ed33449
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279352353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.3279352353
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.2215499451
Short name T210
Test name
Test status
Simulation time 211870703 ps
CPU time 3.45 seconds
Started May 04 12:44:59 PM PDT 24
Finished May 04 12:45:03 PM PDT 24
Peak memory 212968 kb
Host smart-abaf5f08-6710-46b2-9cc5-75593db1cac2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215499451 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.2215499451
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.3535959262
Short name T42
Test name
Test status
Simulation time 54972155 ps
CPU time 2.12 seconds
Started May 04 12:45:00 PM PDT 24
Finished May 04 12:45:03 PM PDT 24
Peak memory 204340 kb
Host smart-6b43d50b-ff06-45f1-be39-e450a8984cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535959262 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
3535959262
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.2039195375
Short name T261
Test name
Test status
Simulation time 114934425 ps
CPU time 2.94 seconds
Started May 04 12:45:00 PM PDT 24
Finished May 04 12:45:03 PM PDT 24
Peak memory 212512 kb
Host smart-221e70f6-d907-4dc8-8a3e-313b60e2da36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039195375 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.2039195375
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3779613008
Short name T278
Test name
Test status
Simulation time 20807099 ps
CPU time 1.64 seconds
Started May 04 12:45:03 PM PDT 24
Finished May 04 12:45:05 PM PDT 24
Peak memory 220828 kb
Host smart-64c4eb21-4ffe-43f4-beb0-47925da6b9db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779613008 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.3779613008
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.2517680474
Short name T298
Test name
Test status
Simulation time 106084849 ps
CPU time 1.26 seconds
Started May 04 12:45:03 PM PDT 24
Finished May 04 12:45:05 PM PDT 24
Peak memory 204380 kb
Host smart-4237eb53-9457-4c8a-8c6b-66b0cfe19bb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517680474 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
2517680474
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.3086888091
Short name T192
Test name
Test status
Simulation time 16370110 ps
CPU time 0.8 seconds
Started May 04 12:45:04 PM PDT 24
Finished May 04 12:45:05 PM PDT 24
Peak memory 204224 kb
Host smart-80b6f593-9878-4501-a246-4a80ed2c410a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086888091 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
3086888091
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.3482870144
Short name T263
Test name
Test status
Simulation time 45809686 ps
CPU time 1.27 seconds
Started May 04 12:45:02 PM PDT 24
Finished May 04 12:45:04 PM PDT 24
Peak memory 204356 kb
Host smart-13148767-ea93-44c1-8f3e-6d0c8b0efa93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482870144 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.3482870144
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.3973139104
Short name T213
Test name
Test status
Simulation time 589348942 ps
CPU time 1.95 seconds
Started May 04 12:45:00 PM PDT 24
Finished May 04 12:45:02 PM PDT 24
Peak memory 212872 kb
Host smart-c30f1884-0b57-4be4-820a-c657424917b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973139104 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.3973139104
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.601925534
Short name T43
Test name
Test status
Simulation time 213620152 ps
CPU time 3.18 seconds
Started May 04 12:45:05 PM PDT 24
Finished May 04 12:45:08 PM PDT 24
Peak memory 212684 kb
Host smart-ca32de13-40be-43a8-ad07-d3a1416a5a23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601925534 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.601925534
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.2045064708
Short name T41
Test name
Test status
Simulation time 174767836 ps
CPU time 6.83 seconds
Started May 04 12:45:04 PM PDT 24
Finished May 04 12:45:11 PM PDT 24
Peak memory 213696 kb
Host smart-de083045-b308-4a7f-9b3c-bc7c467a7c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045064708 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.2045064708
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.1226754376
Short name T207
Test name
Test status
Simulation time 19593408 ps
CPU time 1.06 seconds
Started May 04 12:45:03 PM PDT 24
Finished May 04 12:45:04 PM PDT 24
Peak memory 215288 kb
Host smart-f3fafdb9-7e6f-48fa-9052-cb3295989ac7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226754376 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.1226754376
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.3820101341
Short name T254
Test name
Test status
Simulation time 65246344 ps
CPU time 0.87 seconds
Started May 04 12:45:05 PM PDT 24
Finished May 04 12:45:06 PM PDT 24
Peak memory 204280 kb
Host smart-12b2ddad-5e36-4a2b-bb25-49fe71bf846a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820101341 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
3820101341
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.772349788
Short name T184
Test name
Test status
Simulation time 101942801 ps
CPU time 1.93 seconds
Started May 04 12:45:03 PM PDT 24
Finished May 04 12:45:05 PM PDT 24
Peak memory 204396 kb
Host smart-4f73ad4c-8c9e-434a-a90c-239f0cb911ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772349788 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.k
eymgr_dpe_same_csr_outstanding.772349788
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.3244368885
Short name T225
Test name
Test status
Simulation time 597292406 ps
CPU time 2.64 seconds
Started May 04 12:45:07 PM PDT 24
Finished May 04 12:45:10 PM PDT 24
Peak memory 216528 kb
Host smart-10080ec5-757f-4844-9b81-311aae631ab9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244368885 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.3244368885
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1390438177
Short name T95
Test name
Test status
Simulation time 197447005 ps
CPU time 5.24 seconds
Started May 04 12:45:09 PM PDT 24
Finished May 04 12:45:15 PM PDT 24
Peak memory 212972 kb
Host smart-4f67f621-c7ba-49fa-9e7c-5958b07aaa2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390438177 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1390438177
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1302393308
Short name T306
Test name
Test status
Simulation time 414884778 ps
CPU time 2.7 seconds
Started May 04 12:45:06 PM PDT 24
Finished May 04 12:45:09 PM PDT 24
Peak memory 220740 kb
Host smart-940ca8b0-2076-46f6-a716-2894cc6e082a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302393308 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
1302393308
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1102138099
Short name T255
Test name
Test status
Simulation time 20418599 ps
CPU time 1.29 seconds
Started May 04 12:45:14 PM PDT 24
Finished May 04 12:45:16 PM PDT 24
Peak memory 220276 kb
Host smart-879db225-2596-4db0-b3aa-667814c9dcb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102138099 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.1102138099
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.603431715
Short name T296
Test name
Test status
Simulation time 43993727 ps
CPU time 1.29 seconds
Started May 04 12:45:12 PM PDT 24
Finished May 04 12:45:13 PM PDT 24
Peak memory 204328 kb
Host smart-e59baa81-6266-4ffb-9a9a-4f78d2ab5827
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603431715 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.603431715
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.1329083506
Short name T226
Test name
Test status
Simulation time 12592958 ps
CPU time 0.85 seconds
Started May 04 12:45:12 PM PDT 24
Finished May 04 12:45:14 PM PDT 24
Peak memory 204192 kb
Host smart-9e041032-9c49-49cd-a420-328db9a20b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329083506 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
1329083506
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.661917250
Short name T197
Test name
Test status
Simulation time 195181149 ps
CPU time 1.34 seconds
Started May 04 12:45:13 PM PDT 24
Finished May 04 12:45:14 PM PDT 24
Peak memory 204316 kb
Host smart-64c11788-fb28-4711-b88a-19dbedd06894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661917250 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_dpe_same_csr_outstanding.661917250
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.3773465894
Short name T179
Test name
Test status
Simulation time 68608128 ps
CPU time 1.78 seconds
Started May 04 12:45:07 PM PDT 24
Finished May 04 12:45:10 PM PDT 24
Peak memory 212888 kb
Host smart-876174ad-f97b-4cc8-a142-7998a87e0144
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773465894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.3773465894
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.501528576
Short name T259
Test name
Test status
Simulation time 214721502 ps
CPU time 3.53 seconds
Started May 04 12:45:13 PM PDT 24
Finished May 04 12:45:17 PM PDT 24
Peak memory 213016 kb
Host smart-b49c25b5-900b-45cb-af8d-c39d133c61fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501528576 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.501528576
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.2118007837
Short name T21
Test name
Test status
Simulation time 38744016 ps
CPU time 1.53 seconds
Started May 04 12:45:13 PM PDT 24
Finished May 04 12:45:15 PM PDT 24
Peak memory 212680 kb
Host smart-b6f3249a-556f-48cf-b33b-b4c46be610f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118007837 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
2118007837
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.4267986962
Short name T304
Test name
Test status
Simulation time 214603888 ps
CPU time 2.66 seconds
Started May 04 12:45:11 PM PDT 24
Finished May 04 12:45:14 PM PDT 24
Peak memory 213588 kb
Host smart-f6f84850-435a-48d7-bb7c-f6671e107779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267986962 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.4267986962
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.408403529
Short name T206
Test name
Test status
Simulation time 136191576 ps
CPU time 1.42 seconds
Started May 04 12:45:13 PM PDT 24
Finished May 04 12:45:15 PM PDT 24
Peak memory 212712 kb
Host smart-906d45a5-2dfa-47d4-96f6-06827aef1f57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408403529 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.408403529
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.2225563706
Short name T76
Test name
Test status
Simulation time 54160853 ps
CPU time 0.83 seconds
Started May 04 12:45:12 PM PDT 24
Finished May 04 12:45:13 PM PDT 24
Peak memory 204260 kb
Host smart-783f23a6-412a-4a9c-83c3-f0b83c1b017d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225563706 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
2225563706
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2529640060
Short name T223
Test name
Test status
Simulation time 200173220 ps
CPU time 0.9 seconds
Started May 04 12:45:13 PM PDT 24
Finished May 04 12:45:14 PM PDT 24
Peak memory 204212 kb
Host smart-007a4934-f040-4b07-b1a4-9474139de03c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529640060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
2529640060
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.856165618
Short name T284
Test name
Test status
Simulation time 94235245 ps
CPU time 3.25 seconds
Started May 04 12:45:13 PM PDT 24
Finished May 04 12:45:16 PM PDT 24
Peak memory 204376 kb
Host smart-a62d7875-0ca0-4662-929b-645bbc756723
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856165618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.k
eymgr_dpe_same_csr_outstanding.856165618
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.3338428619
Short name T194
Test name
Test status
Simulation time 61093820 ps
CPU time 2.13 seconds
Started May 04 12:45:17 PM PDT 24
Finished May 04 12:45:19 PM PDT 24
Peak memory 212948 kb
Host smart-c73cebe1-621f-47b0-ab57-8d4fc51b87fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338428619 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.3338428619
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.4102633021
Short name T220
Test name
Test status
Simulation time 467755487 ps
CPU time 4.64 seconds
Started May 04 12:45:12 PM PDT 24
Finished May 04 12:45:17 PM PDT 24
Peak memory 212940 kb
Host smart-02696c3f-0f00-4efa-8fe9-a30d9f755357
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102633021 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.4102633021
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.1634044976
Short name T181
Test name
Test status
Simulation time 64031321 ps
CPU time 1.58 seconds
Started May 04 12:45:13 PM PDT 24
Finished May 04 12:45:15 PM PDT 24
Peak memory 212648 kb
Host smart-b987f8f5-0737-43f0-ba5e-710218baa68e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634044976 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
1634044976
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.683247452
Short name T54
Test name
Test status
Simulation time 39695473 ps
CPU time 1.24 seconds
Started May 04 12:45:22 PM PDT 24
Finished May 04 12:45:23 PM PDT 24
Peak memory 204432 kb
Host smart-2a22cfc5-86d1-4927-b7bf-842b2f6f2f07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683247452 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.683247452
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.177744478
Short name T170
Test name
Test status
Simulation time 16633273 ps
CPU time 1.12 seconds
Started May 04 12:45:18 PM PDT 24
Finished May 04 12:45:20 PM PDT 24
Peak memory 204312 kb
Host smart-30dd1067-095a-4d30-bb94-ed6d16d2a56e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177744478 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.177744478
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.2286936310
Short name T276
Test name
Test status
Simulation time 36578122 ps
CPU time 0.71 seconds
Started May 04 12:45:19 PM PDT 24
Finished May 04 12:45:20 PM PDT 24
Peak memory 204172 kb
Host smart-a56c6e09-ecfd-4735-8e18-04a9260f448c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286936310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.
2286936310
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.4235628408
Short name T279
Test name
Test status
Simulation time 34030251 ps
CPU time 1.79 seconds
Started May 04 12:45:21 PM PDT 24
Finished May 04 12:45:24 PM PDT 24
Peak memory 204288 kb
Host smart-1dfff4cb-cffc-4e86-8e18-a7d8e7118e6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235628408 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.4235628408
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.1368027316
Short name T161
Test name
Test status
Simulation time 1268019852 ps
CPU time 3.45 seconds
Started May 04 12:45:14 PM PDT 24
Finished May 04 12:45:18 PM PDT 24
Peak memory 212996 kb
Host smart-d3c9a7bc-9160-4c01-afa2-114519d40966
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368027316 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.1368027316
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.202282845
Short name T91
Test name
Test status
Simulation time 1311854278 ps
CPU time 6.05 seconds
Started May 04 12:45:13 PM PDT 24
Finished May 04 12:45:20 PM PDT 24
Peak memory 212944 kb
Host smart-a83eace2-52c3-449f-8f14-cce70a095798
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202282845 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.202282845
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2384153584
Short name T232
Test name
Test status
Simulation time 80939658 ps
CPU time 2.99 seconds
Started May 04 12:45:13 PM PDT 24
Finished May 04 12:45:17 PM PDT 24
Peak memory 212660 kb
Host smart-5d47ee42-69cf-4c04-a627-16561392657d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384153584 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
2384153584
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.371542721
Short name T281
Test name
Test status
Simulation time 62568479 ps
CPU time 1.51 seconds
Started May 04 12:45:23 PM PDT 24
Finished May 04 12:45:25 PM PDT 24
Peak memory 212632 kb
Host smart-9a30ba68-1666-4b49-b126-cc477fcd0279
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371542721 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.371542721
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.869681243
Short name T300
Test name
Test status
Simulation time 125032517 ps
CPU time 1.04 seconds
Started May 04 12:45:19 PM PDT 24
Finished May 04 12:45:20 PM PDT 24
Peak memory 204380 kb
Host smart-b4147b30-05b4-4ae4-afa0-916eb6fcdd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869681243 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.869681243
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.1049178589
Short name T224
Test name
Test status
Simulation time 11072753 ps
CPU time 0.84 seconds
Started May 04 12:45:21 PM PDT 24
Finished May 04 12:45:22 PM PDT 24
Peak memory 204224 kb
Host smart-fb8a030e-8064-4a67-a493-ed2a7b49083d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049178589 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
1049178589
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.3003090080
Short name T219
Test name
Test status
Simulation time 61585697 ps
CPU time 1.11 seconds
Started May 04 12:45:19 PM PDT 24
Finished May 04 12:45:20 PM PDT 24
Peak memory 204392 kb
Host smart-944214bb-62aa-4663-9628-4b3cfd7104ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003090080 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.3003090080
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.3307043258
Short name T92
Test name
Test status
Simulation time 183030394 ps
CPU time 1.37 seconds
Started May 04 12:45:20 PM PDT 24
Finished May 04 12:45:22 PM PDT 24
Peak memory 212876 kb
Host smart-f357b0fc-af37-47f4-b31c-7d20499d4134
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307043258 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.3307043258
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.417590756
Short name T293
Test name
Test status
Simulation time 200626449 ps
CPU time 4.56 seconds
Started May 04 12:45:24 PM PDT 24
Finished May 04 12:45:29 PM PDT 24
Peak memory 212904 kb
Host smart-ca29737d-ae6d-41c7-a516-e57952a6a496
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417590756 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.417590756
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.1007389396
Short name T271
Test name
Test status
Simulation time 95541114 ps
CPU time 2.99 seconds
Started May 04 12:45:22 PM PDT 24
Finished May 04 12:45:25 PM PDT 24
Peak memory 214924 kb
Host smart-8c3c0e5a-608b-4c96-b21d-561dde0c7d98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007389396 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
1007389396
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2705086422
Short name T217
Test name
Test status
Simulation time 40920486 ps
CPU time 1.31 seconds
Started May 04 12:45:20 PM PDT 24
Finished May 04 12:45:22 PM PDT 24
Peak memory 204392 kb
Host smart-3cee1d17-f9ce-49f2-a8c9-dbc50cf0b288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705086422 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.2705086422
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.98318077
Short name T198
Test name
Test status
Simulation time 40970608 ps
CPU time 0.97 seconds
Started May 04 12:45:19 PM PDT 24
Finished May 04 12:45:21 PM PDT 24
Peak memory 204256 kb
Host smart-a240a9eb-4a1e-4006-adbe-2efeff2f0329
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98318077 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.98318077
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.1206192766
Short name T62
Test name
Test status
Simulation time 42837248 ps
CPU time 0.76 seconds
Started May 04 12:45:22 PM PDT 24
Finished May 04 12:45:23 PM PDT 24
Peak memory 204172 kb
Host smart-15c888ad-b510-4ed5-b955-bd93cf80d4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206192766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
1206192766
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.3788024578
Short name T77
Test name
Test status
Simulation time 100283226 ps
CPU time 1.48 seconds
Started May 04 12:45:18 PM PDT 24
Finished May 04 12:45:20 PM PDT 24
Peak memory 204380 kb
Host smart-36433a8d-b573-42ee-84dc-ce60dbbe7e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788024578 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.3788024578
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.3540800096
Short name T307
Test name
Test status
Simulation time 119267414 ps
CPU time 1.39 seconds
Started May 04 12:45:18 PM PDT 24
Finished May 04 12:45:20 PM PDT 24
Peak memory 212940 kb
Host smart-584bca3f-9ed0-4a64-bc9c-b5fc31fc21f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540800096 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.3540800096
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.3083013453
Short name T301
Test name
Test status
Simulation time 202492119 ps
CPU time 2.92 seconds
Started May 04 12:45:20 PM PDT 24
Finished May 04 12:45:24 PM PDT 24
Peak memory 212952 kb
Host smart-a4b0afe0-0ec5-42ed-ad1a-d6d883c51a52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083013453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.3083013453
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.4041833261
Short name T32
Test name
Test status
Simulation time 169595839 ps
CPU time 2.62 seconds
Started May 04 12:45:20 PM PDT 24
Finished May 04 12:45:23 PM PDT 24
Peak memory 212624 kb
Host smart-ac7dc157-679f-42d2-9f91-9a3092937174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041833261 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
4041833261
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1099769076
Short name T39
Test name
Test status
Simulation time 132899536 ps
CPU time 5.23 seconds
Started May 04 12:45:21 PM PDT 24
Finished May 04 12:45:27 PM PDT 24
Peak memory 213744 kb
Host smart-541ce054-8b62-4539-b4df-a479167ee1ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099769076 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.1099769076
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.3241095530
Short name T191
Test name
Test status
Simulation time 235363930 ps
CPU time 1.26 seconds
Started May 04 12:45:24 PM PDT 24
Finished May 04 12:45:26 PM PDT 24
Peak memory 212644 kb
Host smart-afbdf90e-0a5c-4bc8-9ee9-c8de3577f608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241095530 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.3241095530
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.4092870132
Short name T190
Test name
Test status
Simulation time 400451898 ps
CPU time 1.01 seconds
Started May 04 12:45:22 PM PDT 24
Finished May 04 12:45:24 PM PDT 24
Peak memory 204240 kb
Host smart-299302c4-9535-4366-ad6f-4a1d2a254805
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092870132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
4092870132
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.2556292581
Short name T253
Test name
Test status
Simulation time 11680483 ps
CPU time 0.8 seconds
Started May 04 12:45:18 PM PDT 24
Finished May 04 12:45:20 PM PDT 24
Peak memory 204200 kb
Host smart-7415d679-86c1-44c7-82fc-d624ba29e1bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556292581 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
2556292581
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.1031099246
Short name T260
Test name
Test status
Simulation time 533331940 ps
CPU time 2.97 seconds
Started May 04 12:45:21 PM PDT 24
Finished May 04 12:45:24 PM PDT 24
Peak memory 204324 kb
Host smart-514a3e1d-0bcf-4391-b75c-753cca2ababe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031099246 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.1031099246
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.931816262
Short name T267
Test name
Test status
Simulation time 134842021 ps
CPU time 2.62 seconds
Started May 04 12:45:23 PM PDT 24
Finished May 04 12:45:26 PM PDT 24
Peak memory 212948 kb
Host smart-bbf85aa9-cda6-4b1a-b249-09041b2881df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931816262 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keym
gr_dpe_shadow_reg_errors.931816262
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1826638631
Short name T248
Test name
Test status
Simulation time 262904371 ps
CPU time 5.55 seconds
Started May 04 12:45:22 PM PDT 24
Finished May 04 12:45:28 PM PDT 24
Peak memory 212480 kb
Host smart-d7808422-9e30-4048-957b-fefae347cf48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826638631 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1826638631
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.2183456093
Short name T289
Test name
Test status
Simulation time 95590434 ps
CPU time 3.34 seconds
Started May 04 12:45:20 PM PDT 24
Finished May 04 12:45:24 PM PDT 24
Peak memory 212604 kb
Host smart-51f04139-34a4-49ac-b0cf-db45201d47a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183456093 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
2183456093
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.1911917656
Short name T45
Test name
Test status
Simulation time 332220064 ps
CPU time 8.98 seconds
Started May 04 12:45:21 PM PDT 24
Finished May 04 12:45:30 PM PDT 24
Peak memory 213756 kb
Host smart-5da4ed16-9f7d-469e-8c6b-0000154e3aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911917656 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.1911917656
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.2345655893
Short name T233
Test name
Test status
Simulation time 306070232 ps
CPU time 5.72 seconds
Started May 04 12:44:36 PM PDT 24
Finished May 04 12:44:42 PM PDT 24
Peak memory 204456 kb
Host smart-4e43c1c0-4734-4bd3-8fb6-f26c3ca2979e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345655893 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.2345655893
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.1759469900
Short name T236
Test name
Test status
Simulation time 1448520929 ps
CPU time 6.7 seconds
Started May 04 12:44:28 PM PDT 24
Finished May 04 12:44:35 PM PDT 24
Peak memory 204376 kb
Host smart-14dee37f-e7e2-4201-aec2-3fc71aac77af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759469900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.1759469900
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2078809100
Short name T180
Test name
Test status
Simulation time 44297683 ps
CPU time 1.01 seconds
Started May 04 12:44:25 PM PDT 24
Finished May 04 12:44:26 PM PDT 24
Peak memory 204288 kb
Host smart-2101d843-61b9-4516-8f25-d222e9268229
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078809100 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.2078809100
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.3588754607
Short name T280
Test name
Test status
Simulation time 19005131 ps
CPU time 1.15 seconds
Started May 04 12:44:36 PM PDT 24
Finished May 04 12:44:38 PM PDT 24
Peak memory 204400 kb
Host smart-aadc2964-e995-40d7-9271-eeff1aaef0a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588754607 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.3588754607
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2380071866
Short name T30
Test name
Test status
Simulation time 55169743 ps
CPU time 1.01 seconds
Started May 04 12:44:27 PM PDT 24
Finished May 04 12:44:28 PM PDT 24
Peak memory 204312 kb
Host smart-d2518da4-f741-4172-baf4-f89ba5a1b7b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380071866 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.2
380071866
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.2859595350
Short name T247
Test name
Test status
Simulation time 17877873 ps
CPU time 0.78 seconds
Started May 04 12:44:36 PM PDT 24
Finished May 04 12:44:37 PM PDT 24
Peak memory 204248 kb
Host smart-65c41fee-fb20-4052-8005-ff502f54c529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859595350 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.2
859595350
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.3640880894
Short name T302
Test name
Test status
Simulation time 273627112 ps
CPU time 2.37 seconds
Started May 04 12:44:35 PM PDT 24
Finished May 04 12:44:37 PM PDT 24
Peak memory 204360 kb
Host smart-b229b752-4c37-4b2c-99bc-a29ac7beb739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640880894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.3640880894
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.2763111026
Short name T262
Test name
Test status
Simulation time 100078623 ps
CPU time 2.82 seconds
Started May 04 12:44:27 PM PDT 24
Finished May 04 12:44:30 PM PDT 24
Peak memory 212952 kb
Host smart-8f520471-eed2-4204-a952-4fc774f7811a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763111026 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.2763111026
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.3248737023
Short name T234
Test name
Test status
Simulation time 42174717 ps
CPU time 0.85 seconds
Started May 04 12:45:22 PM PDT 24
Finished May 04 12:45:23 PM PDT 24
Peak memory 203784 kb
Host smart-b74af7ff-c4ca-4edc-bad3-f89ea31cc3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248737023 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
3248737023
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2332068070
Short name T291
Test name
Test status
Simulation time 7587589 ps
CPU time 0.77 seconds
Started May 04 12:45:20 PM PDT 24
Finished May 04 12:45:21 PM PDT 24
Peak memory 204260 kb
Host smart-70c488c1-c4a2-487b-9c4a-ea545a4a5833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332068070 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
2332068070
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.953038826
Short name T89
Test name
Test status
Simulation time 12044432 ps
CPU time 0.84 seconds
Started May 04 12:45:21 PM PDT 24
Finished May 04 12:45:22 PM PDT 24
Peak memory 204228 kb
Host smart-1a39ec47-ab37-455a-99fa-aae024011254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953038826 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.953038826
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.1586806879
Short name T167
Test name
Test status
Simulation time 40557522 ps
CPU time 0.83 seconds
Started May 04 12:45:19 PM PDT 24
Finished May 04 12:45:20 PM PDT 24
Peak memory 204240 kb
Host smart-d1085708-81af-4ab1-8127-230870b5c1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586806879 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
1586806879
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.881589524
Short name T195
Test name
Test status
Simulation time 43932795 ps
CPU time 0.86 seconds
Started May 04 12:45:24 PM PDT 24
Finished May 04 12:45:26 PM PDT 24
Peak memory 204272 kb
Host smart-af4cc73f-642c-4e6c-bb4d-e5754b254e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881589524 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.881589524
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.2077502984
Short name T176
Test name
Test status
Simulation time 10632391 ps
CPU time 0.81 seconds
Started May 04 12:45:20 PM PDT 24
Finished May 04 12:45:22 PM PDT 24
Peak memory 204176 kb
Host smart-e9b84f28-68eb-47fd-a2d7-5be2aa3696f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077502984 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
2077502984
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.4287337085
Short name T277
Test name
Test status
Simulation time 9817879 ps
CPU time 0.69 seconds
Started May 04 12:45:21 PM PDT 24
Finished May 04 12:45:22 PM PDT 24
Peak memory 204180 kb
Host smart-cf03929f-0bf9-45be-b9cd-22816d9d440e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287337085 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
4287337085
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.618342651
Short name T171
Test name
Test status
Simulation time 45400994 ps
CPU time 0.84 seconds
Started May 04 12:45:25 PM PDT 24
Finished May 04 12:45:27 PM PDT 24
Peak memory 204256 kb
Host smart-32167be4-c9e5-4044-b29b-54dc5ee981e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618342651 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.618342651
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.2800900113
Short name T203
Test name
Test status
Simulation time 30998979 ps
CPU time 0.85 seconds
Started May 04 12:45:25 PM PDT 24
Finished May 04 12:45:26 PM PDT 24
Peak memory 204136 kb
Host smart-1ec24dba-7218-4989-8db7-b5f7633495f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800900113 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
2800900113
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.1729442413
Short name T110
Test name
Test status
Simulation time 43014245 ps
CPU time 0.84 seconds
Started May 04 12:45:24 PM PDT 24
Finished May 04 12:45:25 PM PDT 24
Peak memory 204248 kb
Host smart-36366680-534f-46e4-8092-4324360c7611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729442413 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
1729442413
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.1883959521
Short name T94
Test name
Test status
Simulation time 2117848553 ps
CPU time 5.25 seconds
Started May 04 12:44:33 PM PDT 24
Finished May 04 12:44:38 PM PDT 24
Peak memory 204364 kb
Host smart-91991507-642e-4eb3-9862-5116069c4b51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883959521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.1883959521
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.4221802845
Short name T216
Test name
Test status
Simulation time 822964154 ps
CPU time 11.64 seconds
Started May 04 12:44:34 PM PDT 24
Finished May 04 12:44:46 PM PDT 24
Peak memory 204420 kb
Host smart-36d3ea24-2bd1-4678-af0d-ed8b178499a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221802845 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.4221802845
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.3662041629
Short name T251
Test name
Test status
Simulation time 65659098 ps
CPU time 1.06 seconds
Started May 04 12:44:37 PM PDT 24
Finished May 04 12:44:39 PM PDT 24
Peak memory 204380 kb
Host smart-ce2842ba-6557-42c4-949a-ad2f9a6925ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662041629 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.3662041629
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.914386259
Short name T269
Test name
Test status
Simulation time 105961729 ps
CPU time 1.28 seconds
Started May 04 12:44:39 PM PDT 24
Finished May 04 12:44:40 PM PDT 24
Peak memory 212656 kb
Host smart-b0ab83ce-adf4-4d43-a97b-0e0c0714c239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914386259 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.914386259
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.1025256046
Short name T202
Test name
Test status
Simulation time 47904443 ps
CPU time 1.18 seconds
Started May 04 12:44:34 PM PDT 24
Finished May 04 12:44:35 PM PDT 24
Peak memory 204356 kb
Host smart-eee1c3e2-39f2-49d4-91a0-a5745c4a423b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025256046 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.1
025256046
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.2268583333
Short name T294
Test name
Test status
Simulation time 14881387 ps
CPU time 0.75 seconds
Started May 04 12:44:35 PM PDT 24
Finished May 04 12:44:36 PM PDT 24
Peak memory 204196 kb
Host smart-7c9895ec-5903-4929-b6b6-5344300cb87c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268583333 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.2
268583333
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.3655232230
Short name T188
Test name
Test status
Simulation time 108019389 ps
CPU time 2.12 seconds
Started May 04 12:44:39 PM PDT 24
Finished May 04 12:44:41 PM PDT 24
Peak memory 204340 kb
Host smart-6573ef9f-a64c-4bc4-be2c-3fe84ecac9b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655232230 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.3655232230
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3482485753
Short name T193
Test name
Test status
Simulation time 90628239 ps
CPU time 2.3 seconds
Started May 04 12:44:34 PM PDT 24
Finished May 04 12:44:37 PM PDT 24
Peak memory 212972 kb
Host smart-83805636-8eab-4874-b294-8480608499f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482485753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3482485753
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3036754263
Short name T55
Test name
Test status
Simulation time 117585713 ps
CPU time 3.24 seconds
Started May 04 12:44:33 PM PDT 24
Finished May 04 12:44:37 PM PDT 24
Peak memory 212960 kb
Host smart-be2c5fb8-f994-4cab-b390-fb286ce301b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036754263 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3036754263
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.570519217
Short name T288
Test name
Test status
Simulation time 144995193 ps
CPU time 5.2 seconds
Started May 04 12:44:34 PM PDT 24
Finished May 04 12:44:40 PM PDT 24
Peak memory 214732 kb
Host smart-5638e72c-bf2a-4d6d-ad97-92b85abc406a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570519217 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.570519217
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.4220361485
Short name T230
Test name
Test status
Simulation time 99728354 ps
CPU time 2.85 seconds
Started May 04 12:44:34 PM PDT 24
Finished May 04 12:44:37 PM PDT 24
Peak memory 213588 kb
Host smart-84be8ef3-9298-4a33-901c-6ee57b16d512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220361485 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.4220361485
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.2615566768
Short name T241
Test name
Test status
Simulation time 28656120 ps
CPU time 0.73 seconds
Started May 04 12:45:28 PM PDT 24
Finished May 04 12:45:29 PM PDT 24
Peak memory 204180 kb
Host smart-b4c29675-5d7b-4e87-8084-39fcabec6c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615566768 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
2615566768
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.3912187941
Short name T295
Test name
Test status
Simulation time 42847755 ps
CPU time 0.83 seconds
Started May 04 12:45:28 PM PDT 24
Finished May 04 12:45:29 PM PDT 24
Peak memory 204256 kb
Host smart-794efe62-ba33-4c35-ab1a-e699767a5aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912187941 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
3912187941
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.3135356963
Short name T243
Test name
Test status
Simulation time 53887102 ps
CPU time 0.69 seconds
Started May 04 12:45:25 PM PDT 24
Finished May 04 12:45:26 PM PDT 24
Peak memory 204172 kb
Host smart-93e46792-adf6-4588-9b44-1723aa70c2bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135356963 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
3135356963
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.1095608805
Short name T201
Test name
Test status
Simulation time 19153478 ps
CPU time 0.82 seconds
Started May 04 12:45:27 PM PDT 24
Finished May 04 12:45:28 PM PDT 24
Peak memory 204240 kb
Host smart-fc6556f7-ecdb-4718-97a4-40f76964f094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095608805 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
1095608805
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.2465322638
Short name T214
Test name
Test status
Simulation time 45406190 ps
CPU time 0.79 seconds
Started May 04 12:45:27 PM PDT 24
Finished May 04 12:45:28 PM PDT 24
Peak memory 204224 kb
Host smart-0b92603f-47ec-46be-96dc-05faea6c85ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465322638 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
2465322638
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.1006444358
Short name T305
Test name
Test status
Simulation time 11699196 ps
CPU time 0.86 seconds
Started May 04 12:45:25 PM PDT 24
Finished May 04 12:45:26 PM PDT 24
Peak memory 204228 kb
Host smart-a14efaba-58e4-40b0-a5ff-08d48c1dad56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006444358 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
1006444358
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.154410551
Short name T249
Test name
Test status
Simulation time 36514952 ps
CPU time 0.74 seconds
Started May 04 12:45:24 PM PDT 24
Finished May 04 12:45:25 PM PDT 24
Peak memory 204212 kb
Host smart-0dfcea6b-01a1-40e0-825d-c27e588f4c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154410551 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.154410551
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3490777417
Short name T218
Test name
Test status
Simulation time 20914399 ps
CPU time 0.72 seconds
Started May 04 12:45:26 PM PDT 24
Finished May 04 12:45:27 PM PDT 24
Peak memory 204172 kb
Host smart-284a2501-275f-4e60-86d2-988fb8a0cc7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490777417 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
3490777417
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.1818830542
Short name T200
Test name
Test status
Simulation time 20793188 ps
CPU time 0.72 seconds
Started May 04 12:45:28 PM PDT 24
Finished May 04 12:45:29 PM PDT 24
Peak memory 204224 kb
Host smart-d65019ed-82eb-4769-a644-3d1ff2264966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818830542 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
1818830542
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3857783177
Short name T246
Test name
Test status
Simulation time 29584150 ps
CPU time 0.78 seconds
Started May 04 12:45:27 PM PDT 24
Finished May 04 12:45:28 PM PDT 24
Peak memory 204196 kb
Host smart-878ccce8-05f7-4c70-a839-2b0fa7a61df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857783177 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
3857783177
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1871487403
Short name T96
Test name
Test status
Simulation time 42914644 ps
CPU time 3.03 seconds
Started May 04 12:44:40 PM PDT 24
Finished May 04 12:44:43 PM PDT 24
Peak memory 204380 kb
Host smart-6a9f544f-3963-4c09-8d3e-c9b13228ef0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871487403 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.1871487403
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.2881178146
Short name T240
Test name
Test status
Simulation time 94668642 ps
CPU time 4.39 seconds
Started May 04 12:44:38 PM PDT 24
Finished May 04 12:44:43 PM PDT 24
Peak memory 204380 kb
Host smart-a4fe3bef-08a8-4f38-999b-93bdb901bc98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881178146 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.2881178146
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.2052197572
Short name T182
Test name
Test status
Simulation time 26187909 ps
CPU time 1 seconds
Started May 04 12:44:39 PM PDT 24
Finished May 04 12:44:40 PM PDT 24
Peak memory 204344 kb
Host smart-2c909d30-1a85-4153-b34f-3088cdf45bdf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052197572 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.2052197572
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.4087548538
Short name T211
Test name
Test status
Simulation time 182742162 ps
CPU time 1.21 seconds
Started May 04 12:44:40 PM PDT 24
Finished May 04 12:44:42 PM PDT 24
Peak memory 204412 kb
Host smart-42f4d2bb-aa10-4653-bf4d-6fcdd81b7a95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087548538 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.4087548538
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.382388144
Short name T164
Test name
Test status
Simulation time 37523851 ps
CPU time 0.99 seconds
Started May 04 12:44:40 PM PDT 24
Finished May 04 12:44:42 PM PDT 24
Peak memory 204184 kb
Host smart-d9caefc8-262f-47da-9736-2f0a43359834
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382388144 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.382388144
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.303849463
Short name T34
Test name
Test status
Simulation time 15103133 ps
CPU time 0.79 seconds
Started May 04 12:44:38 PM PDT 24
Finished May 04 12:44:39 PM PDT 24
Peak memory 204128 kb
Host smart-a48b1cc0-1a02-42c5-82d6-828b36735597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303849463 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.303849463
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.3931798376
Short name T60
Test name
Test status
Simulation time 101689427 ps
CPU time 1.4 seconds
Started May 04 12:44:42 PM PDT 24
Finished May 04 12:44:43 PM PDT 24
Peak memory 204408 kb
Host smart-fa6e63f2-7290-428b-83d7-7b4aed8bf27d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931798376 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.3931798376
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.1178522016
Short name T169
Test name
Test status
Simulation time 64208314 ps
CPU time 1.98 seconds
Started May 04 12:44:38 PM PDT 24
Finished May 04 12:44:40 PM PDT 24
Peak memory 212868 kb
Host smart-6503ec45-aea3-449f-a015-682b00c03020
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178522016 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.1178522016
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1858692791
Short name T237
Test name
Test status
Simulation time 225586388 ps
CPU time 3.18 seconds
Started May 04 12:44:38 PM PDT 24
Finished May 04 12:44:42 PM PDT 24
Peak memory 212924 kb
Host smart-52a9b198-5591-4923-994b-ade760f03779
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858692791 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1858692791
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.2549278603
Short name T238
Test name
Test status
Simulation time 117376691 ps
CPU time 1.55 seconds
Started May 04 12:44:39 PM PDT 24
Finished May 04 12:44:41 PM PDT 24
Peak memory 212632 kb
Host smart-2d9de5b7-d77b-4693-964d-fbc902a33baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549278603 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.2
549278603
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3436293083
Short name T35
Test name
Test status
Simulation time 12857342 ps
CPU time 0.85 seconds
Started May 04 12:45:25 PM PDT 24
Finished May 04 12:45:26 PM PDT 24
Peak memory 204236 kb
Host smart-51ae445d-59e1-414b-b39a-7a65454c4fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436293083 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
3436293083
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.1785465611
Short name T268
Test name
Test status
Simulation time 18012355 ps
CPU time 0.86 seconds
Started May 04 12:45:27 PM PDT 24
Finished May 04 12:45:29 PM PDT 24
Peak memory 204236 kb
Host smart-2509b86d-73db-46b9-9873-4971bbf55951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785465611 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
1785465611
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.895226549
Short name T256
Test name
Test status
Simulation time 10197880 ps
CPU time 0.87 seconds
Started May 04 12:45:25 PM PDT 24
Finished May 04 12:45:27 PM PDT 24
Peak memory 204272 kb
Host smart-2cc88578-127f-475d-8ef3-42cbb58bb018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895226549 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.895226549
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.1897619291
Short name T265
Test name
Test status
Simulation time 23458236 ps
CPU time 0.86 seconds
Started May 04 12:45:26 PM PDT 24
Finished May 04 12:45:27 PM PDT 24
Peak memory 204236 kb
Host smart-e6817fd7-50f7-4f09-9391-4bbd0645ccfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897619291 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
1897619291
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.1913240861
Short name T250
Test name
Test status
Simulation time 14080332 ps
CPU time 0.81 seconds
Started May 04 12:45:26 PM PDT 24
Finished May 04 12:45:27 PM PDT 24
Peak memory 204200 kb
Host smart-704d9fbd-4b17-4b45-88ae-9c083450f283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913240861 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
1913240861
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.3224062980
Short name T175
Test name
Test status
Simulation time 37357398 ps
CPU time 0.78 seconds
Started May 04 12:45:26 PM PDT 24
Finished May 04 12:45:27 PM PDT 24
Peak memory 204168 kb
Host smart-5812f479-6d00-4ef5-a0b0-a8e299d95bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224062980 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
3224062980
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.2521826528
Short name T174
Test name
Test status
Simulation time 51184910 ps
CPU time 0.7 seconds
Started May 04 12:45:25 PM PDT 24
Finished May 04 12:45:27 PM PDT 24
Peak memory 204192 kb
Host smart-edccb34f-44e6-4447-ab92-20a6cbbc13e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521826528 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
2521826528
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.748699986
Short name T165
Test name
Test status
Simulation time 37377120 ps
CPU time 0.84 seconds
Started May 04 12:45:26 PM PDT 24
Finished May 04 12:45:28 PM PDT 24
Peak memory 204264 kb
Host smart-8a8698b7-dbee-4cb2-85ca-7cdb35e352f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748699986 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.748699986
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.1162965456
Short name T292
Test name
Test status
Simulation time 15683161 ps
CPU time 0.74 seconds
Started May 04 12:45:26 PM PDT 24
Finished May 04 12:45:27 PM PDT 24
Peak memory 204204 kb
Host smart-b0e9a565-ba79-43ee-bda1-ad2c1139cdab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162965456 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
1162965456
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.413835377
Short name T163
Test name
Test status
Simulation time 28765246 ps
CPU time 0.81 seconds
Started May 04 12:45:25 PM PDT 24
Finished May 04 12:45:26 PM PDT 24
Peak memory 204228 kb
Host smart-56ee4feb-9680-4063-b821-a2c794481296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413835377 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.413835377
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.4005213886
Short name T282
Test name
Test status
Simulation time 75237583 ps
CPU time 1.38 seconds
Started May 04 12:44:40 PM PDT 24
Finished May 04 12:44:42 PM PDT 24
Peak memory 220736 kb
Host smart-8d9567fb-3dcf-4fa2-a0b1-b99fc856d769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005213886 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.4005213886
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.74220099
Short name T273
Test name
Test status
Simulation time 133240110 ps
CPU time 0.92 seconds
Started May 04 12:44:39 PM PDT 24
Finished May 04 12:44:40 PM PDT 24
Peak memory 204224 kb
Host smart-fbcf8ce5-b4f2-438f-9851-7ae6ad0ada21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74220099 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.74220099
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.3583707181
Short name T274
Test name
Test status
Simulation time 7855034 ps
CPU time 0.77 seconds
Started May 04 12:44:38 PM PDT 24
Finished May 04 12:44:40 PM PDT 24
Peak memory 204152 kb
Host smart-2449bc9b-7e0c-4f7f-bb1a-b1bcacceba8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583707181 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.3
583707181
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.3807353993
Short name T235
Test name
Test status
Simulation time 320616753 ps
CPU time 2.23 seconds
Started May 04 12:44:38 PM PDT 24
Finished May 04 12:44:41 PM PDT 24
Peak memory 204368 kb
Host smart-f51bb2b9-087a-4285-8838-85c5948c23ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807353993 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.3807353993
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1672582870
Short name T258
Test name
Test status
Simulation time 190740476 ps
CPU time 1.84 seconds
Started May 04 12:44:37 PM PDT 24
Finished May 04 12:44:40 PM PDT 24
Peak memory 212940 kb
Host smart-ab22f6b3-e36a-4517-9764-19d8ababf378
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672582870 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.1672582870
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.1258962959
Short name T222
Test name
Test status
Simulation time 471514001 ps
CPU time 8.09 seconds
Started May 04 12:44:38 PM PDT 24
Finished May 04 12:44:47 PM PDT 24
Peak memory 212976 kb
Host smart-d14b472e-177b-433f-96a7-24f10482af89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258962959 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.1258962959
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2151508350
Short name T36
Test name
Test status
Simulation time 200015421 ps
CPU time 3.04 seconds
Started May 04 12:44:38 PM PDT 24
Finished May 04 12:44:41 PM PDT 24
Peak memory 212568 kb
Host smart-52d6e448-0fab-4abc-b0dc-1b2ec427f78a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151508350 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.2
151508350
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.3731904321
Short name T58
Test name
Test status
Simulation time 335188933 ps
CPU time 1.23 seconds
Started May 04 12:44:46 PM PDT 24
Finished May 04 12:44:47 PM PDT 24
Peak memory 214960 kb
Host smart-d2fd51e2-4c67-476b-bdfa-4fde39c14a3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731904321 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.3731904321
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.3510805220
Short name T162
Test name
Test status
Simulation time 11635894 ps
CPU time 1.08 seconds
Started May 04 12:44:44 PM PDT 24
Finished May 04 12:44:46 PM PDT 24
Peak memory 204368 kb
Host smart-dceba2b5-3a86-4774-a690-974b788b5d18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510805220 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.3
510805220
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.586371663
Short name T196
Test name
Test status
Simulation time 35976653 ps
CPU time 0.75 seconds
Started May 04 12:44:46 PM PDT 24
Finished May 04 12:44:47 PM PDT 24
Peak memory 204256 kb
Host smart-afa0ffb4-7f92-46f9-9398-bd1e0494e940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586371663 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.586371663
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.1091408975
Short name T78
Test name
Test status
Simulation time 283167667 ps
CPU time 2.84 seconds
Started May 04 12:44:48 PM PDT 24
Finished May 04 12:44:51 PM PDT 24
Peak memory 204428 kb
Host smart-e9ff5bda-17d1-4e0c-ae61-8a57e778ba36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091408975 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.1091408975
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.1741647070
Short name T205
Test name
Test status
Simulation time 262092719 ps
CPU time 1.78 seconds
Started May 04 12:44:46 PM PDT 24
Finished May 04 12:44:48 PM PDT 24
Peak memory 212964 kb
Host smart-6e773ece-050e-4f0b-9ed9-4f3745691924
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741647070 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.1741647070
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.848567215
Short name T53
Test name
Test status
Simulation time 1259595965 ps
CPU time 3.67 seconds
Started May 04 12:44:46 PM PDT 24
Finished May 04 12:44:50 PM PDT 24
Peak memory 212976 kb
Host smart-d74ca5d1-ea74-46d4-a659-2b8fe82f9b29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848567215 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.848567215
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.415828109
Short name T33
Test name
Test status
Simulation time 59061246 ps
CPU time 1.85 seconds
Started May 04 12:44:45 PM PDT 24
Finished May 04 12:44:47 PM PDT 24
Peak memory 212572 kb
Host smart-d5687a13-0981-42d1-b1da-8541d6a61e76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415828109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.415828109
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.2514947842
Short name T47
Test name
Test status
Simulation time 338340298 ps
CPU time 3.7 seconds
Started May 04 12:44:47 PM PDT 24
Finished May 04 12:44:51 PM PDT 24
Peak memory 213612 kb
Host smart-10449ef2-a80d-4942-b583-f7e8aa6cfc4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514947842 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.2514947842
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.1533418353
Short name T90
Test name
Test status
Simulation time 59340329 ps
CPU time 1.24 seconds
Started May 04 12:44:51 PM PDT 24
Finished May 04 12:44:53 PM PDT 24
Peak memory 220200 kb
Host smart-4402cd4e-82ec-4ccc-81db-9a66a129e57a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533418353 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.1533418353
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.773625111
Short name T166
Test name
Test status
Simulation time 23230455 ps
CPU time 0.97 seconds
Started May 04 12:44:51 PM PDT 24
Finished May 04 12:44:52 PM PDT 24
Peak memory 204176 kb
Host smart-7a455f0b-ae19-472e-8bdb-225230c206c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773625111 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.773625111
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.2290193176
Short name T266
Test name
Test status
Simulation time 35987500 ps
CPU time 0.7 seconds
Started May 04 12:44:46 PM PDT 24
Finished May 04 12:44:47 PM PDT 24
Peak memory 204200 kb
Host smart-e266b338-292d-4a9a-8ce2-dec800c77f4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290193176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.2
290193176
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.2099976146
Short name T212
Test name
Test status
Simulation time 34169080 ps
CPU time 1.76 seconds
Started May 04 12:44:52 PM PDT 24
Finished May 04 12:44:54 PM PDT 24
Peak memory 204328 kb
Host smart-ec9e5109-f0eb-497d-aafe-bf1791933068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099976146 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.2099976146
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.398966399
Short name T59
Test name
Test status
Simulation time 315749769 ps
CPU time 1.91 seconds
Started May 04 12:44:46 PM PDT 24
Finished May 04 12:44:49 PM PDT 24
Peak memory 212988 kb
Host smart-eab73d7f-fcb6-4b50-9ea2-978ee8516dc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398966399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymg
r_dpe_shadow_reg_errors.398966399
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2840916006
Short name T239
Test name
Test status
Simulation time 69309164 ps
CPU time 2.53 seconds
Started May 04 12:44:47 PM PDT 24
Finished May 04 12:44:50 PM PDT 24
Peak memory 212884 kb
Host smart-9c839e15-4f34-42e3-ae04-89de5de9f8e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840916006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2840916006
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.2075819599
Short name T187
Test name
Test status
Simulation time 87119117 ps
CPU time 1.65 seconds
Started May 04 12:44:48 PM PDT 24
Finished May 04 12:44:49 PM PDT 24
Peak memory 212560 kb
Host smart-37c7c4e2-0823-48d1-b4e3-0a38c013507f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075819599 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.2
075819599
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.1758663256
Short name T283
Test name
Test status
Simulation time 398680071 ps
CPU time 2.96 seconds
Started May 04 12:44:46 PM PDT 24
Finished May 04 12:44:49 PM PDT 24
Peak memory 213768 kb
Host smart-c9f7f5ca-f388-4537-81e6-bdebc2fb634b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758663256 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.1758663256
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.840031012
Short name T87
Test name
Test status
Simulation time 80690557 ps
CPU time 0.88 seconds
Started May 04 12:44:59 PM PDT 24
Finished May 04 12:45:00 PM PDT 24
Peak memory 204324 kb
Host smart-03e22139-a08d-4447-bd31-f81784969fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840031012 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.840031012
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.9171718
Short name T172
Test name
Test status
Simulation time 181051928 ps
CPU time 0.99 seconds
Started May 04 12:44:54 PM PDT 24
Finished May 04 12:44:55 PM PDT 24
Peak memory 204168 kb
Host smart-e33afa14-87ec-47e8-a1e9-9cff1a36addd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9171718 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.9171718
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.75233133
Short name T257
Test name
Test status
Simulation time 10661737 ps
CPU time 0.83 seconds
Started May 04 12:44:51 PM PDT 24
Finished May 04 12:44:52 PM PDT 24
Peak memory 204216 kb
Host smart-aca70595-da29-42a6-80fd-9925a3c14b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75233133 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.75233133
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.311770768
Short name T173
Test name
Test status
Simulation time 38289770 ps
CPU time 1.82 seconds
Started May 04 12:44:54 PM PDT 24
Finished May 04 12:44:56 PM PDT 24
Peak memory 204320 kb
Host smart-671edc7b-6a2f-4c1c-a291-e76bef925876
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311770768 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_dpe_same_csr_outstanding.311770768
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.241044174
Short name T183
Test name
Test status
Simulation time 71276638 ps
CPU time 2.34 seconds
Started May 04 12:44:53 PM PDT 24
Finished May 04 12:44:55 PM PDT 24
Peak memory 212972 kb
Host smart-c8335e9b-36a4-4b33-8cce-d461fbd61145
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241044174 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymg
r_dpe_shadow_reg_errors.241044174
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.196749247
Short name T189
Test name
Test status
Simulation time 200194994 ps
CPU time 3.26 seconds
Started May 04 12:44:52 PM PDT 24
Finished May 04 12:44:56 PM PDT 24
Peak memory 212880 kb
Host smart-c5e89f2e-de08-45ee-bd27-041caf97f03d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196749247 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.196749247
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.2794186969
Short name T177
Test name
Test status
Simulation time 104535272 ps
CPU time 2.73 seconds
Started May 04 12:44:51 PM PDT 24
Finished May 04 12:44:54 PM PDT 24
Peak memory 212572 kb
Host smart-fd676fb7-9fb5-4242-b840-4950672bd8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794186969 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.2
794186969
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.2748774905
Short name T48
Test name
Test status
Simulation time 335454467 ps
CPU time 3.48 seconds
Started May 04 12:44:51 PM PDT 24
Finished May 04 12:44:55 PM PDT 24
Peak memory 213696 kb
Host smart-31cf76d3-0a84-4f42-bb6f-4fd86174a82d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748774905 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.2748774905
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.1791344014
Short name T275
Test name
Test status
Simulation time 23978447 ps
CPU time 1.73 seconds
Started May 04 12:44:58 PM PDT 24
Finished May 04 12:45:00 PM PDT 24
Peak memory 217084 kb
Host smart-e1c7df20-1268-42f1-9283-ae03938355e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791344014 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.1791344014
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.675250020
Short name T199
Test name
Test status
Simulation time 27726559 ps
CPU time 1.07 seconds
Started May 04 12:44:58 PM PDT 24
Finished May 04 12:44:59 PM PDT 24
Peak memory 204280 kb
Host smart-5eb4551d-0485-4510-b50a-ac8a96ce2ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675250020 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.675250020
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.2150716947
Short name T208
Test name
Test status
Simulation time 125377271 ps
CPU time 0.82 seconds
Started May 04 12:44:58 PM PDT 24
Finished May 04 12:44:59 PM PDT 24
Peak memory 204204 kb
Host smart-1491b6f4-f972-4a42-917d-a7a46fc0a75c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150716947 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.2
150716947
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.775006590
Short name T264
Test name
Test status
Simulation time 146627460 ps
CPU time 3.59 seconds
Started May 04 12:45:01 PM PDT 24
Finished May 04 12:45:05 PM PDT 24
Peak memory 204468 kb
Host smart-4e8c4626-b07e-4f39-9127-2d915100a3de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775006590 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ke
ymgr_dpe_same_csr_outstanding.775006590
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.307588791
Short name T186
Test name
Test status
Simulation time 502038383 ps
CPU time 3.33 seconds
Started May 04 12:45:00 PM PDT 24
Finished May 04 12:45:04 PM PDT 24
Peak memory 212976 kb
Host smart-3cca7199-138f-46bd-8601-8f10bb73bd1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307588791 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymg
r_dpe_shadow_reg_errors.307588791
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.623197684
Short name T299
Test name
Test status
Simulation time 171131573 ps
CPU time 5.56 seconds
Started May 04 12:44:59 PM PDT 24
Finished May 04 12:45:05 PM PDT 24
Peak memory 212948 kb
Host smart-da0cacec-3ee1-438f-ae1d-55f195884baa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623197684 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.623197684
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.61734881
Short name T221
Test name
Test status
Simulation time 181301899 ps
CPU time 1.49 seconds
Started May 04 12:44:59 PM PDT 24
Finished May 04 12:45:01 PM PDT 24
Peak memory 220464 kb
Host smart-450c3942-a807-4062-b5ad-0fa3faf3ac6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61734881 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.61734881
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.1654549672
Short name T23
Test name
Test status
Simulation time 5788781009 ps
CPU time 11.92 seconds
Started May 04 01:34:45 PM PDT 24
Finished May 04 01:34:57 PM PDT 24
Peak memory 232544 kb
Host smart-42a1d4e6-be16-4d64-be7d-2bbae765d87e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654549672 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.1654549672
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.3949847693
Short name T120
Test name
Test status
Simulation time 31901731 ps
CPU time 0.67 seconds
Started May 04 01:34:41 PM PDT 24
Finished May 04 01:34:42 PM PDT 24
Peak memory 205236 kb
Host smart-96a0989f-8f88-4e15-bf15-3344a8d9e73e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949847693 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.3
949847693
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.3680324136
Short name T82
Test name
Test status
Simulation time 1014547715 ps
CPU time 14.33 seconds
Started May 04 01:34:44 PM PDT 24
Finished May 04 01:34:58 PM PDT 24
Peak memory 206096 kb
Host smart-b5f9f34b-97ab-4590-a86a-6421ece7b4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680324136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.3680324136
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.3364569722
Short name T18
Test name
Test status
Simulation time 71541592 ps
CPU time 0.77 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:05 PM PDT 24
Peak memory 204672 kb
Host smart-063cfe24-0113-4c69-af6c-c93422a86c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364569722 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
3364569722
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.1846457553
Short name T136
Test name
Test status
Simulation time 39132016 ps
CPU time 0.78 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:34:51 PM PDT 24
Peak memory 205264 kb
Host smart-4c40f931-9d32-49d3-800a-d115ac836466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846457553 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
1846457553
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.3729779346
Short name T80
Test name
Test status
Simulation time 948733569 ps
CPU time 10.65 seconds
Started May 04 01:34:51 PM PDT 24
Finished May 04 01:35:02 PM PDT 24
Peak memory 206132 kb
Host smart-02d2b663-9463-423d-bffa-6e54685edbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729779346 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.3729779346
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.4216911354
Short name T119
Test name
Test status
Simulation time 25723168 ps
CPU time 0.74 seconds
Started May 04 01:34:48 PM PDT 24
Finished May 04 01:34:50 PM PDT 24
Peak memory 205312 kb
Host smart-6d7b470a-8d4d-421f-b0a6-38d63f0e9087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216911354 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
4216911354
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.2943884529
Short name T127
Test name
Test status
Simulation time 15306829 ps
CPU time 0.74 seconds
Started May 04 01:34:51 PM PDT 24
Finished May 04 01:34:52 PM PDT 24
Peak memory 205276 kb
Host smart-a24bc267-f61a-45e6-aa02-9609f59d50c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943884529 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
2943884529
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.1497864801
Short name T160
Test name
Test status
Simulation time 26543825 ps
CPU time 0.93 seconds
Started May 04 01:34:48 PM PDT 24
Finished May 04 01:34:49 PM PDT 24
Peak memory 205428 kb
Host smart-a4040c4a-41d1-4c09-82e1-309f5fdb3bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497864801 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
1497864801
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.4089559722
Short name T114
Test name
Test status
Simulation time 21490763 ps
CPU time 0.97 seconds
Started May 04 01:34:47 PM PDT 24
Finished May 04 01:34:49 PM PDT 24
Peak memory 205360 kb
Host smart-acc93ea6-de97-4ed9-a54e-9d0050fb617c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089559722 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
4089559722
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.2747727038
Short name T141
Test name
Test status
Simulation time 10043371 ps
CPU time 0.72 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:34:52 PM PDT 24
Peak memory 205112 kb
Host smart-ceae83c6-2d58-468c-a3db-0bd6c04f124c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747727038 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
2747727038
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.1665781408
Short name T3
Test name
Test status
Simulation time 46576743305 ps
CPU time 144.74 seconds
Started May 04 01:34:48 PM PDT 24
Finished May 04 01:37:13 PM PDT 24
Peak memory 208388 kb
Host smart-798f0bc8-d80e-4c64-84fd-8ee6cf99579a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665781408 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.1665781408
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.2667721500
Short name T154
Test name
Test status
Simulation time 9201508 ps
CPU time 0.73 seconds
Started May 04 01:34:52 PM PDT 24
Finished May 04 01:34:53 PM PDT 24
Peak memory 205256 kb
Host smart-cd5ae9cd-7e13-454c-8578-afe00d7951a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667721500 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
2667721500
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.3845065409
Short name T106
Test name
Test status
Simulation time 767571102 ps
CPU time 21.5 seconds
Started May 04 01:34:51 PM PDT 24
Finished May 04 01:35:13 PM PDT 24
Peak memory 208060 kb
Host smart-8c7f8112-25af-4eb9-a301-4a88d6e01a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845065409 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.3845065409
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.2019777705
Short name T115
Test name
Test status
Simulation time 14600885 ps
CPU time 0.84 seconds
Started May 04 01:34:49 PM PDT 24
Finished May 04 01:34:50 PM PDT 24
Peak memory 205332 kb
Host smart-fe0ad8ad-fe81-4378-a65b-aee613f8887f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019777705 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
2019777705
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.373338922
Short name T122
Test name
Test status
Simulation time 10455687 ps
CPU time 0.73 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:34:51 PM PDT 24
Peak memory 205324 kb
Host smart-5a1c9125-08a8-4bd4-93c5-3d9ce03e4633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373338922 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.373338922
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.1197654252
Short name T126
Test name
Test status
Simulation time 25292089 ps
CPU time 1.05 seconds
Started May 04 01:34:45 PM PDT 24
Finished May 04 01:34:46 PM PDT 24
Peak memory 205492 kb
Host smart-800830ba-1dad-41b6-9114-820c7cfb81b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197654252 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.1
197654252
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.2765117619
Short name T5
Test name
Test status
Simulation time 392532937 ps
CPU time 8.76 seconds
Started May 04 01:34:44 PM PDT 24
Finished May 04 01:34:53 PM PDT 24
Peak memory 230716 kb
Host smart-5ca1e434-21e1-48af-bc92-04561fdae464
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765117619 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.2765117619
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.3091875786
Short name T102
Test name
Test status
Simulation time 211958783 ps
CPU time 11.45 seconds
Started May 04 01:34:43 PM PDT 24
Finished May 04 01:34:54 PM PDT 24
Peak memory 207480 kb
Host smart-59de61c3-93b2-4c3d-8cc4-9d93580dc64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091875786 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.3091875786
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.4244350357
Short name T146
Test name
Test status
Simulation time 15450794 ps
CPU time 0.91 seconds
Started May 04 01:34:52 PM PDT 24
Finished May 04 01:34:53 PM PDT 24
Peak memory 205332 kb
Host smart-72bee2b0-62f3-4326-bf4f-89c08a12a21e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244350357 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
4244350357
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.3121790725
Short name T73
Test name
Test status
Simulation time 12014979436 ps
CPU time 36.97 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:35:28 PM PDT 24
Peak memory 207512 kb
Host smart-84f419da-07e4-4278-a870-a059b8cea92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121790725 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.3121790725
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.1507765502
Short name T17
Test name
Test status
Simulation time 26760747 ps
CPU time 0.92 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:04 PM PDT 24
Peak memory 205420 kb
Host smart-ce56c231-33dd-405b-99a3-e74ee856e3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507765502 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
1507765502
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.146997923
Short name T81
Test name
Test status
Simulation time 1432742915 ps
CPU time 13.7 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:35:04 PM PDT 24
Peak memory 207920 kb
Host smart-f0179bfa-ad63-4fce-bfd3-2d2fd79f75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146997923 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.146997923
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.2586054145
Short name T113
Test name
Test status
Simulation time 20478740 ps
CPU time 0.85 seconds
Started May 04 01:34:51 PM PDT 24
Finished May 04 01:34:52 PM PDT 24
Peak memory 205324 kb
Host smart-df1c775c-c323-4e5d-a98f-14b334e6af2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586054145 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
2586054145
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.1024909062
Short name T84
Test name
Test status
Simulation time 2993765927 ps
CPU time 28.27 seconds
Started May 04 01:34:47 PM PDT 24
Finished May 04 01:35:16 PM PDT 24
Peak memory 207564 kb
Host smart-fba39fe7-60a9-4f68-a9d1-83798725fbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024909062 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.1024909062
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.203088267
Short name T125
Test name
Test status
Simulation time 11914757 ps
CPU time 0.9 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:34:51 PM PDT 24
Peak memory 205312 kb
Host smart-fbc1a055-4da2-4df5-a7e2-85569543005c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203088267 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.203088267
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.3874179031
Short name T139
Test name
Test status
Simulation time 10676273 ps
CPU time 0.77 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:05 PM PDT 24
Peak memory 204820 kb
Host smart-e8fbde4d-7e74-491b-a7ef-b123b5888229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874179031 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
3874179031
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.2627463950
Short name T128
Test name
Test status
Simulation time 2713662100 ps
CPU time 22.43 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:35:13 PM PDT 24
Peak memory 208376 kb
Host smart-d26cf4ed-ce30-435f-9fa7-a99b41d09dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627463950 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.2627463950
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.2883803171
Short name T69
Test name
Test status
Simulation time 20496992 ps
CPU time 0.82 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:05 PM PDT 24
Peak memory 205288 kb
Host smart-40ca4f58-6c0e-4506-91df-fc75a8072d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883803171 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
2883803171
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.546123536
Short name T149
Test name
Test status
Simulation time 1288363633 ps
CPU time 14.87 seconds
Started May 04 01:34:51 PM PDT 24
Finished May 04 01:35:06 PM PDT 24
Peak memory 206080 kb
Host smart-72cddfb7-f106-4b07-a1e2-8c79867af9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546123536 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.546123536
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.1385658551
Short name T64
Test name
Test status
Simulation time 100456972 ps
CPU time 0.87 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:05 PM PDT 24
Peak memory 204944 kb
Host smart-413b6bdd-23f8-4b63-ab1a-354a6485a27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385658551 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
1385658551
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.3344813116
Short name T112
Test name
Test status
Simulation time 8768864 ps
CPU time 0.74 seconds
Started May 04 01:34:49 PM PDT 24
Finished May 04 01:34:51 PM PDT 24
Peak memory 205256 kb
Host smart-988416e9-5862-4689-ab10-ff1fdf39c351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344813116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
3344813116
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.2412140432
Short name T97
Test name
Test status
Simulation time 367241454 ps
CPU time 13.83 seconds
Started May 04 01:34:48 PM PDT 24
Finished May 04 01:35:02 PM PDT 24
Peak memory 207980 kb
Host smart-726b8bd7-c327-46d0-b5f1-0af29f51b282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412140432 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.2412140432
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.2725403890
Short name T129
Test name
Test status
Simulation time 29641161 ps
CPU time 0.75 seconds
Started May 04 01:34:57 PM PDT 24
Finished May 04 01:34:58 PM PDT 24
Peak memory 205296 kb
Host smart-64096f9e-ec58-4311-bf51-0fbbff7d9a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725403890 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
2725403890
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.707332645
Short name T142
Test name
Test status
Simulation time 12459485 ps
CPU time 0.8 seconds
Started May 04 01:34:58 PM PDT 24
Finished May 04 01:34:59 PM PDT 24
Peak memory 205332 kb
Host smart-203b59ed-eeb1-4e60-bd85-06d3aa4a5ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707332645 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.707332645
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.1984865087
Short name T15
Test name
Test status
Simulation time 11002198 ps
CPU time 0.85 seconds
Started May 04 01:34:42 PM PDT 24
Finished May 04 01:34:43 PM PDT 24
Peak memory 205324 kb
Host smart-4de4a327-f027-462e-b7cf-3e9a8e6f28ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984865087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.1
984865087
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.2258374555
Short name T22
Test name
Test status
Simulation time 787683987 ps
CPU time 5.15 seconds
Started May 04 01:34:45 PM PDT 24
Finished May 04 01:34:50 PM PDT 24
Peak memory 230420 kb
Host smart-cd6570e3-0b02-4784-aaa9-d57bae3f46ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258374555 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.2258374555
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.2846765961
Short name T101
Test name
Test status
Simulation time 19337142597 ps
CPU time 85.65 seconds
Started May 04 01:34:42 PM PDT 24
Finished May 04 01:36:08 PM PDT 24
Peak memory 208404 kb
Host smart-356f3c04-a65d-4a46-84ec-0b3c1bf47912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846765961 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.2846765961
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.164219643
Short name T155
Test name
Test status
Simulation time 14431980 ps
CPU time 0.78 seconds
Started May 04 01:34:54 PM PDT 24
Finished May 04 01:34:55 PM PDT 24
Peak memory 205220 kb
Host smart-21a47a48-3aa7-4516-abde-affc96b32dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164219643 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.164219643
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.2235781470
Short name T152
Test name
Test status
Simulation time 9755838 ps
CPU time 0.7 seconds
Started May 04 01:34:55 PM PDT 24
Finished May 04 01:34:56 PM PDT 24
Peak memory 205340 kb
Host smart-5a56a9dd-1e90-4944-8ab7-f3fceaeb48c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235781470 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
2235781470
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.2435851653
Short name T121
Test name
Test status
Simulation time 40602549 ps
CPU time 0.82 seconds
Started May 04 01:34:55 PM PDT 24
Finished May 04 01:34:56 PM PDT 24
Peak memory 205324 kb
Host smart-ff90d169-13c1-444f-b147-7145deae14d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435851653 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
2435851653
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.2203778923
Short name T123
Test name
Test status
Simulation time 699312417 ps
CPU time 17.02 seconds
Started May 04 01:34:57 PM PDT 24
Finished May 04 01:35:14 PM PDT 24
Peak memory 207340 kb
Host smart-ca419f82-c150-4bff-8eb0-41fed43ccfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203778923 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.2203778923
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.3087642101
Short name T153
Test name
Test status
Simulation time 51627553 ps
CPU time 0.72 seconds
Started May 04 01:34:55 PM PDT 24
Finished May 04 01:34:56 PM PDT 24
Peak memory 205332 kb
Host smart-2444d71a-73bf-449c-9b79-30f2d0b16bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087642101 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
3087642101
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.1064476629
Short name T111
Test name
Test status
Simulation time 23853963 ps
CPU time 0.74 seconds
Started May 04 01:34:56 PM PDT 24
Finished May 04 01:34:58 PM PDT 24
Peak memory 205348 kb
Host smart-17354070-b4a3-4423-9e88-c6ecc399e52e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064476629 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
1064476629
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.2203006817
Short name T11
Test name
Test status
Simulation time 6254938326 ps
CPU time 53.12 seconds
Started May 04 01:34:53 PM PDT 24
Finished May 04 01:35:47 PM PDT 24
Peak memory 207944 kb
Host smart-d17e64d1-7a59-4e22-bcc1-c16a634ea80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203006817 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.2203006817
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.621959388
Short name T133
Test name
Test status
Simulation time 10509250 ps
CPU time 0.72 seconds
Started May 04 01:34:56 PM PDT 24
Finished May 04 01:34:57 PM PDT 24
Peak memory 205344 kb
Host smart-053991ab-cedb-4d9a-a036-7ca296b8649b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621959388 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.621959388
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.4238384129
Short name T9
Test name
Test status
Simulation time 930679820 ps
CPU time 19.34 seconds
Started May 04 01:34:54 PM PDT 24
Finished May 04 01:35:14 PM PDT 24
Peak memory 206136 kb
Host smart-7f940ab2-cba3-4b17-8012-9a8f7ab2895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238384129 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.4238384129
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.2441094723
Short name T138
Test name
Test status
Simulation time 22025005 ps
CPU time 0.87 seconds
Started May 04 01:34:56 PM PDT 24
Finished May 04 01:34:57 PM PDT 24
Peak memory 205324 kb
Host smart-8e943592-c229-4b0f-89a2-52511346e49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441094723 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
2441094723
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.1927561103
Short name T66
Test name
Test status
Simulation time 1426484266 ps
CPU time 15.44 seconds
Started May 04 01:34:54 PM PDT 24
Finished May 04 01:35:10 PM PDT 24
Peak memory 208220 kb
Host smart-5e359540-5003-41e7-be9f-54ba914e347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927561103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.1927561103
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.2197229406
Short name T118
Test name
Test status
Simulation time 166330315 ps
CPU time 0.76 seconds
Started May 04 01:34:53 PM PDT 24
Finished May 04 01:34:54 PM PDT 24
Peak memory 205268 kb
Host smart-dc48d62e-4682-44f2-8859-67ccaeaa6282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197229406 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
2197229406
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.4084249449
Short name T75
Test name
Test status
Simulation time 718086338 ps
CPU time 18.74 seconds
Started May 04 01:34:56 PM PDT 24
Finished May 04 01:35:15 PM PDT 24
Peak memory 207232 kb
Host smart-10338553-7eba-4372-bd99-506c5bc9192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084249449 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.4084249449
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.4172295061
Short name T132
Test name
Test status
Simulation time 18365212 ps
CPU time 0.72 seconds
Started May 04 01:34:55 PM PDT 24
Finished May 04 01:34:57 PM PDT 24
Peak memory 205328 kb
Host smart-04437ca4-6e91-4b93-9f89-94491a8ecda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172295061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
4172295061
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.3178866146
Short name T83
Test name
Test status
Simulation time 19205216036 ps
CPU time 97.48 seconds
Started May 04 01:34:54 PM PDT 24
Finished May 04 01:36:32 PM PDT 24
Peak memory 207664 kb
Host smart-d83708fc-ef3e-45be-9f93-b7d0ab9abdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178866146 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.3178866146
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.1344960333
Short name T67
Test name
Test status
Simulation time 13686606 ps
CPU time 0.79 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:05 PM PDT 24
Peak memory 204904 kb
Host smart-f74ec1a1-6678-4d19-a67b-89da562d37e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344960333 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
1344960333
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.23946675
Short name T151
Test name
Test status
Simulation time 528741884 ps
CPU time 14.68 seconds
Started May 04 01:34:56 PM PDT 24
Finished May 04 01:35:11 PM PDT 24
Peak memory 207616 kb
Host smart-f852e0e1-2a0e-48ae-97bf-1055236da881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23946675 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.23946675
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.1495565974
Short name T157
Test name
Test status
Simulation time 58768499 ps
CPU time 0.9 seconds
Started May 04 01:34:45 PM PDT 24
Finished May 04 01:34:46 PM PDT 24
Peak memory 205268 kb
Host smart-de5d9d8c-bf8d-4f23-aed6-8274775c1ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495565974 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.1
495565974
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.3899714504
Short name T74
Test name
Test status
Simulation time 3466540551 ps
CPU time 21.67 seconds
Started May 04 01:34:43 PM PDT 24
Finished May 04 01:35:05 PM PDT 24
Peak memory 206464 kb
Host smart-0ce960ca-11aa-4a84-a5fd-fc3082efd43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899714504 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.3899714504
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.4074191654
Short name T148
Test name
Test status
Simulation time 22756657 ps
CPU time 0.93 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:35:03 PM PDT 24
Peak memory 205248 kb
Host smart-bf6415ad-da80-4446-8b49-d455d7c50041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074191654 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
4074191654
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.456988397
Short name T25
Test name
Test status
Simulation time 1243388236 ps
CPU time 22.64 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:35:24 PM PDT 24
Peak memory 208188 kb
Host smart-03806d62-afb1-4b90-8ad8-627058c620fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456988397 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.456988397
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.1899805401
Short name T147
Test name
Test status
Simulation time 103868501 ps
CPU time 0.8 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:35:03 PM PDT 24
Peak memory 205256 kb
Host smart-ac547d0d-21ed-4cf6-8faa-07ccee8192fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899805401 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
1899805401
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.1842374887
Short name T8
Test name
Test status
Simulation time 958265803 ps
CPU time 20.77 seconds
Started May 04 01:35:04 PM PDT 24
Finished May 04 01:35:25 PM PDT 24
Peak memory 206248 kb
Host smart-7c43f3fa-b0fe-4619-b48b-640399edca86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842374887 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.1842374887
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.244708011
Short name T140
Test name
Test status
Simulation time 14983957 ps
CPU time 0.77 seconds
Started May 04 01:35:00 PM PDT 24
Finished May 04 01:35:01 PM PDT 24
Peak memory 205216 kb
Host smart-229dd754-bab5-427a-8027-1f5a889deff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244708011 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.244708011
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.1231332591
Short name T156
Test name
Test status
Simulation time 571932575 ps
CPU time 8.57 seconds
Started May 04 01:35:00 PM PDT 24
Finished May 04 01:35:08 PM PDT 24
Peak memory 208012 kb
Host smart-e1c27fff-33c3-43fc-b9f9-320810597fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231332591 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1231332591
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.4273101629
Short name T145
Test name
Test status
Simulation time 57005115 ps
CPU time 0.72 seconds
Started May 04 01:35:00 PM PDT 24
Finished May 04 01:35:01 PM PDT 24
Peak memory 205332 kb
Host smart-e5f827d8-e20d-47e5-9580-737ca932a4d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273101629 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
4273101629
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.3751231609
Short name T134
Test name
Test status
Simulation time 18064381 ps
CPU time 0.75 seconds
Started May 04 01:34:59 PM PDT 24
Finished May 04 01:35:00 PM PDT 24
Peak memory 205344 kb
Host smart-5cbc9868-7fad-44ae-a326-97b0351c421b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751231609 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
3751231609
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.1235206566
Short name T117
Test name
Test status
Simulation time 45300231 ps
CPU time 0.74 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:35:03 PM PDT 24
Peak memory 205336 kb
Host smart-365f4a77-1956-4f76-9846-10fe3f8ef1b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235206566 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
1235206566
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.3418911618
Short name T108
Test name
Test status
Simulation time 721907828 ps
CPU time 14.44 seconds
Started May 04 01:35:03 PM PDT 24
Finished May 04 01:35:18 PM PDT 24
Peak memory 206564 kb
Host smart-216da7d3-4f13-4130-9e23-33f172137bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418911618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.3418911618
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.700499622
Short name T144
Test name
Test status
Simulation time 15088447 ps
CPU time 0.91 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:35:02 PM PDT 24
Peak memory 205504 kb
Host smart-453111bd-dce6-426f-bb29-0b691c546009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700499622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.700499622
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.3539381115
Short name T71
Test name
Test status
Simulation time 631901509 ps
CPU time 21.15 seconds
Started May 04 01:35:02 PM PDT 24
Finished May 04 01:35:24 PM PDT 24
Peak memory 207716 kb
Host smart-9203899f-7a6e-4728-b21a-3d9262186b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539381115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.3539381115
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.3390591931
Short name T158
Test name
Test status
Simulation time 10966374 ps
CPU time 0.77 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:35:03 PM PDT 24
Peak memory 205332 kb
Host smart-de902d24-a4e8-4d65-a5d9-54d79e541c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390591931 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
3390591931
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.2006592840
Short name T150
Test name
Test status
Simulation time 30140118 ps
CPU time 0.8 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:35:03 PM PDT 24
Peak memory 205232 kb
Host smart-a042e6b6-a8cd-4eff-9c86-0d80ebfd8bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006592840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
2006592840
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.4255516692
Short name T143
Test name
Test status
Simulation time 15559012 ps
CPU time 0.76 seconds
Started May 04 01:35:01 PM PDT 24
Finished May 04 01:35:02 PM PDT 24
Peak memory 205328 kb
Host smart-3b7455b6-331c-4e2c-98fd-c7ed1362e578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255516692 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
4255516692
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.1570887689
Short name T130
Test name
Test status
Simulation time 663200466 ps
CPU time 15.09 seconds
Started May 04 01:35:00 PM PDT 24
Finished May 04 01:35:16 PM PDT 24
Peak memory 207448 kb
Host smart-fcc1107d-51aa-4796-bb58-273f5122461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570887689 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.1570887689
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.657204380
Short name T14
Test name
Test status
Simulation time 97669529 ps
CPU time 0.79 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:34:51 PM PDT 24
Peak memory 205320 kb
Host smart-bccee68f-6218-4214-8596-4f2fcd857230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657204380 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.657204380
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.1751897845
Short name T12
Test name
Test status
Simulation time 4204282566 ps
CPU time 22.16 seconds
Started May 04 01:34:43 PM PDT 24
Finished May 04 01:35:05 PM PDT 24
Peak memory 208112 kb
Host smart-c339a7c8-8d44-4405-897c-6ddf3f522ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751897845 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.1751897845
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.1675357135
Short name T116
Test name
Test status
Simulation time 56141272 ps
CPU time 0.8 seconds
Started May 04 01:34:43 PM PDT 24
Finished May 04 01:34:44 PM PDT 24
Peak memory 205216 kb
Host smart-dcd02821-4bee-4f4b-9aa1-2a6403801eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675357135 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.1
675357135
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.3861350788
Short name T124
Test name
Test status
Simulation time 2364748896 ps
CPU time 31.12 seconds
Started May 04 01:34:45 PM PDT 24
Finished May 04 01:35:17 PM PDT 24
Peak memory 208016 kb
Host smart-bf9bfeb7-3239-4e56-b359-4bd55d6abae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861350788 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.3861350788
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.2293000147
Short name T159
Test name
Test status
Simulation time 12219712 ps
CPU time 0.83 seconds
Started May 04 01:34:49 PM PDT 24
Finished May 04 01:34:50 PM PDT 24
Peak memory 205292 kb
Host smart-1e223865-f44d-4027-9840-00dcfb213ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293000147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.2
293000147
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.2938231989
Short name T70
Test name
Test status
Simulation time 6040969639 ps
CPU time 44.13 seconds
Started May 04 01:34:50 PM PDT 24
Finished May 04 01:35:34 PM PDT 24
Peak memory 208324 kb
Host smart-904267b0-25ef-4112-bd24-a3b51962f291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938231989 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.2938231989
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.4027901528
Short name T65
Test name
Test status
Simulation time 11076929 ps
CPU time 0.71 seconds
Started May 04 01:34:51 PM PDT 24
Finished May 04 01:34:52 PM PDT 24
Peak memory 205212 kb
Host smart-fd59536a-c189-478b-a4c1-c0e3209a0d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027901528 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.4
027901528
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.3615400854
Short name T135
Test name
Test status
Simulation time 6019390290 ps
CPU time 43.16 seconds
Started May 04 01:34:49 PM PDT 24
Finished May 04 01:35:32 PM PDT 24
Peak memory 207272 kb
Host smart-e67f6e06-51b4-406a-b46a-4f69319d8788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615400854 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.3615400854
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.4166610603
Short name T137
Test name
Test status
Simulation time 31890889 ps
CPU time 0.75 seconds
Started May 04 01:34:49 PM PDT 24
Finished May 04 01:34:50 PM PDT 24
Peak memory 205368 kb
Host smart-861c49eb-e378-460a-a719-b9f88de99e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166610603 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.4
166610603
Directory /workspace/9.keymgr_dpe_alert_test/latest
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