Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.27	97.70	90.58	57.52	76.92	94.94	98.34	17.89

Total test records in report: 310

T257	/workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.4120203484	May 11 03:53:32 PM PDT 24	May 11 03:53:35 PM PDT 24	112284433 ps
T258	/workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.3226440374	May 11 03:54:07 PM PDT 24	May 11 03:54:09 PM PDT 24	45079906 ps
T48	/workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.2967808898	May 11 03:54:05 PM PDT 24	May 11 03:54:12 PM PDT 24	821779849 ps
T259	/workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.662342900	May 11 03:53:37 PM PDT 24	May 11 03:53:39 PM PDT 24	10937492 ps
T260	/workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.2120713241	May 11 03:54:06 PM PDT 24	May 11 03:54:09 PM PDT 24	40916091 ps
T261	/workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.766209459	May 11 03:54:06 PM PDT 24	May 11 03:54:09 PM PDT 24	11714107 ps
T262	/workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.4290603296	May 11 03:54:01 PM PDT 24	May 11 03:54:03 PM PDT 24	39042699 ps
T263	/workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.17759040	May 11 03:53:52 PM PDT 24	May 11 03:53:54 PM PDT 24	9993200 ps
T264	/workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.3737818710	May 11 03:53:30 PM PDT 24	May 11 03:53:37 PM PDT 24	1322626100 ps
T265	/workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.2431823437	May 11 03:54:06 PM PDT 24	May 11 03:54:08 PM PDT 24	14121858 ps
T266	/workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.720089537	May 11 03:54:04 PM PDT 24	May 11 03:54:06 PM PDT 24	10608013 ps
T43	/workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.1429267825	May 11 03:53:32 PM PDT 24	May 11 03:53:40 PM PDT 24	660288783 ps
T267	/workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.681518237	May 11 03:53:52 PM PDT 24	May 11 03:53:53 PM PDT 24	8429628 ps
T268	/workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.2912890664	May 11 03:54:09 PM PDT 24	May 11 03:54:12 PM PDT 24	30214594 ps
T269	/workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.4166136075	May 11 03:53:37 PM PDT 24	May 11 03:53:39 PM PDT 24	50853333 ps
T270	/workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2594025369	May 11 03:54:04 PM PDT 24	May 11 03:54:06 PM PDT 24	15634420 ps
T271	/workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4089719754	May 11 03:53:52 PM PDT 24	May 11 03:53:55 PM PDT 24	196774121 ps
T272	/workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.1436247147	May 11 03:53:58 PM PDT 24	May 11 03:54:03 PM PDT 24	113224183 ps
T46	/workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.4269072290	May 11 03:53:36 PM PDT 24	May 11 03:53:40 PM PDT 24	70318422 ps
T273	/workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.762549247	May 11 03:54:01 PM PDT 24	May 11 03:54:08 PM PDT 24	1063624250 ps
T274	/workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.3220013020	May 11 03:54:18 PM PDT 24	May 11 03:54:20 PM PDT 24	28892306 ps
T275	/workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.318306361	May 11 03:53:27 PM PDT 24	May 11 03:53:32 PM PDT 24	776359896 ps
T276	/workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.545926771	May 11 03:53:34 PM PDT 24	May 11 03:53:38 PM PDT 24	100459262 ps
T277	/workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.3371540689	May 11 03:53:42 PM PDT 24	May 11 03:53:45 PM PDT 24	79384951 ps
T278	/workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.3543179787	May 11 03:53:40 PM PDT 24	May 11 03:53:47 PM PDT 24	554424446 ps
T279	/workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.45826385	May 11 03:53:40 PM PDT 24	May 11 03:53:41 PM PDT 24	38427612 ps
T280	/workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1157686217	May 11 03:53:36 PM PDT 24	May 11 03:53:39 PM PDT 24	48159705 ps
T281	/workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.743038302	May 11 03:54:00 PM PDT 24	May 11 03:54:01 PM PDT 24	68684641 ps
T55	/workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.3208807051	May 11 03:53:44 PM PDT 24	May 11 03:53:49 PM PDT 24	171622201 ps
T282	/workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.2311180359	May 11 03:54:08 PM PDT 24	May 11 03:54:11 PM PDT 24	42878301 ps
T283	/workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.2111864190	May 11 03:54:08 PM PDT 24	May 11 03:54:11 PM PDT 24	35843673 ps
T284	/workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.3268044816	May 11 03:54:02 PM PDT 24	May 11 03:54:04 PM PDT 24	38058494 ps
T285	/workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2681539278	May 11 03:54:06 PM PDT 24	May 11 03:54:11 PM PDT 24	304704895 ps
T42	/workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.568758985	May 11 03:54:03 PM PDT 24	May 11 03:54:12 PM PDT 24	380384701 ps
T286	/workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.2629901907	May 11 03:54:18 PM PDT 24	May 11 03:54:20 PM PDT 24	200561885 ps
T287	/workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3834812294	May 11 03:54:11 PM PDT 24	May 11 03:54:13 PM PDT 24	15569467 ps
T288	/workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.3199377211	May 11 03:54:03 PM PDT 24	May 11 03:54:04 PM PDT 24	14448598 ps
T289	/workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.4117503255	May 11 03:54:06 PM PDT 24	May 11 03:54:09 PM PDT 24	14256518 ps
T290	/workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1051483971	May 11 03:53:38 PM PDT 24	May 11 03:53:41 PM PDT 24	270498032 ps
T291	/workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.2986885980	May 11 03:54:11 PM PDT 24	May 11 03:54:13 PM PDT 24	25792141 ps
T53	/workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.588252097	May 11 03:53:55 PM PDT 24	May 11 03:53:58 PM PDT 24	88713933 ps
T292	/workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.3875351684	May 11 03:54:04 PM PDT 24	May 11 03:54:07 PM PDT 24	608505348 ps
T293	/workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.425679656	May 11 03:54:04 PM PDT 24	May 11 03:54:06 PM PDT 24	57887897 ps
T294	/workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.3354290829	May 11 03:54:04 PM PDT 24	May 11 03:54:05 PM PDT 24	20342875 ps
T295	/workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.794526017	May 11 03:54:08 PM PDT 24	May 11 03:54:11 PM PDT 24	35038320 ps
T296	/workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2191474072	May 11 03:53:25 PM PDT 24	May 11 03:53:29 PM PDT 24	8911963 ps
T297	/workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.3914541108	May 11 03:53:53 PM PDT 24	May 11 03:53:59 PM PDT 24	221751616 ps
T298	/workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3383490557	May 11 03:53:23 PM PDT 24	May 11 03:53:35 PM PDT 24	425194129 ps
T299	/workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.3239777734	May 11 03:53:24 PM PDT 24	May 11 03:53:31 PM PDT 24	88363912 ps
T300	/workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.2804075275	May 11 03:53:59 PM PDT 24	May 11 03:54:03 PM PDT 24	152652905 ps
T301	/workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.3084078214	May 11 03:53:51 PM PDT 24	May 11 03:53:53 PM PDT 24	18680805 ps
T302	/workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.2875203871	May 11 03:54:15 PM PDT 24	May 11 03:54:17 PM PDT 24	11035621 ps
T303	/workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.3154574921	May 11 03:54:16 PM PDT 24	May 11 03:54:19 PM PDT 24	329767776 ps
T304	/workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.2742499429	May 11 03:54:08 PM PDT 24	May 11 03:54:12 PM PDT 24	36928440 ps
T305	/workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.3998742990	May 11 03:54:15 PM PDT 24	May 11 03:54:19 PM PDT 24	153965020 ps
T306	/workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2024927213	May 11 03:54:15 PM PDT 24	May 11 03:54:19 PM PDT 24	59082050 ps
T307	/workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.4000769285	May 11 03:53:29 PM PDT 24	May 11 03:53:32 PM PDT 24	412549420 ps
T308	/workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.3736203946	May 11 03:53:31 PM PDT 24	May 11 03:53:37 PM PDT 24	156186623 ps
T309	/workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2557170537	May 11 03:53:59 PM PDT 24	May 11 03:54:01 PM PDT 24	40959708 ps
T310	/workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1177193087	May 11 03:53:57 PM PDT 24	May 11 03:53:59 PM PDT 24	68943505 ps

Test location	/workspace/coverage/default/42.keymgr_dpe_smoke.1228095716
Short name	T3
Test name
Test status
Simulation time	47516935021 ps
CPU time	205.21 seconds
Started	May 11 01:38:47 PM PDT 24
Finished	May 11 01:42:12 PM PDT 24
Peak memory	208612 kb
Host	smart-44e0f9dc-7251-4207-ba46-4ecd7cd24295
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228095716 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1228095716
Directory	/workspace/42.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.537049950
Short name	T34
Test name
Test status
Simulation time	266456110 ps
CPU time	5.71 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:10 PM PDT 24
Peak memory	213028 kb
Host	smart-ea76c73a-bac5-4fe7-ba4e-47fd26b688e1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537049950 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_ TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.537049950
Directory	/workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/0.keymgr_dpe_sec_cm.281343970
Short name	T4
Test name
Test status
Simulation time	621466279 ps
CPU time	8.37 seconds
Started	May 11 01:38:27 PM PDT 24
Finished	May 11 01:38:35 PM PDT 24
Peak memory	233608 kb
Host	smart-5b1f8894-0894-4296-855e-4ec5f0412f3c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281343970 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.281343970
Directory	/workspace/0.keymgr_dpe_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.899894668
Short name	T33
Test name
Test status
Simulation time	329975017 ps
CPU time	2.85 seconds
Started	May 11 03:53:58 PM PDT 24
Finished	May 11 03:54:01 PM PDT 24
Peak memory	212772 kb
Host	smart-dac2832b-3896-4187-938f-c0a385892f63
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899894668 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.899894668
Directory	/workspace/15.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/default/30.keymgr_dpe_smoke.3478904613
Short name	T11
Test name
Test status
Simulation time	761017419 ps
CPU time	10.79 seconds
Started	May 11 01:38:40 PM PDT 24
Finished	May 11 01:38:51 PM PDT 24
Peak memory	206208 kb
Host	smart-d900950b-7a22-4e3e-b125-8784a9a424a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3478904613 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.3478904613
Directory	/workspace/30.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.618566495
Short name	T39
Test name
Test status
Simulation time	44597611 ps
CPU time	0.8 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	204320 kb
Host	smart-a0ef9aa5-403f-4eeb-8def-f0828f7da2b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618566495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.618566495
Directory	/workspace/23.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.768222428
Short name	T45
Test name
Test status
Simulation time	623523629 ps
CPU time	6.79 seconds
Started	May 11 03:54:09 PM PDT 24
Finished	May 11 03:54:18 PM PDT 24
Peak memory	213720 kb
Host	smart-ce74ab19-62ff-40cc-8819-001007d94284
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768222428 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe _tl_intg_err.768222428
Directory	/workspace/19.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/default/13.keymgr_dpe_alert_test.31142091
Short name	T112
Test name
Test status
Simulation time	125157071 ps
CPU time	0.86 seconds
Started	May 11 01:38:33 PM PDT 24
Finished	May 11 01:38:34 PM PDT 24
Peak memory	205292 kb
Host	smart-5d605d6a-19be-4777-8549-acbaa1abdecf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31142091 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.31142091
Directory	/workspace/13.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/4.keymgr_dpe_smoke.2263309815
Short name	T72
Test name
Test status
Simulation time	7929414020 ps
CPU time	144.07 seconds
Started	May 11 01:38:29 PM PDT 24
Finished	May 11 01:40:53 PM PDT 24
Peak memory	208500 kb
Host	smart-a35b3958-1fcf-4763-9894-1339000ba050
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263309815 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.2263309815
Directory	/workspace/4.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/34.keymgr_dpe_smoke.3974619345
Short name	T1
Test name
Test status
Simulation time	657878574 ps
CPU time	11.06 seconds
Started	May 11 01:38:42 PM PDT 24
Finished	May 11 01:38:53 PM PDT 24
Peak memory	206028 kb
Host	smart-37c6455e-2522-4fe7-9a55-ab9fd26abfae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974619345 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.3974619345
Directory	/workspace/34.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.2123230982
Short name	T196
Test name
Test status
Simulation time	579654789 ps
CPU time	2.78 seconds
Started	May 11 03:53:56 PM PDT 24
Finished	May 11 03:53:59 PM PDT 24
Peak memory	212792 kb
Host	smart-09767ac9-25de-425f-a8a8-f91d5b81ba36
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123230982 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors. 2123230982
Directory	/workspace/10.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/default/1.keymgr_dpe_sec_cm.4119894384
Short name	T21
Test name
Test status
Simulation time	1282064381 ps
CPU time	7.88 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:47 PM PDT 24
Peak memory	233364 kb
Host	smart-44e57b89-3696-489c-abe6-ef8c81c1968e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119894384 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.4119894384
Directory	/workspace/1.keymgr_dpe_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.1285648118
Short name	T52
Test name
Test status
Simulation time	156800809 ps
CPU time	3.46 seconds
Started	May 11 03:53:41 PM PDT 24
Finished	May 11 03:53:45 PM PDT 24
Peak memory	213732 kb
Host	smart-86d7eb23-46a2-415c-91f3-52f98348945f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285648118 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe _tl_intg_err.1285648118
Directory	/workspace/6.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.568758985
Short name	T42
Test name
Test status
Simulation time	380384701 ps
CPU time	8.52 seconds
Started	May 11 03:54:03 PM PDT 24
Finished	May 11 03:54:12 PM PDT 24
Peak memory	213968 kb
Host	smart-5471b909-5836-4b2f-9ca6-582de7de131a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568758985 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe _tl_intg_err.568758985
Directory	/workspace/15.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.912357536
Short name	T56
Test name
Test status
Simulation time	248066651 ps
CPU time	2.48 seconds
Started	May 11 03:53:21 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	213076 kb
Host	smart-4e7f870d-01f9-48c7-89da-4c94945ad383
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912357536 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymg r_dpe_shadow_reg_errors.912357536
Directory	/workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.866705694
Short name	T49
Test name
Test status
Simulation time	799352199 ps
CPU time	5.27 seconds
Started	May 11 03:53:52 PM PDT 24
Finished	May 11 03:53:58 PM PDT 24
Peak memory	212652 kb
Host	smart-e40fb71a-6f80-4836-b729-50ce35da12f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866705694 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe _tl_intg_err.866705694
Directory	/workspace/10.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/default/0.keymgr_dpe_smoke.2297287122
Short name	T98
Test name
Test status
Simulation time	792533710 ps
CPU time	23.81 seconds
Started	May 11 01:38:30 PM PDT 24
Finished	May 11 01:38:54 PM PDT 24
Peak memory	208000 kb
Host	smart-e18b78a7-c49e-4c05-86db-13430ffcf6a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297287122 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.2297287122
Directory	/workspace/0.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.2456557192
Short name	T31
Test name
Test status
Simulation time	255151262 ps
CPU time	2.96 seconds
Started	May 11 03:53:25 PM PDT 24
Finished	May 11 03:53:31 PM PDT 24
Peak memory	213672 kb
Host	smart-470ebacc-6cc0-4a1a-92da-2443aa710f14
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456557192 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe _tl_intg_err.2456557192
Directory	/workspace/0.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.588252097
Short name	T53
Test name
Test status
Simulation time	88713933 ps
CPU time	2.62 seconds
Started	May 11 03:53:55 PM PDT 24
Finished	May 11 03:53:58 PM PDT 24
Peak memory	212756 kb
Host	smart-cad81fb9-5a9f-43c5-82b7-d9197c32e64f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588252097 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe _tl_intg_err.588252097
Directory	/workspace/11.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.1601449774
Short name	T50
Test name
Test status
Simulation time	442537720 ps
CPU time	8.34 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:17 PM PDT 24
Peak memory	213760 kb
Host	smart-4a457b67-ed1d-4710-af34-4fe0ae23ecfd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601449774 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp e_tl_intg_err.1601449774
Directory	/workspace/16.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.1348793078
Short name	T18
Test name
Test status
Simulation time	1061169285 ps
CPU time	5.35 seconds
Started	May 11 03:54:09 PM PDT 24
Finished	May 11 03:54:16 PM PDT 24
Peak memory	212716 kb
Host	smart-2025675d-93b3-42b0-9bde-0e5fa80eab04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348793078 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp e_tl_intg_err.1348793078
Directory	/workspace/17.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.1429267825
Short name	T43
Test name
Test status
Simulation time	660288783 ps
CPU time	7.1 seconds
Started	May 11 03:53:32 PM PDT 24
Finished	May 11 03:53:40 PM PDT 24
Peak memory	214028 kb
Host	smart-7335f043-a0b5-49d0-a504-ed874973ed0a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429267825 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe _tl_intg_err.1429267825
Directory	/workspace/3.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.235906203
Short name	T47
Test name
Test status
Simulation time	164772768 ps
CPU time	5.51 seconds
Started	May 11 03:53:42 PM PDT 24
Finished	May 11 03:53:48 PM PDT 24
Peak memory	212776 kb
Host	smart-d5a9828a-1589-4474-b88b-a77155fd4d39
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235906203 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_ tl_intg_err.235906203
Directory	/workspace/5.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.1236871849
Short name	T208
Test name
Test status
Simulation time	49237702 ps
CPU time	0.78 seconds
Started	May 11 03:53:25 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	204348 kb
Host	smart-55f11cde-7343-4f96-802d-ca20c9658c95
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236871849 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.1 236871849
Directory	/workspace/1.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.14934866
Short name	T90
Test name
Test status
Simulation time	152687165 ps
CPU time	0.95 seconds
Started	May 11 03:53:56 PM PDT 24
Finished	May 11 03:53:58 PM PDT 24
Peak memory	204420 kb
Host	smart-6092cfb9-030f-4d6a-aa3b-bd198c0a4f87
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14934866 -assert nopostproc +UVM_TESTNAME=k eymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.14934866
Directory	/workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/1.keymgr_dpe_smoke.543690023
Short name	T87
Test name
Test status
Simulation time	512278289 ps
CPU time	17.87 seconds
Started	May 11 01:38:34 PM PDT 24
Finished	May 11 01:38:53 PM PDT 24
Peak memory	207816 kb
Host	smart-46678d54-43df-4247-a927-3cbddadfbc2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543690023 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.543690023
Directory	/workspace/1.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/14.keymgr_dpe_smoke.441509835
Short name	T89
Test name
Test status
Simulation time	1889763224 ps
CPU time	20.17 seconds
Started	May 11 01:38:32 PM PDT 24
Finished	May 11 01:38:53 PM PDT 24
Peak memory	208096 kb
Host	smart-8acadfa5-6a69-4444-92d3-3fb517dd0c48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441509835 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.441509835
Directory	/workspace/14.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/15.keymgr_dpe_smoke.133630846
Short name	T136
Test name
Test status
Simulation time	2345773488 ps
CPU time	37.92 seconds
Started	May 11 01:38:33 PM PDT 24
Finished	May 11 01:39:11 PM PDT 24
Peak memory	207564 kb
Host	smart-22f77131-c602-4d9c-8df6-d69480bb3943
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133630846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.133630846
Directory	/workspace/15.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/16.keymgr_dpe_smoke.1754148374
Short name	T106
Test name
Test status
Simulation time	933905615 ps
CPU time	13.88 seconds
Started	May 11 01:39:35 PM PDT 24
Finished	May 11 01:39:49 PM PDT 24
Peak memory	208180 kb
Host	smart-1eaf7827-882b-4333-a90f-a3d89bc4f56d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754148374 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.1754148374
Directory	/workspace/16.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/17.keymgr_dpe_smoke.2257135545
Short name	T101
Test name
Test status
Simulation time	3410849607 ps
CPU time	18.53 seconds
Started	May 11 01:38:33 PM PDT 24
Finished	May 11 01:38:52 PM PDT 24
Peak memory	208336 kb
Host	smart-47818e2c-ed1b-463a-9243-a61baed36163
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257135545 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.2257135545
Directory	/workspace/17.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/2.keymgr_dpe_smoke.2006742061
Short name	T102
Test name
Test status
Simulation time	38229057458 ps
CPU time	141.96 seconds
Started	May 11 01:38:31 PM PDT 24
Finished	May 11 01:40:53 PM PDT 24
Peak memory	208648 kb
Host	smart-2ea37c80-ceb2-4365-8580-f04c12ce6c55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006742061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.2006742061
Directory	/workspace/2.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/20.keymgr_dpe_smoke.3542191743
Short name	T103
Test name
Test status
Simulation time	935523266 ps
CPU time	20.11 seconds
Started	May 11 01:38:36 PM PDT 24
Finished	May 11 01:38:57 PM PDT 24
Peak memory	208644 kb
Host	smart-ddf6cdec-f360-4ed0-b6c7-26d32acd3b7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542191743 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.3542191743
Directory	/workspace/20.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/23.keymgr_dpe_smoke.3984578048
Short name	T12
Test name
Test status
Simulation time	618339531 ps
CPU time	10.86 seconds
Started	May 11 01:38:35 PM PDT 24
Finished	May 11 01:38:46 PM PDT 24
Peak memory	206348 kb
Host	smart-b59e4cae-679b-458c-a5a2-95b508eaf303
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984578048 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3984578048
Directory	/workspace/23.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/24.keymgr_dpe_smoke.909827053
Short name	T100
Test name
Test status
Simulation time	1263910924 ps
CPU time	28.69 seconds
Started	May 11 01:38:37 PM PDT 24
Finished	May 11 01:39:07 PM PDT 24
Peak memory	207460 kb
Host	smart-cacfc5e3-34ec-4d99-bc64-3ea6dbcbf2d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909827053 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.909827053
Directory	/workspace/24.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/29.keymgr_dpe_smoke.958200418
Short name	T68
Test name
Test status
Simulation time	1961452919 ps
CPU time	17.55 seconds
Started	May 11 01:38:40 PM PDT 24
Finished	May 11 01:38:58 PM PDT 24
Peak memory	206384 kb
Host	smart-956e0a58-a08e-47a8-8029-1d2c11634adf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958200418 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.958200418
Directory	/workspace/29.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/31.keymgr_dpe_smoke.1785852040
Short name	T7
Test name
Test status
Simulation time	2395180331 ps
CPU time	17.49 seconds
Started	May 11 01:38:41 PM PDT 24
Finished	May 11 01:38:59 PM PDT 24
Peak memory	207416 kb
Host	smart-97a97af2-88bf-4ab2-a693-1f769294ac23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785852040 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.1785852040
Directory	/workspace/31.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/32.keymgr_dpe_smoke.1469994551
Short name	T97
Test name
Test status
Simulation time	2146605100 ps
CPU time	19.71 seconds
Started	May 11 01:38:39 PM PDT 24
Finished	May 11 01:38:59 PM PDT 24
Peak memory	208064 kb
Host	smart-1e1fa282-1725-4859-aa27-6884cd7bc23a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1469994551 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.1469994551
Directory	/workspace/32.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/33.keymgr_dpe_smoke.2533076723
Short name	T88
Test name
Test status
Simulation time	2477813112 ps
CPU time	37.01 seconds
Started	May 11 01:38:40 PM PDT 24
Finished	May 11 01:39:17 PM PDT 24
Peak memory	207776 kb
Host	smart-dea5a7fd-402d-4ea9-b0d1-990e53889e37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533076723 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.2533076723
Directory	/workspace/33.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/38.keymgr_dpe_smoke.4097919853
Short name	T73
Test name
Test status
Simulation time	233807473 ps
CPU time	10.88 seconds
Started	May 11 01:38:45 PM PDT 24
Finished	May 11 01:38:56 PM PDT 24
Peak memory	207944 kb
Host	smart-cc013011-7ca2-488c-8c73-52b7c5f79396
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097919853 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.4097919853
Directory	/workspace/38.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/43.keymgr_dpe_smoke.1302330157
Short name	T13
Test name
Test status
Simulation time	2549415573 ps
CPU time	36.04 seconds
Started	May 11 01:38:49 PM PDT 24
Finished	May 11 01:39:25 PM PDT 24
Peak memory	208320 kb
Host	smart-cfaa0641-dcb6-4da7-bac4-2ce0623d7d21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302330157 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.1302330157
Directory	/workspace/43.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/8.keymgr_dpe_smoke.1509839398
Short name	T96
Test name
Test status
Simulation time	20890035713 ps
CPU time	166.34 seconds
Started	May 11 01:38:30 PM PDT 24
Finished	May 11 01:41:17 PM PDT 24
Peak memory	208072 kb
Host	smart-c1bdcc85-f896-453e-99ce-73ed88ecfd96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1509839398 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.1509839398
Directory	/workspace/8.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.318306361
Short name	T275
Test name
Test status
Simulation time	776359896 ps
CPU time	3.96 seconds
Started	May 11 03:53:27 PM PDT 24
Finished	May 11 03:53:32 PM PDT 24
Peak memory	204676 kb
Host	smart-cc98932d-d3b0-41d0-8ed9-dba8f11cab14
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318306361 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr _aliasing.318306361
Directory	/workspace/0.keymgr_dpe_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1401899225
Short name	T237
Test name
Test status
Simulation time	343548683 ps
CPU time	8.56 seconds
Started	May 11 03:53:25 PM PDT 24
Finished	May 11 03:53:36 PM PDT 24
Peak memory	204556 kb
Host	smart-c3550304-0c67-45c9-8407-3c0e5cbb4731
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401899225 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs r_bit_bash.1401899225
Directory	/workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.4275092998
Short name	T77
Test name
Test status
Simulation time	104992170 ps
CPU time	1.32 seconds
Started	May 11 03:53:24 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	204540 kb
Host	smart-4935070b-11af-4b6d-b3e4-848816ae80d7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275092998 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs r_hw_reset.4275092998
Directory	/workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.1819884922
Short name	T63
Test name
Test status
Simulation time	59408247 ps
CPU time	0.94 seconds
Started	May 11 03:53:25 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	204396 kb
Host	smart-a716f5e3-a97a-46e8-aeb2-03b5add48639
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819884922 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.1819884922
Directory	/workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.3336715481
Short name	T167
Test name
Test status
Simulation time	24054964 ps
CPU time	1.1 seconds
Started	May 11 03:53:26 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	204544 kb
Host	smart-ba08604f-42ab-4827-a07f-2c3cae24efbf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336715481 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.3 336715481
Directory	/workspace/0.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2191474072
Short name	T296
Test name
Test status
Simulation time	8911963 ps
CPU time	0.82 seconds
Started	May 11 03:53:25 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	204412 kb
Host	smart-62c8c875-a3aa-42b5-a2e2-8b2ca185e8cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191474072 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.2 191474072
Directory	/workspace/0.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.2526287607
Short name	T251
Test name
Test status
Simulation time	94776987 ps
CPU time	1.54 seconds
Started	May 11 03:53:25 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	204528 kb
Host	smart-8e074de0-debf-45a0-9fcf-2759da475dc1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526287607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k eymgr_dpe_same_csr_outstanding.2526287607
Directory	/workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.428388331
Short name	T83
Test name
Test status
Simulation time	126902609 ps
CPU time	2.97 seconds
Started	May 11 03:53:18 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	213080 kb
Host	smart-a2d4d0d0-5be8-4833-872c-126b3ada7f75
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428388331 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_ TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.428388331
Directory	/workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.4289243166
Short name	T20
Test name
Test status
Simulation time	112080875 ps
CPU time	2.31 seconds
Started	May 11 03:53:21 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	212780 kb
Host	smart-6a33f541-3215-4627-aff3-aca12723f8cb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289243166 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.4 289243166
Directory	/workspace/0.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.3736203946
Short name	T308
Test name
Test status
Simulation time	156186623 ps
CPU time	5.67 seconds
Started	May 11 03:53:31 PM PDT 24
Finished	May 11 03:53:37 PM PDT 24
Peak memory	204608 kb
Host	smart-1355bf87-9662-4717-865b-0d9cc5c14cbb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736203946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs r_aliasing.3736203946
Directory	/workspace/1.keymgr_dpe_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.3737818710
Short name	T264
Test name
Test status
Simulation time	1322626100 ps
CPU time	5.54 seconds
Started	May 11 03:53:30 PM PDT 24
Finished	May 11 03:53:37 PM PDT 24
Peak memory	204512 kb
Host	smart-be837902-458b-4b53-9875-a68f5a47b09c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737818710 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs r_bit_bash.3737818710
Directory	/workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.341755522
Short name	T76
Test name
Test status
Simulation time	23217712 ps
CPU time	1.03 seconds
Started	May 11 03:53:25 PM PDT 24
Finished	May 11 03:53:29 PM PDT 24
Peak memory	204504 kb
Host	smart-62ea230d-79bd-4921-b242-713b00b0b1df
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341755522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr _hw_reset.341755522
Directory	/workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.2660765630
Short name	T204
Test name
Test status
Simulation time	101400519 ps
CPU time	1.49 seconds
Started	May 11 03:53:30 PM PDT 24
Finished	May 11 03:53:33 PM PDT 24
Peak memory	212700 kb
Host	smart-61f11c7e-5bb4-41e7-b89a-855a68e323e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660765630 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.2660765630
Directory	/workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.3848803919
Short name	T79
Test name
Test status
Simulation time	11904782 ps
CPU time	0.86 seconds
Started	May 11 03:53:28 PM PDT 24
Finished	May 11 03:53:30 PM PDT 24
Peak memory	204432 kb
Host	smart-72367d60-81d0-41e0-a333-8c0a2f5bd7f8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848803919 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.3 848803919
Directory	/workspace/1.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.4000769285
Short name	T307
Test name
Test status
Simulation time	412549420 ps
CPU time	1.57 seconds
Started	May 11 03:53:29 PM PDT 24
Finished	May 11 03:53:32 PM PDT 24
Peak memory	204568 kb
Host	smart-631ca4ff-08f0-4755-8643-3feff15302cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000769285 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k eymgr_dpe_same_csr_outstanding.4000769285
Directory	/workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.2943753834
Short name	T210
Test name
Test status
Simulation time	120852473 ps
CPU time	3.5 seconds
Started	May 11 03:53:28 PM PDT 24
Finished	May 11 03:53:33 PM PDT 24
Peak memory	213028 kb
Host	smart-00d0ec9e-2dca-4249-9e57-7b55d18682f2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943753834 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym gr_dpe_shadow_reg_errors.2943753834
Directory	/workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3383490557
Short name	T298
Test name
Test status
Simulation time	425194129 ps
CPU time	7.62 seconds
Started	May 11 03:53:23 PM PDT 24
Finished	May 11 03:53:35 PM PDT 24
Peak memory	212968 kb
Host	smart-be750019-7b38-4d78-b4cb-7dc4f17ebbf8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383490557 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3383490557
Directory	/workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.3239777734
Short name	T299
Test name
Test status
Simulation time	88363912 ps
CPU time	3.07 seconds
Started	May 11 03:53:24 PM PDT 24
Finished	May 11 03:53:31 PM PDT 24
Peak memory	212752 kb
Host	smart-a7b987e0-e72b-49d9-9b7f-455329722e8e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239777734 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.3 239777734
Directory	/workspace/1.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.4095281559
Short name	T108
Test name
Test status
Simulation time	122031611 ps
CPU time	4.82 seconds
Started	May 11 03:53:30 PM PDT 24
Finished	May 11 03:53:36 PM PDT 24
Peak memory	213808 kb
Host	smart-532c73e2-7280-484b-874b-4429da2ef064
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095281559 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe _tl_intg_err.4095281559
Directory	/workspace/1.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2492574522
Short name	T245
Test name
Test status
Simulation time	58310163 ps
CPU time	1.36 seconds
Started	May 11 03:53:52 PM PDT 24
Finished	May 11 03:53:54 PM PDT 24
Peak memory	204636 kb
Host	smart-7fbd231f-75c2-429d-ac60-c3774a093124
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492574522 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.2492574522
Directory	/workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.529804340
Short name	T246
Test name
Test status
Simulation time	43617435 ps
CPU time	1.04 seconds
Started	May 11 03:53:56 PM PDT 24
Finished	May 11 03:53:58 PM PDT 24
Peak memory	204312 kb
Host	smart-4396eeeb-8656-4461-aecd-98498172f62b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529804340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.529804340
Directory	/workspace/10.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.814153172
Short name	T40
Test name
Test status
Simulation time	33926708 ps
CPU time	0.87 seconds
Started	May 11 03:53:55 PM PDT 24
Finished	May 11 03:53:56 PM PDT 24
Peak memory	204380 kb
Host	smart-13e7ec7f-6229-4ed3-9d4c-8f1548bf52fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814153172 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.814153172
Directory	/workspace/10.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.3084078214
Short name	T301
Test name
Test status
Simulation time	18680805 ps
CPU time	1.13 seconds
Started	May 11 03:53:51 PM PDT 24
Finished	May 11 03:53:53 PM PDT 24
Peak memory	204576 kb
Host	smart-a2b1b743-a3bf-4593-9488-88abed3a596b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084078214 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. keymgr_dpe_same_csr_outstanding.3084078214
Directory	/workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.120380211
Short name	T176
Test name
Test status
Simulation time	35335485 ps
CPU time	1.78 seconds
Started	May 11 03:53:53 PM PDT 24
Finished	May 11 03:53:55 PM PDT 24
Peak memory	213032 kb
Host	smart-e26259ec-b1ae-448a-abed-3deda0aea94d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120380211 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keym gr_dpe_shadow_reg_errors.120380211
Directory	/workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.2223798633
Short name	T211
Test name
Test status
Simulation time	127266561 ps
CPU time	5.67 seconds
Started	May 11 03:53:52 PM PDT 24
Finished	May 11 03:53:58 PM PDT 24
Peak memory	219340 kb
Host	smart-5732a17b-f9ba-42ce-b668-175ecb85bf18
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223798633 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.2223798633
Directory	/workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.2469897315
Short name	T200
Test name
Test status
Simulation time	38636822 ps
CPU time	0.96 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	204428 kb
Host	smart-651b1357-cbb2-422f-8abd-8c102bb5f047
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469897315 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.2469897315
Directory	/workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.815156025
Short name	T85
Test name
Test status
Simulation time	12771074 ps
CPU time	0.98 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	204504 kb
Host	smart-680ddd58-ff22-4d28-b441-10aeea9e1692
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815156025 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.815156025
Directory	/workspace/11.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1357066948
Short name	T220
Test name
Test status
Simulation time	130116055 ps
CPU time	0.72 seconds
Started	May 11 03:53:54 PM PDT 24
Finished	May 11 03:53:55 PM PDT 24
Peak memory	204408 kb
Host	smart-daf12157-174d-4b61-a729-aeedf0156ec6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357066948 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test. 1357066948
Directory	/workspace/11.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.4290603296
Short name	T262
Test name
Test status
Simulation time	39042699 ps
CPU time	1.48 seconds
Started	May 11 03:54:01 PM PDT 24
Finished	May 11 03:54:03 PM PDT 24
Peak memory	204604 kb
Host	smart-5912559b-3f32-4adc-9a4e-52525843c345
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290603296 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. keymgr_dpe_same_csr_outstanding.4290603296
Directory	/workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1381482861
Short name	T186
Test name
Test status
Simulation time	1009377155 ps
CPU time	3.75 seconds
Started	May 11 03:53:54 PM PDT 24
Finished	May 11 03:53:58 PM PDT 24
Peak memory	213060 kb
Host	smart-712e9cfe-5c08-46b2-ade8-43855739d7cd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381482861 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key mgr_dpe_shadow_reg_errors.1381482861
Directory	/workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.3914541108
Short name	T297
Test name
Test status
Simulation time	221751616 ps
CPU time	5.43 seconds
Started	May 11 03:53:53 PM PDT 24
Finished	May 11 03:53:59 PM PDT 24
Peak memory	213040 kb
Host	smart-c9a3ab96-570e-44f9-81cb-fdb23c7e23d2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914541108 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.3914541108
Directory	/workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1177193087
Short name	T310
Test name
Test status
Simulation time	68943505 ps
CPU time	1.37 seconds
Started	May 11 03:53:57 PM PDT 24
Finished	May 11 03:53:59 PM PDT 24
Peak memory	220448 kb
Host	smart-ab98615c-f562-4923-9adf-a58440715ca7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177193087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors. 1177193087
Directory	/workspace/11.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.509689404
Short name	T222
Test name
Test status
Simulation time	81097508 ps
CPU time	1.04 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	204332 kb
Host	smart-6a80f983-4d2c-471c-85c4-e5550e6c6bd2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509689404 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.509689404
Directory	/workspace/12.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.2120713241
Short name	T260
Test name
Test status
Simulation time	40916091 ps
CPU time	0.72 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:09 PM PDT 24
Peak memory	204360 kb
Host	smart-75d7a9e2-1809-4e22-8308-05eda33244e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120713241 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test. 2120713241
Directory	/workspace/12.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.2096493432
Short name	T247
Test name
Test status
Simulation time	69638618 ps
CPU time	1.93 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:07 PM PDT 24
Peak memory	204492 kb
Host	smart-7dc2c5de-2c65-45e7-bdb0-8830f1978016
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096493432 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. keymgr_dpe_same_csr_outstanding.2096493432
Directory	/workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.604110525
Short name	T202
Test name
Test status
Simulation time	76124377 ps
CPU time	2.46 seconds
Started	May 11 03:54:08 PM PDT 24
Finished	May 11 03:54:13 PM PDT 24
Peak memory	212792 kb
Host	smart-0c46f158-e44d-43f0-8069-51d25a959efb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604110525 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keym gr_dpe_shadow_reg_errors.604110525
Directory	/workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.2013945186
Short name	T174
Test name
Test status
Simulation time	198466445 ps
CPU time	4.32 seconds
Started	May 11 03:53:57 PM PDT 24
Finished	May 11 03:54:02 PM PDT 24
Peak memory	213060 kb
Host	smart-21d5fde4-0d0d-457f-9834-69ff01fe2261
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013945186 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.2013945186
Directory	/workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3447525777
Short name	T65
Test name
Test status
Simulation time	291861259 ps
CPU time	3.83 seconds
Started	May 11 03:53:56 PM PDT 24
Finished	May 11 03:54:00 PM PDT 24
Peak memory	214812 kb
Host	smart-ec164d6a-c544-4886-a411-dc510a33905d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447525777 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors. 3447525777
Directory	/workspace/12.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.2676235077
Short name	T51
Test name
Test status
Simulation time	315596697 ps
CPU time	5.72 seconds
Started	May 11 03:53:57 PM PDT 24
Finished	May 11 03:54:03 PM PDT 24
Peak memory	213920 kb
Host	smart-9385622d-57c7-474d-9a1a-0793da0898e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676235077 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp e_tl_intg_err.2676235077
Directory	/workspace/12.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.4287634607
Short name	T216
Test name
Test status
Simulation time	49469466 ps
CPU time	1.45 seconds
Started	May 11 03:54:03 PM PDT 24
Finished	May 11 03:54:05 PM PDT 24
Peak memory	212724 kb
Host	smart-bd2ab192-234c-45f7-b55d-5bb1db8ed1e9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287634607 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.4287634607
Directory	/workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.2742499429
Short name	T304
Test name
Test status
Simulation time	36928440 ps
CPU time	1.27 seconds
Started	May 11 03:54:08 PM PDT 24
Finished	May 11 03:54:12 PM PDT 24
Peak memory	204316 kb
Host	smart-0dcdae4b-d9e5-457c-9324-1b5e36462db5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742499429 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw. 2742499429
Directory	/workspace/13.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.720089537
Short name	T266
Test name
Test status
Simulation time	10608013 ps
CPU time	0.79 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	204112 kb
Host	smart-22e4f77d-e6ef-4322-9192-96f9553d14c5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720089537 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.720089537
Directory	/workspace/13.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.1265592270
Short name	T80
Test name
Test status
Simulation time	190981373 ps
CPU time	1.41 seconds
Started	May 11 03:54:07 PM PDT 24
Finished	May 11 03:54:11 PM PDT 24
Peak memory	204472 kb
Host	smart-41cec816-ca1a-4b66-9fe9-2648ebd29fbe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265592270 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. keymgr_dpe_same_csr_outstanding.1265592270
Directory	/workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.2804075275
Short name	T300
Test name
Test status
Simulation time	152652905 ps
CPU time	3.3 seconds
Started	May 11 03:53:59 PM PDT 24
Finished	May 11 03:54:03 PM PDT 24
Peak memory	213068 kb
Host	smart-627d51f0-21f1-4ed0-b9d1-da65ba2d7a38
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804075275 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key mgr_dpe_shadow_reg_errors.2804075275
Directory	/workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2008273287
Short name	T59
Test name
Test status
Simulation time	248618732 ps
CPU time	5.95 seconds
Started	May 11 03:53:58 PM PDT 24
Finished	May 11 03:54:04 PM PDT 24
Peak memory	213064 kb
Host	smart-470edc45-51bb-4ec3-89db-6f04cf7380ec
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008273287 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2008273287
Directory	/workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1110149255
Short name	T253
Test name
Test status
Simulation time	289386929 ps
CPU time	3 seconds
Started	May 11 03:54:05 PM PDT 24
Finished	May 11 03:54:09 PM PDT 24
Peak memory	212860 kb
Host	smart-a36685a1-f1c0-47d7-96b8-5df0873cf8c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110149255 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors. 1110149255
Directory	/workspace/13.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.1436247147
Short name	T272
Test name
Test status
Simulation time	113224183 ps
CPU time	4.24 seconds
Started	May 11 03:53:58 PM PDT 24
Finished	May 11 03:54:03 PM PDT 24
Peak memory	213772 kb
Host	smart-36c2afd5-7c12-4bc3-94f8-ff07c42f6b48
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436247147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp e_tl_intg_err.1436247147
Directory	/workspace/13.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.3149343678
Short name	T221
Test name
Test status
Simulation time	64198921 ps
CPU time	1.17 seconds
Started	May 11 03:54:05 PM PDT 24
Finished	May 11 03:54:08 PM PDT 24
Peak memory	204592 kb
Host	smart-e69002af-00d1-4b1c-98a9-e2a1faed2bbd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149343678 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.3149343678
Directory	/workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.3199377211
Short name	T288
Test name
Test status
Simulation time	14448598 ps
CPU time	0.92 seconds
Started	May 11 03:54:03 PM PDT 24
Finished	May 11 03:54:04 PM PDT 24
Peak memory	204428 kb
Host	smart-746c4b69-529b-49c1-8ce0-0eec26f24015
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199377211 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw. 3199377211
Directory	/workspace/14.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.142502466
Short name	T179
Test name
Test status
Simulation time	41613608 ps
CPU time	0.81 seconds
Started	May 11 03:54:05 PM PDT 24
Finished	May 11 03:54:07 PM PDT 24
Peak memory	204452 kb
Host	smart-1f942e91-9e3e-49d6-8ab6-fd66e5b652a9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142502466 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.142502466
Directory	/workspace/14.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.743038302
Short name	T281
Test name
Test status
Simulation time	68684641 ps
CPU time	1.23 seconds
Started	May 11 03:54:00 PM PDT 24
Finished	May 11 03:54:01 PM PDT 24
Peak memory	204500 kb
Host	smart-348c7dd8-6510-4a3f-87ee-7f2c3b6bc13c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743038302 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ= keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k eymgr_dpe_same_csr_outstanding.743038302
Directory	/workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.2042400542
Short name	T67
Test name
Test status
Simulation time	97811791 ps
CPU time	1.94 seconds
Started	May 11 03:53:59 PM PDT 24
Finished	May 11 03:54:01 PM PDT 24
Peak memory	212988 kb
Host	smart-98ea6670-5ea6-4e6f-a460-ec5944994d4a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042400542 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key mgr_dpe_shadow_reg_errors.2042400542
Directory	/workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.762549247
Short name	T273
Test name
Test status
Simulation time	1063624250 ps
CPU time	6.31 seconds
Started	May 11 03:54:01 PM PDT 24
Finished	May 11 03:54:08 PM PDT 24
Peak memory	213072 kb
Host	smart-5cf772fe-95dd-462c-9aaf-d2d955a22d53
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762549247 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_ TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.762549247
Directory	/workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.2254574528
Short name	T36
Test name
Test status
Simulation time	138592208 ps
CPU time	3.16 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:12 PM PDT 24
Peak memory	212664 kb
Host	smart-7ae2778a-2ecf-43c3-8c32-636ce3f4d7f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254574528 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors. 2254574528
Directory	/workspace/14.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.2084412108
Short name	T199
Test name
Test status
Simulation time	92780092 ps
CPU time	2.14 seconds
Started	May 11 03:54:05 PM PDT 24
Finished	May 11 03:54:08 PM PDT 24
Peak memory	204488 kb
Host	smart-84c4e3cd-32ad-4348-b9b7-489163a3e4b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084412108 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp e_tl_intg_err.2084412108
Directory	/workspace/14.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.1645375899
Short name	T19
Test name
Test status
Simulation time	23086584 ps
CPU time	1.28 seconds
Started	May 11 03:54:08 PM PDT 24
Finished	May 11 03:54:12 PM PDT 24
Peak memory	212616 kb
Host	smart-0abca0ff-0fc7-4ded-a76f-7e337f5c34a6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645375899 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.1645375899
Directory	/workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.3259693624
Short name	T62
Test name
Test status
Simulation time	29146136 ps
CPU time	1.09 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:08 PM PDT 24
Peak memory	204508 kb
Host	smart-9b1d43e6-5978-4ec6-ac92-39d28b3af432
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259693624 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw. 3259693624
Directory	/workspace/15.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.907113753
Short name	T185
Test name
Test status
Simulation time	19596576 ps
CPU time	0.8 seconds
Started	May 11 03:54:08 PM PDT 24
Finished	May 11 03:54:11 PM PDT 24
Peak memory	204336 kb
Host	smart-f0685d9f-cec8-4605-a414-ce4750779ff3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907113753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.907113753
Directory	/workspace/15.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.847987407
Short name	T227
Test name
Test status
Simulation time	169000915 ps
CPU time	3.07 seconds
Started	May 11 03:54:00 PM PDT 24
Finished	May 11 03:54:03 PM PDT 24
Peak memory	204516 kb
Host	smart-cd74bfde-44a9-44d5-8f84-afb6337b231d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847987407 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ= keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.k eymgr_dpe_same_csr_outstanding.847987407
Directory	/workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.613517823
Short name	T60
Test name
Test status
Simulation time	95638721 ps
CPU time	3.15 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:08 PM PDT 24
Peak memory	213088 kb
Host	smart-f1b629ce-d99e-4a8b-9cc8-09993dadf7af
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613517823 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keym gr_dpe_shadow_reg_errors.613517823
Directory	/workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.4114803815
Short name	T212
Test name
Test status
Simulation time	57921648 ps
CPU time	3.23 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:08 PM PDT 24
Peak memory	217900 kb
Host	smart-e96b820f-52d3-4ac7-be7c-d04e03a4b6a7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114803815 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.4114803815
Directory	/workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.4247085795
Short name	T58
Test name
Test status
Simulation time	89921658 ps
CPU time	1.13 seconds
Started	May 11 03:54:01 PM PDT 24
Finished	May 11 03:54:02 PM PDT 24
Peak memory	215184 kb
Host	smart-0a3dd00d-5520-4ef3-8f98-b8d8318d1ccf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247085795 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.4247085795
Directory	/workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.312573036
Short name	T201
Test name
Test status
Simulation time	36934356 ps
CPU time	1.03 seconds
Started	May 11 03:53:59 PM PDT 24
Finished	May 11 03:54:01 PM PDT 24
Peak memory	204432 kb
Host	smart-4f59b88c-514e-4754-91c2-e0245171e848
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312573036 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.312573036
Directory	/workspace/16.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.2111864190
Short name	T283
Test name
Test status
Simulation time	35843673 ps
CPU time	0.69 seconds
Started	May 11 03:54:08 PM PDT 24
Finished	May 11 03:54:11 PM PDT 24
Peak memory	204088 kb
Host	smart-8c1c1a1f-e666-4676-b9a6-4e82a63369b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111864190 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test. 2111864190
Directory	/workspace/16.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2557170537
Short name	T309
Test name
Test status
Simulation time	40959708 ps
CPU time	1.59 seconds
Started	May 11 03:53:59 PM PDT 24
Finished	May 11 03:54:01 PM PDT 24
Peak memory	204520 kb
Host	smart-6cad543a-d269-44b9-be46-49e3a9c6844d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557170537 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. keymgr_dpe_same_csr_outstanding.2557170537
Directory	/workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.3875351684
Short name	T292
Test name
Test status
Simulation time	608505348 ps
CPU time	2.23 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:07 PM PDT 24
Peak memory	213120 kb
Host	smart-f020652f-8f80-4793-8afc-1f538c87c80a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875351684 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key mgr_dpe_shadow_reg_errors.3875351684
Directory	/workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.832658622
Short name	T171
Test name
Test status
Simulation time	291914668 ps
CPU time	5.75 seconds
Started	May 11 03:54:00 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	213080 kb
Host	smart-a85d0cb9-d796-4241-be4c-c94650de9c77
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832658622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_ TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.832658622
Directory	/workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2681539278
Short name	T285
Test name
Test status
Simulation time	304704895 ps
CPU time	3.06 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:11 PM PDT 24
Peak memory	212812 kb
Host	smart-daa6cc0e-f038-4f19-a1ea-c82ef9d59239
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681539278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors. 2681539278
Directory	/workspace/16.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2594025369
Short name	T270
Test name
Test status
Simulation time	15634420 ps
CPU time	1.26 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	220308 kb
Host	smart-1e6f595d-87c1-4193-96c6-ce091b37028f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594025369 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.2594025369
Directory	/workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.425679656
Short name	T293
Test name
Test status
Simulation time	57887897 ps
CPU time	1.05 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	204424 kb
Host	smart-952be129-7ca6-466f-b42a-297b5b752e6b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425679656 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.425679656
Directory	/workspace/17.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.1826827771
Short name	T109
Test name
Test status
Simulation time	15840054 ps
CPU time	0.73 seconds
Started	May 11 03:54:07 PM PDT 24
Finished	May 11 03:54:10 PM PDT 24
Peak memory	204252 kb
Host	smart-387b54fd-a614-4455-b5b5-50cc18fef5f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826827771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test. 1826827771
Directory	/workspace/17.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.3686604144
Short name	T188
Test name
Test status
Simulation time	31146177 ps
CPU time	1.27 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:07 PM PDT 24
Peak memory	204612 kb
Host	smart-479555d6-ae2f-49b4-a3b6-9a994cb892db
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686604144 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. keymgr_dpe_same_csr_outstanding.3686604144
Directory	/workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.991966797
Short name	T175
Test name
Test status
Simulation time	130438080 ps
CPU time	2.44 seconds
Started	May 11 03:54:17 PM PDT 24
Finished	May 11 03:54:21 PM PDT 24
Peak memory	212744 kb
Host	smart-211743d0-9f26-447f-9cba-cf55d243686b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991966797 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keym gr_dpe_shadow_reg_errors.991966797
Directory	/workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.1122047209
Short name	T231
Test name
Test status
Simulation time	52644603 ps
CPU time	1.95 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:09 PM PDT 24
Peak memory	221032 kb
Host	smart-2e42a8ac-d194-4328-be4e-39e64bd30b7a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122047209 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors. 1122047209
Directory	/workspace/17.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.216455422
Short name	T197
Test name
Test status
Simulation time	110833549 ps
CPU time	1.3 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:07 PM PDT 24
Peak memory	204436 kb
Host	smart-debcdcf2-b6fe-4e30-9c41-23072768ddd0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216455422 -assert nopostproc +UVM_TESTNAME= keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.216455422
Directory	/workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2018386618
Short name	T189
Test name
Test status
Simulation time	161351000 ps
CPU time	0.98 seconds
Started	May 11 03:54:18 PM PDT 24
Finished	May 11 03:54:20 PM PDT 24
Peak memory	204128 kb
Host	smart-7d5ae44b-0565-4fac-bc1b-cb990c19408d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018386618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw. 2018386618
Directory	/workspace/18.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.2912890664
Short name	T268
Test name
Test status
Simulation time	30214594 ps
CPU time	0.73 seconds
Started	May 11 03:54:09 PM PDT 24
Finished	May 11 03:54:12 PM PDT 24
Peak memory	204392 kb
Host	smart-f81e8f0d-c09f-4fda-bd64-b1f57ddb95aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912890664 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test. 2912890664
Directory	/workspace/18.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.3119872567
Short name	T217
Test name
Test status
Simulation time	477279945 ps
CPU time	1.93 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	204464 kb
Host	smart-b7b76f74-f612-4270-9e71-3f706eaa00c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119872567 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. keymgr_dpe_same_csr_outstanding.3119872567
Directory	/workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.1025747241
Short name	T182
Test name
Test status
Simulation time	93030187 ps
CPU time	2.07 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:07 PM PDT 24
Peak memory	213084 kb
Host	smart-35ed7046-2dc0-4d2a-ae52-fe1c66dc3e39
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025747241 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key mgr_dpe_shadow_reg_errors.1025747241
Directory	/workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2024927213
Short name	T306
Test name
Test status
Simulation time	59082050 ps
CPU time	3.12 seconds
Started	May 11 03:54:15 PM PDT 24
Finished	May 11 03:54:19 PM PDT 24
Peak memory	205060 kb
Host	smart-0b5fdef8-0dcc-4203-986b-73f63c980dbc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024927213 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2024927213
Directory	/workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.3998742990
Short name	T305
Test name
Test status
Simulation time	153965020 ps
CPU time	2.52 seconds
Started	May 11 03:54:15 PM PDT 24
Finished	May 11 03:54:19 PM PDT 24
Peak memory	220952 kb
Host	smart-5816ca5b-5e87-4e01-9a25-613de41d7888
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998742990 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors. 3998742990
Directory	/workspace/18.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.2967808898
Short name	T48
Test name
Test status
Simulation time	821779849 ps
CPU time	5.64 seconds
Started	May 11 03:54:05 PM PDT 24
Finished	May 11 03:54:12 PM PDT 24
Peak memory	212732 kb
Host	smart-0aac1a49-ff00-4e98-b983-a023079968c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967808898 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp e_tl_intg_err.2967808898
Directory	/workspace/18.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.3354290829
Short name	T294
Test name
Test status
Simulation time	20342875 ps
CPU time	0.93 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:05 PM PDT 24
Peak memory	204520 kb
Host	smart-9ec26423-eedf-4c31-907c-c48298dfde42
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354290829 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.3354290829
Directory	/workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.3247389467
Short name	T209
Test name
Test status
Simulation time	19236904 ps
CPU time	1.15 seconds
Started	May 11 03:54:03 PM PDT 24
Finished	May 11 03:54:04 PM PDT 24
Peak memory	204532 kb
Host	smart-077cfa98-d8ca-46d4-830f-b5b0feac3f14
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247389467 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw. 3247389467
Directory	/workspace/19.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.2930853693
Short name	T228
Test name
Test status
Simulation time	48203231 ps
CPU time	0.82 seconds
Started	May 11 03:54:03 PM PDT 24
Finished	May 11 03:54:04 PM PDT 24
Peak memory	204376 kb
Host	smart-a8ee7dd6-bee1-4159-8b24-3983f03a23ba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930853693 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test. 2930853693
Directory	/workspace/19.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.602863278
Short name	T234
Test name
Test status
Simulation time	154127431 ps
CPU time	1.79 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:10 PM PDT 24
Peak memory	204408 kb
Host	smart-c23179de-7edf-43cf-8311-4733ede21565
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602863278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ= keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k eymgr_dpe_same_csr_outstanding.602863278
Directory	/workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.3154574921
Short name	T303
Test name
Test status
Simulation time	329767776 ps
CPU time	1.35 seconds
Started	May 11 03:54:16 PM PDT 24
Finished	May 11 03:54:19 PM PDT 24
Peak memory	212676 kb
Host	smart-0806d275-f364-486a-92a1-726e2d9cc747
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154574921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key mgr_dpe_shadow_reg_errors.3154574921
Directory	/workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3480132776
Short name	T180
Test name
Test status
Simulation time	108534916 ps
CPU time	5.35 seconds
Started	May 11 03:54:08 PM PDT 24
Finished	May 11 03:54:15 PM PDT 24
Peak memory	213252 kb
Host	smart-dc5abfda-d731-4ebf-8789-8d581ae4b1ac
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480132776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3480132776
Directory	/workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.1114034047
Short name	T44
Test name
Test status
Simulation time	47142822 ps
CPU time	2.92 seconds
Started	May 11 03:54:00 PM PDT 24
Finished	May 11 03:54:03 PM PDT 24
Peak memory	213936 kb
Host	smart-d8836080-b5a5-4a45-b338-a8c75a1ad9bf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114034047 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors. 1114034047
Directory	/workspace/19.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.3708285490
Short name	T81
Test name
Test status
Simulation time	310869276 ps
CPU time	5.39 seconds
Started	May 11 03:53:34 PM PDT 24
Finished	May 11 03:53:40 PM PDT 24
Peak memory	204584 kb
Host	smart-1cd72441-b801-47b0-8f0a-37cc5adfa899
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708285490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs r_aliasing.3708285490
Directory	/workspace/2.keymgr_dpe_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.1379455945
Short name	T215
Test name
Test status
Simulation time	4725923889 ps
CPU time	22.36 seconds
Started	May 11 03:53:34 PM PDT 24
Finished	May 11 03:53:57 PM PDT 24
Peak memory	204660 kb
Host	smart-85b74617-e025-4c2d-a740-097acf430757
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379455945 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs r_bit_bash.1379455945
Directory	/workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.279544848
Short name	T183
Test name
Test status
Simulation time	11509021 ps
CPU time	0.88 seconds
Started	May 11 03:53:34 PM PDT 24
Finished	May 11 03:53:35 PM PDT 24
Peak memory	204392 kb
Host	smart-b10aa030-820a-41d9-840d-ebd71e750edd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279544848 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr _hw_reset.279544848
Directory	/workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.1249042158
Short name	T66
Test name
Test status
Simulation time	241885663 ps
CPU time	1.59 seconds
Started	May 11 03:53:33 PM PDT 24
Finished	May 11 03:53:36 PM PDT 24
Peak memory	212808 kb
Host	smart-8cf1c023-aa01-48c9-8a7e-34c88bb9b045
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249042158 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.1249042158
Directory	/workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.1410689852
Short name	T173
Test name
Test status
Simulation time	71740029 ps
CPU time	1.14 seconds
Started	May 11 03:53:33 PM PDT 24
Finished	May 11 03:53:34 PM PDT 24
Peak memory	204516 kb
Host	smart-ecf3c817-059f-4297-97c1-bf58d9be9406
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410689852 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.1 410689852
Directory	/workspace/2.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.3957276866
Short name	T84
Test name
Test status
Simulation time	12066279 ps
CPU time	0.86 seconds
Started	May 11 03:53:28 PM PDT 24
Finished	May 11 03:53:31 PM PDT 24
Peak memory	204336 kb
Host	smart-8c1078b1-3505-4add-a2e5-9e4862c8591a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957276866 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.3 957276866
Directory	/workspace/2.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.2788897096
Short name	T86
Test name
Test status
Simulation time	262315782 ps
CPU time	2.32 seconds
Started	May 11 03:53:32 PM PDT 24
Finished	May 11 03:53:35 PM PDT 24
Peak memory	204580 kb
Host	smart-c65f3527-3ba5-4e47-90cf-449435179b82
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788897096 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k eymgr_dpe_same_csr_outstanding.2788897096
Directory	/workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.3142467774
Short name	T244
Test name
Test status
Simulation time	119575596 ps
CPU time	2.16 seconds
Started	May 11 03:53:29 PM PDT 24
Finished	May 11 03:53:32 PM PDT 24
Peak memory	213088 kb
Host	smart-bbe92316-6dbd-4f61-b286-c68ac9715a2d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142467774 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym gr_dpe_shadow_reg_errors.3142467774
Directory	/workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4161103194
Short name	T170
Test name
Test status
Simulation time	57065551 ps
CPU time	2.48 seconds
Started	May 11 03:53:28 PM PDT 24
Finished	May 11 03:53:32 PM PDT 24
Peak memory	212992 kb
Host	smart-77b4b414-d29f-489f-992a-7b97d5730c13
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161103194 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4161103194
Directory	/workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.199572896
Short name	T192
Test name
Test status
Simulation time	56096729 ps
CPU time	2.11 seconds
Started	May 11 03:53:29 PM PDT 24
Finished	May 11 03:53:32 PM PDT 24
Peak memory	220712 kb
Host	smart-5e9e6a51-4048-46e9-affe-538eed30c451
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199572896 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.199572896
Directory	/workspace/2.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.2439755587
Short name	T41
Test name
Test status
Simulation time	166489617 ps
CPU time	3.64 seconds
Started	May 11 03:53:31 PM PDT 24
Finished	May 11 03:53:35 PM PDT 24
Peak memory	212784 kb
Host	smart-5ad2c862-8842-43fe-86c1-b1588179db4a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439755587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe _tl_intg_err.2439755587
Directory	/workspace/2.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.2769018960
Short name	T252
Test name
Test status
Simulation time	13918507 ps
CPU time	0.69 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:08 PM PDT 24
Peak memory	204276 kb
Host	smart-75eaae7e-6bb5-4f16-9a1f-83ac35711e90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769018960 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test. 2769018960
Directory	/workspace/20.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.3970854280
Short name	T232
Test name
Test status
Simulation time	10879603 ps
CPU time	0.77 seconds
Started	May 11 03:54:03 PM PDT 24
Finished	May 11 03:54:04 PM PDT 24
Peak memory	204344 kb
Host	smart-b99a7a77-d898-44c9-98b7-bbbbe38ea651
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970854280 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test. 3970854280
Directory	/workspace/21.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.148056935
Short name	T255
Test name
Test status
Simulation time	44640439 ps
CPU time	0.69 seconds
Started	May 11 03:54:18 PM PDT 24
Finished	May 11 03:54:20 PM PDT 24
Peak memory	204084 kb
Host	smart-ebf16f9a-4f58-4ffa-be58-8d3600182cf3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148056935 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.148056935
Directory	/workspace/22.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.3126081578
Short name	T94
Test name
Test status
Simulation time	42955816 ps
CPU time	0.8 seconds
Started	May 11 03:54:02 PM PDT 24
Finished	May 11 03:54:03 PM PDT 24
Peak memory	204400 kb
Host	smart-7d87ee11-8c4c-472b-8611-5335d3dcf6b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126081578 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test. 3126081578
Directory	/workspace/24.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.4117503255
Short name	T289
Test name
Test status
Simulation time	14256518 ps
CPU time	0.7 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:09 PM PDT 24
Peak memory	204292 kb
Host	smart-6c8af894-1597-4b0b-b71c-d288c67f6cf1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117503255 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test. 4117503255
Directory	/workspace/25.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.1639160484
Short name	T241
Test name
Test status
Simulation time	32234028 ps
CPU time	0.79 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:09 PM PDT 24
Peak memory	204392 kb
Host	smart-5120d232-6360-4fdd-b18a-dd1a6cc2e2de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639160484 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test. 1639160484
Directory	/workspace/26.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.3226440374
Short name	T258
Test name
Test status
Simulation time	45079906 ps
CPU time	0.75 seconds
Started	May 11 03:54:07 PM PDT 24
Finished	May 11 03:54:09 PM PDT 24
Peak memory	204416 kb
Host	smart-6fe08f6d-e73e-4596-9f5f-64a931eb5b20
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226440374 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test. 3226440374
Directory	/workspace/27.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.1006427114
Short name	T93
Test name
Test status
Simulation time	35477866 ps
CPU time	0.83 seconds
Started	May 11 03:54:11 PM PDT 24
Finished	May 11 03:54:13 PM PDT 24
Peak memory	204192 kb
Host	smart-904f7fb6-c93f-4298-a192-b459082c7b68
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006427114 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test. 1006427114
Directory	/workspace/28.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.2368755526
Short name	T248
Test name
Test status
Simulation time	14339657 ps
CPU time	0.7 seconds
Started	May 11 03:54:17 PM PDT 24
Finished	May 11 03:54:20 PM PDT 24
Peak memory	204032 kb
Host	smart-80a44ab2-70c5-4c52-9c83-66a46a46ae40
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368755526 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test. 2368755526
Directory	/workspace/29.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.2477979161
Short name	T184
Test name
Test status
Simulation time	303747427 ps
CPU time	6.53 seconds
Started	May 11 03:53:38 PM PDT 24
Finished	May 11 03:53:46 PM PDT 24
Peak memory	204556 kb
Host	smart-f44c868c-c565-4fab-a17f-cfdbe13dfb90
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477979161 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs r_aliasing.2477979161
Directory	/workspace/3.keymgr_dpe_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1270051214
Short name	T256
Test name
Test status
Simulation time	457245055 ps
CPU time	7.03 seconds
Started	May 11 03:53:40 PM PDT 24
Finished	May 11 03:53:48 PM PDT 24
Peak memory	204536 kb
Host	smart-a60422b8-e594-4193-9919-2fd63d943cb5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270051214 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs r_bit_bash.1270051214
Directory	/workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.4259764356
Short name	T166
Test name
Test status
Simulation time	74987465 ps
CPU time	0.86 seconds
Started	May 11 03:53:33 PM PDT 24
Finished	May 11 03:53:34 PM PDT 24
Peak memory	204408 kb
Host	smart-c5ee085b-64af-43e3-ae25-863045f7563b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259764356 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs r_hw_reset.4259764356
Directory	/workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.662342900
Short name	T259
Test name
Test status
Simulation time	10937492 ps
CPU time	1.09 seconds
Started	May 11 03:53:37 PM PDT 24
Finished	May 11 03:53:39 PM PDT 24
Peak memory	204520 kb
Host	smart-7318b78f-27e7-43d6-8f48-e1e01ed49bec
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662342900 -assert nopostproc +UVM_TESTNAME= keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.662342900
Directory	/workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.1859068522
Short name	T172
Test name
Test status
Simulation time	42936930 ps
CPU time	0.88 seconds
Started	May 11 03:53:33 PM PDT 24
Finished	May 11 03:53:35 PM PDT 24
Peak memory	204456 kb
Host	smart-902ef1af-e800-4a60-a589-8c09ace762b7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859068522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.1 859068522
Directory	/workspace/3.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.4277172895
Short name	T238
Test name
Test status
Simulation time	37917966 ps
CPU time	0.74 seconds
Started	May 11 03:53:34 PM PDT 24
Finished	May 11 03:53:35 PM PDT 24
Peak memory	204408 kb
Host	smart-5dcbab62-fe0a-48f6-9fe6-5afa359aa197
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277172895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.4 277172895
Directory	/workspace/3.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.588109556
Short name	T198
Test name
Test status
Simulation time	113202233 ps
CPU time	2.1 seconds
Started	May 11 03:53:37 PM PDT 24
Finished	May 11 03:53:40 PM PDT 24
Peak memory	204528 kb
Host	smart-f139a0ce-a98f-4eae-9bc0-35c7a85a2892
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588109556 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ= keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ke ymgr_dpe_same_csr_outstanding.588109556
Directory	/workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.945892351
Short name	T64
Test name
Test status
Simulation time	138538439 ps
CPU time	1.67 seconds
Started	May 11 03:53:32 PM PDT 24
Finished	May 11 03:53:34 PM PDT 24
Peak memory	213052 kb
Host	smart-73a895a4-c3c7-42d3-be69-b7249dab58f0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945892351 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymg r_dpe_shadow_reg_errors.945892351
Directory	/workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.4120203484
Short name	T257
Test name
Test status
Simulation time	112284433 ps
CPU time	3.12 seconds
Started	May 11 03:53:32 PM PDT 24
Finished	May 11 03:53:35 PM PDT 24
Peak memory	213044 kb
Host	smart-c502e1a5-dd9d-4b19-b4a7-b683cfb61032
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120203484 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.4120203484
Directory	/workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.545926771
Short name	T276
Test name
Test status
Simulation time	100459262 ps
CPU time	3.8 seconds
Started	May 11 03:53:34 PM PDT 24
Finished	May 11 03:53:38 PM PDT 24
Peak memory	216052 kb
Host	smart-0f024b24-2fc0-4e6b-87c2-ddd4b32d4363
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545926771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.545926771
Directory	/workspace/3.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.2986885980
Short name	T291
Test name
Test status
Simulation time	25792141 ps
CPU time	0.73 seconds
Started	May 11 03:54:11 PM PDT 24
Finished	May 11 03:54:13 PM PDT 24
Peak memory	204300 kb
Host	smart-228a8820-a3a5-4224-abaa-f0b60da99457
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986885980 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test. 2986885980
Directory	/workspace/30.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.769467387
Short name	T229
Test name
Test status
Simulation time	90082605 ps
CPU time	0.85 seconds
Started	May 11 03:54:07 PM PDT 24
Finished	May 11 03:54:10 PM PDT 24
Peak memory	204340 kb
Host	smart-18027399-530b-4f22-9eef-4a2e35d438fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769467387 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.769467387
Directory	/workspace/31.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.4107232484
Short name	T190
Test name
Test status
Simulation time	14523545 ps
CPU time	0.74 seconds
Started	May 11 03:54:05 PM PDT 24
Finished	May 11 03:54:07 PM PDT 24
Peak memory	204352 kb
Host	smart-0a09fe48-6861-4408-95fc-85995a64ba43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107232484 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test. 4107232484
Directory	/workspace/32.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.583063140
Short name	T223
Test name
Test status
Simulation time	29218560 ps
CPU time	0.67 seconds
Started	May 11 03:54:16 PM PDT 24
Finished	May 11 03:54:18 PM PDT 24
Peak memory	204056 kb
Host	smart-e37dac3b-71ae-48ce-8287-a9e3b96e66b6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583063140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.583063140
Directory	/workspace/33.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.930318089
Short name	T95
Test name
Test status
Simulation time	136803681 ps
CPU time	0.79 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	204388 kb
Host	smart-4c4dffad-a565-4ea1-afcd-451ec49ccf90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930318089 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.930318089
Directory	/workspace/34.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3834812294
Short name	T287
Test name
Test status
Simulation time	15569467 ps
CPU time	0.8 seconds
Started	May 11 03:54:11 PM PDT 24
Finished	May 11 03:54:13 PM PDT 24
Peak memory	204108 kb
Host	smart-fabc12a6-0808-4f87-9f43-6e23635a9a7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834812294 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test. 3834812294
Directory	/workspace/35.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.1179967159
Short name	T214
Test name
Test status
Simulation time	41147235 ps
CPU time	0.78 seconds
Started	May 11 03:54:09 PM PDT 24
Finished	May 11 03:54:12 PM PDT 24
Peak memory	204392 kb
Host	smart-d045a9b4-54b2-42ce-bc61-e65f802072a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179967159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test. 1179967159
Directory	/workspace/36.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.2050533001
Short name	T191
Test name
Test status
Simulation time	11592748 ps
CPU time	0.89 seconds
Started	May 11 03:54:02 PM PDT 24
Finished	May 11 03:54:04 PM PDT 24
Peak memory	204416 kb
Host	smart-8d10d16d-bb80-4372-aaf9-a83bdc6038af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050533001 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test. 2050533001
Directory	/workspace/37.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3586836911
Short name	T206
Test name
Test status
Simulation time	15199888 ps
CPU time	0.84 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:09 PM PDT 24
Peak memory	204412 kb
Host	smart-bf7ce87c-b1f0-4270-a760-23260acf2dd9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586836911 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test. 3586836911
Directory	/workspace/38.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.1511552857
Short name	T168
Test name
Test status
Simulation time	37520764 ps
CPU time	0.68 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:08 PM PDT 24
Peak memory	204252 kb
Host	smart-155735f7-e651-4608-8d21-c1a070d4478a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511552857 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test. 1511552857
Directory	/workspace/39.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.3543179787
Short name	T278
Test name
Test status
Simulation time	554424446 ps
CPU time	6.23 seconds
Started	May 11 03:53:40 PM PDT 24
Finished	May 11 03:53:47 PM PDT 24
Peak memory	204604 kb
Host	smart-48db643a-af99-4759-8f7e-947a67ed4125
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543179787 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs r_aliasing.3543179787
Directory	/workspace/4.keymgr_dpe_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3696259179
Short name	T181
Test name
Test status
Simulation time	1212173470 ps
CPU time	9.41 seconds
Started	May 11 03:53:36 PM PDT 24
Finished	May 11 03:53:47 PM PDT 24
Peak memory	204604 kb
Host	smart-5a20f8ee-2ca9-4a7a-a947-ac63ea753bba
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696259179 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs r_bit_bash.3696259179
Directory	/workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.885254698
Short name	T236
Test name
Test status
Simulation time	108248966 ps
CPU time	1.07 seconds
Started	May 11 03:53:42 PM PDT 24
Finished	May 11 03:53:44 PM PDT 24
Peak memory	204284 kb
Host	smart-e3f57414-4f4e-4ebf-b8a5-1e0ec3cdc96a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885254698 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr _hw_reset.885254698
Directory	/workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1157686217
Short name	T280
Test name
Test status
Simulation time	48159705 ps
CPU time	1.17 seconds
Started	May 11 03:53:36 PM PDT 24
Finished	May 11 03:53:39 PM PDT 24
Peak memory	204504 kb
Host	smart-88dc93a7-5628-4f81-b8ac-26557aedc1ce
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157686217 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.1157686217
Directory	/workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1044026644
Short name	T177
Test name
Test status
Simulation time	13880368 ps
CPU time	0.97 seconds
Started	May 11 03:53:40 PM PDT 24
Finished	May 11 03:53:42 PM PDT 24
Peak memory	204432 kb
Host	smart-28e8abe7-d23e-4e82-907a-3a8d13b929ea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044026644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1 044026644
Directory	/workspace/4.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.2319971300
Short name	T225
Test name
Test status
Simulation time	39545398 ps
CPU time	0.87 seconds
Started	May 11 03:53:37 PM PDT 24
Finished	May 11 03:53:39 PM PDT 24
Peak memory	204404 kb
Host	smart-2f858388-aa9f-43a8-a113-53a11a06235c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319971300 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.2 319971300
Directory	/workspace/4.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.4166136075
Short name	T269
Test name
Test status
Simulation time	50853333 ps
CPU time	1.35 seconds
Started	May 11 03:53:37 PM PDT 24
Finished	May 11 03:53:39 PM PDT 24
Peak memory	204488 kb
Host	smart-ce698209-6cd2-4eae-a8bc-bbe702b4b883
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166136075 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k eymgr_dpe_same_csr_outstanding.4166136075
Directory	/workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.2857299286
Short name	T57
Test name
Test status
Simulation time	1356533981 ps
CPU time	2.21 seconds
Started	May 11 03:53:37 PM PDT 24
Finished	May 11 03:53:40 PM PDT 24
Peak memory	213088 kb
Host	smart-db98bebb-588a-496e-b5e2-365b8f4afe3d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857299286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym gr_dpe_shadow_reg_errors.2857299286
Directory	/workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.4192421361
Short name	T169
Test name
Test status
Simulation time	94352356 ps
CPU time	2.36 seconds
Started	May 11 03:53:42 PM PDT 24
Finished	May 11 03:53:45 PM PDT 24
Peak memory	212828 kb
Host	smart-d06acc48-29c0-4ced-85fc-bb11cd7e0a09
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192421361 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.4192421361
Directory	/workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.2942235909
Short name	T239
Test name
Test status
Simulation time	36465689 ps
CPU time	2.2 seconds
Started	May 11 03:53:39 PM PDT 24
Finished	May 11 03:53:42 PM PDT 24
Peak memory	212808 kb
Host	smart-077a09e7-f12e-4f06-b301-a08582a087b7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942235909 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.2 942235909
Directory	/workspace/4.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.4269072290
Short name	T46
Test name
Test status
Simulation time	70318422 ps
CPU time	2.84 seconds
Started	May 11 03:53:36 PM PDT 24
Finished	May 11 03:53:40 PM PDT 24
Peak memory	204568 kb
Host	smart-7df8def3-b4eb-4027-a2e3-bfcf9eeed963
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269072290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe _tl_intg_err.4269072290
Directory	/workspace/4.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.2311180359
Short name	T282
Test name
Test status
Simulation time	42878301 ps
CPU time	0.86 seconds
Started	May 11 03:54:08 PM PDT 24
Finished	May 11 03:54:11 PM PDT 24
Peak memory	204372 kb
Host	smart-638dbe76-3064-49a6-88f3-fda0713504aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311180359 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test. 2311180359
Directory	/workspace/40.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.2629901907
Short name	T286
Test name
Test status
Simulation time	200561885 ps
CPU time	0.72 seconds
Started	May 11 03:54:18 PM PDT 24
Finished	May 11 03:54:20 PM PDT 24
Peak memory	204084 kb
Host	smart-82591c0c-0d71-4c9b-972e-ac7d22708f9e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629901907 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test. 2629901907
Directory	/workspace/41.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.3220013020
Short name	T274
Test name
Test status
Simulation time	28892306 ps
CPU time	0.66 seconds
Started	May 11 03:54:18 PM PDT 24
Finished	May 11 03:54:20 PM PDT 24
Peak memory	203968 kb
Host	smart-42f9f580-69fc-4a94-9b85-d4f231ed33fc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220013020 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test. 3220013020
Directory	/workspace/42.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.961833521
Short name	T193
Test name
Test status
Simulation time	41755902 ps
CPU time	0.72 seconds
Started	May 11 03:54:07 PM PDT 24
Finished	May 11 03:54:10 PM PDT 24
Peak memory	204312 kb
Host	smart-eb9f5286-f719-4a6d-8f1c-219f97e96891
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961833521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.961833521
Directory	/workspace/43.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.3268044816
Short name	T284
Test name
Test status
Simulation time	38058494 ps
CPU time	0.73 seconds
Started	May 11 03:54:02 PM PDT 24
Finished	May 11 03:54:04 PM PDT 24
Peak memory	204376 kb
Host	smart-91f87874-131e-46ec-a69e-38ca585686fd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268044816 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test. 3268044816
Directory	/workspace/44.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.2431823437
Short name	T265
Test name
Test status
Simulation time	14121858 ps
CPU time	0.75 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:08 PM PDT 24
Peak memory	204404 kb
Host	smart-a6f7d68a-a964-48c4-8062-1fb3ba3debfe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431823437 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test. 2431823437
Directory	/workspace/45.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.2875203871
Short name	T302
Test name
Test status
Simulation time	11035621 ps
CPU time	0.73 seconds
Started	May 11 03:54:15 PM PDT 24
Finished	May 11 03:54:17 PM PDT 24
Peak memory	204372 kb
Host	smart-827a455e-a13d-4501-acf0-d9bba3cf907d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875203871 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test. 2875203871
Directory	/workspace/46.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.794526017
Short name	T295
Test name
Test status
Simulation time	35038320 ps
CPU time	0.7 seconds
Started	May 11 03:54:08 PM PDT 24
Finished	May 11 03:54:11 PM PDT 24
Peak memory	204328 kb
Host	smart-25726336-e38a-4c43-aa2f-830243bbedd1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794526017 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.794526017
Directory	/workspace/47.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.766209459
Short name	T261
Test name
Test status
Simulation time	11714107 ps
CPU time	0.66 seconds
Started	May 11 03:54:06 PM PDT 24
Finished	May 11 03:54:09 PM PDT 24
Peak memory	204304 kb
Host	smart-78a92e81-15f5-43fb-b790-f089e74e247e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766209459 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.766209459
Directory	/workspace/48.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.3448171154
Short name	T38
Test name
Test status
Simulation time	13723501 ps
CPU time	0.81 seconds
Started	May 11 03:54:04 PM PDT 24
Finished	May 11 03:54:06 PM PDT 24
Peak memory	204376 kb
Host	smart-c263f5a2-c674-497e-901c-92b5870f4dd8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448171154 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test. 3448171154
Directory	/workspace/49.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.251718469
Short name	T254
Test name
Test status
Simulation time	166994312 ps
CPU time	1.01 seconds
Started	May 11 03:53:40 PM PDT 24
Finished	May 11 03:53:42 PM PDT 24
Peak memory	204476 kb
Host	smart-ec2dd822-42ba-4eb1-8aa0-1f082ce1dd26
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251718469 -assert nopostproc +UVM_TESTNAME= keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.251718469
Directory	/workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.2214767978
Short name	T194
Test name
Test status
Simulation time	119729088 ps
CPU time	1.08 seconds
Started	May 11 03:53:39 PM PDT 24
Finished	May 11 03:53:41 PM PDT 24
Peak memory	204496 kb
Host	smart-5c0aa0be-1f43-4f63-b979-cf2165dc98e3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214767978 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.2 214767978
Directory	/workspace/5.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.3696252871
Short name	T226
Test name
Test status
Simulation time	35734112 ps
CPU time	0.78 seconds
Started	May 11 03:53:39 PM PDT 24
Finished	May 11 03:53:41 PM PDT 24
Peak memory	204352 kb
Host	smart-129f5ca7-9c15-4e96-be84-83958abaf369
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696252871 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.3 696252871
Directory	/workspace/5.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.399922887
Short name	T35
Test name
Test status
Simulation time	169358613 ps
CPU time	1.41 seconds
Started	May 11 03:53:40 PM PDT 24
Finished	May 11 03:53:42 PM PDT 24
Peak memory	204568 kb
Host	smart-4bd72b1b-74fc-49fd-9404-83355bbbff57
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399922887 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ= keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke ymgr_dpe_same_csr_outstanding.399922887
Directory	/workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1051483971
Short name	T290
Test name
Test status
Simulation time	270498032 ps
CPU time	2.51 seconds
Started	May 11 03:53:38 PM PDT 24
Finished	May 11 03:53:41 PM PDT 24
Peak memory	213056 kb
Host	smart-7016c7b8-fa21-40a7-83fb-330f323c50d1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051483971 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym gr_dpe_shadow_reg_errors.1051483971
Directory	/workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.479998620
Short name	T187
Test name
Test status
Simulation time	86240599 ps
CPU time	2.9 seconds
Started	May 11 03:53:39 PM PDT 24
Finished	May 11 03:53:42 PM PDT 24
Peak memory	213216 kb
Host	smart-056474f3-afe5-4de6-911d-f94e00786346
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479998620 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_ TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.479998620
Directory	/workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2177769521
Short name	T218
Test name
Test status
Simulation time	271949498 ps
CPU time	4.13 seconds
Started	May 11 03:53:43 PM PDT 24
Finished	May 11 03:53:48 PM PDT 24
Peak memory	212780 kb
Host	smart-99a8762d-0600-4927-bb64-d8458a1b5b29
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177769521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.2 177769521
Directory	/workspace/5.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.3918351933
Short name	T213
Test name
Test status
Simulation time	57028890 ps
CPU time	1.05 seconds
Started	May 11 03:53:43 PM PDT 24
Finished	May 11 03:53:44 PM PDT 24
Peak memory	204632 kb
Host	smart-a71a5a25-3ee3-42ff-8ff7-3c4ecacfc03f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918351933 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.3918351933
Directory	/workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2405607648
Short name	T91
Test name
Test status
Simulation time	21864440 ps
CPU time	1.33 seconds
Started	May 11 03:53:39 PM PDT 24
Finished	May 11 03:53:41 PM PDT 24
Peak memory	204500 kb
Host	smart-48e37226-46c1-4b78-ac78-e899b623e20c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405607648 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2 405607648
Directory	/workspace/6.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.45826385
Short name	T279
Test name
Test status
Simulation time	38427612 ps
CPU time	0.72 seconds
Started	May 11 03:53:40 PM PDT 24
Finished	May 11 03:53:41 PM PDT 24
Peak memory	204356 kb
Host	smart-9b0b3305-34b2-42c2-9cd9-eff913e470b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45826385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.45826385
Directory	/workspace/6.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.2483531004
Short name	T207
Test name
Test status
Simulation time	90325911 ps
CPU time	2.2 seconds
Started	May 11 03:53:44 PM PDT 24
Finished	May 11 03:53:47 PM PDT 24
Peak memory	204552 kb
Host	smart-33f37c51-d790-43a5-91ab-0b023b8577b6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483531004 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k eymgr_dpe_same_csr_outstanding.2483531004
Directory	/workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.3371540689
Short name	T277
Test name
Test status
Simulation time	79384951 ps
CPU time	1.93 seconds
Started	May 11 03:53:42 PM PDT 24
Finished	May 11 03:53:45 PM PDT 24
Peak memory	212988 kb
Host	smart-109389c8-747f-4493-9729-a149bdf2fe47
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371540689 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym gr_dpe_shadow_reg_errors.3371540689
Directory	/workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2720420561
Short name	T235
Test name
Test status
Simulation time	136106366 ps
CPU time	3.9 seconds
Started	May 11 03:53:41 PM PDT 24
Finished	May 11 03:53:46 PM PDT 24
Peak memory	212996 kb
Host	smart-fcd084b8-f69d-4dd6-8e2e-ad1e6dd9e669
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720420561 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2720420561
Directory	/workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.364018686
Short name	T205
Test name
Test status
Simulation time	281654985 ps
CPU time	5.02 seconds
Started	May 11 03:53:42 PM PDT 24
Finished	May 11 03:53:48 PM PDT 24
Peak memory	212740 kb
Host	smart-1a4c35e6-7572-417e-96ab-6ef9fc6dce22
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364018686 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.364018686
Directory	/workspace/6.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.2400472838
Short name	T242
Test name
Test status
Simulation time	54446717 ps
CPU time	0.99 seconds
Started	May 11 03:53:46 PM PDT 24
Finished	May 11 03:53:47 PM PDT 24
Peak memory	204484 kb
Host	smart-bbd78b85-f594-49df-9f6c-fffa08c72e46
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400472838 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.2400472838
Directory	/workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.1006851461
Short name	T78
Test name
Test status
Simulation time	31249056 ps
CPU time	1.03 seconds
Started	May 11 03:53:44 PM PDT 24
Finished	May 11 03:53:46 PM PDT 24
Peak memory	204508 kb
Host	smart-2a54102a-9276-4b13-bf5e-ac8c24209522
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006851461 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.1 006851461
Directory	/workspace/7.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.3947999981
Short name	T243
Test name
Test status
Simulation time	52006112 ps
CPU time	0.92 seconds
Started	May 11 03:53:44 PM PDT 24
Finished	May 11 03:53:46 PM PDT 24
Peak memory	204332 kb
Host	smart-36827371-b0f5-42bb-9749-05a3315d03d2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947999981 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.3 947999981
Directory	/workspace/7.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.3608623867
Short name	T82
Test name
Test status
Simulation time	406576785 ps
CPU time	3.19 seconds
Started	May 11 03:53:47 PM PDT 24
Finished	May 11 03:53:50 PM PDT 24
Peak memory	204572 kb
Host	smart-a645301b-00e1-48b8-b3e2-7be5df899a06
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608623867 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k eymgr_dpe_same_csr_outstanding.3608623867
Directory	/workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.2322327704
Short name	T92
Test name
Test status
Simulation time	245483596 ps
CPU time	1.45 seconds
Started	May 11 03:53:46 PM PDT 24
Finished	May 11 03:53:48 PM PDT 24
Peak memory	213072 kb
Host	smart-f6172298-ba5c-456f-a8e7-6f27e4d53582
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322327704 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym gr_dpe_shadow_reg_errors.2322327704
Directory	/workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2403017027
Short name	T224
Test name
Test status
Simulation time	217741083 ps
CPU time	3.35 seconds
Started	May 11 03:53:46 PM PDT 24
Finished	May 11 03:53:50 PM PDT 24
Peak memory	212984 kb
Host	smart-c0bd0a95-ce9e-4bb7-a1bf-2ab573c61a6c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403017027 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2403017027
Directory	/workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.3224619989
Short name	T30
Test name
Test status
Simulation time	338712504 ps
CPU time	3.01 seconds
Started	May 11 03:53:46 PM PDT 24
Finished	May 11 03:53:49 PM PDT 24
Peak memory	212792 kb
Host	smart-09f3d6b9-ae47-4126-aef9-2afd687808f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224619989 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.3 224619989
Directory	/workspace/7.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.3208807051
Short name	T55
Test name
Test status
Simulation time	171622201 ps
CPU time	4.62 seconds
Started	May 11 03:53:44 PM PDT 24
Finished	May 11 03:53:49 PM PDT 24
Peak memory	204784 kb
Host	smart-930c78bb-f6ca-4a40-9c1a-4ce9e0049f8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208807051 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe _tl_intg_err.3208807051
Directory	/workspace/7.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.220553674
Short name	T219
Test name
Test status
Simulation time	18634194 ps
CPU time	1.56 seconds
Started	May 11 03:53:51 PM PDT 24
Finished	May 11 03:53:53 PM PDT 24
Peak memory	212852 kb
Host	smart-70c18165-5ccc-4ccd-a77c-8bfd51e51052
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220553674 -assert nopostproc +UVM_TESTNAME= keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.220553674
Directory	/workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.17759040
Short name	T263
Test name
Test status
Simulation time	9993200 ps
CPU time	0.92 seconds
Started	May 11 03:53:52 PM PDT 24
Finished	May 11 03:53:54 PM PDT 24
Peak memory	204460 kb
Host	smart-4bb32ac9-28fd-4774-9ba3-ecbf033786a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17759040 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.17759040
Directory	/workspace/8.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.2370775170
Short name	T233
Test name
Test status
Simulation time	17982448 ps
CPU time	0.86 seconds
Started	May 11 03:53:51 PM PDT 24
Finished	May 11 03:53:53 PM PDT 24
Peak memory	204412 kb
Host	smart-04af55a4-5170-4432-96c1-5e7380778111
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370775170 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.2 370775170
Directory	/workspace/8.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.1318804965
Short name	T195
Test name
Test status
Simulation time	26754441 ps
CPU time	1.68 seconds
Started	May 11 03:53:50 PM PDT 24
Finished	May 11 03:53:52 PM PDT 24
Peak memory	204544 kb
Host	smart-aa388736-9019-412d-bec4-17f5154a47e2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318804965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k eymgr_dpe_same_csr_outstanding.1318804965
Directory	/workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.772143405
Short name	T250
Test name
Test status
Simulation time	63483403 ps
CPU time	1.62 seconds
Started	May 11 03:53:52 PM PDT 24
Finished	May 11 03:53:55 PM PDT 24
Peak memory	212924 kb
Host	smart-13e39300-840f-47ac-a091-6e679e2e1c7f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772143405 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymg r_dpe_shadow_reg_errors.772143405
Directory	/workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4089719754
Short name	T271
Test name
Test status
Simulation time	196774121 ps
CPU time	2.47 seconds
Started	May 11 03:53:52 PM PDT 24
Finished	May 11 03:53:55 PM PDT 24
Peak memory	212996 kb
Host	smart-6b9f4785-eb49-4bda-9593-4b6be0602f55
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089719754 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM _TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4089719754
Directory	/workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3489321046
Short name	T37
Test name
Test status
Simulation time	83648667 ps
CPU time	1.78 seconds
Started	May 11 03:53:52 PM PDT 24
Finished	May 11 03:53:54 PM PDT 24
Peak memory	215952 kb
Host	smart-99f46e85-c6e4-4087-ac38-0024a4f75021
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489321046 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.3 489321046
Directory	/workspace/8.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.1876389323
Short name	T32
Test name
Test status
Simulation time	76639586 ps
CPU time	3.06 seconds
Started	May 11 03:53:54 PM PDT 24
Finished	May 11 03:53:58 PM PDT 24
Peak memory	212672 kb
Host	smart-5b7a03cd-5517-4a92-b22e-4465b0a6f249
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876389323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe _tl_intg_err.1876389323
Directory	/workspace/8.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.2491527927
Short name	T230
Test name
Test status
Simulation time	13507697 ps
CPU time	1.12 seconds
Started	May 11 03:53:53 PM PDT 24
Finished	May 11 03:53:55 PM PDT 24
Peak memory	204516 kb
Host	smart-2133bd7c-8695-4c81-9387-68abf3259b31
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491527927 -assert nopostproc +UVM_TESTNAME =keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.2491527927
Directory	/workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.823369414
Short name	T61
Test name
Test status
Simulation time	60611972 ps
CPU time	1.14 seconds
Started	May 11 03:53:52 PM PDT 24
Finished	May 11 03:53:54 PM PDT 24
Peak memory	204492 kb
Host	smart-83123cc2-d8c2-4ead-9bf1-d0ecc17e208a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823369414 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.823369414
Directory	/workspace/9.keymgr_dpe_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.681518237
Short name	T267
Test name
Test status
Simulation time	8429628 ps
CPU time	0.77 seconds
Started	May 11 03:53:52 PM PDT 24
Finished	May 11 03:53:53 PM PDT 24
Peak memory	204368 kb
Host	smart-5f57dd60-adcc-432f-a646-02279ad072a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681518237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.681518237
Directory	/workspace/9.keymgr_dpe_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2176160431
Short name	T178
Test name
Test status
Simulation time	34292600 ps
CPU time	1.77 seconds
Started	May 11 03:53:54 PM PDT 24
Finished	May 11 03:53:56 PM PDT 24
Peak memory	204572 kb
Host	smart-1cffa4e2-8d69-47fc-b39c-29f91278f90d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176160431 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ =keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k eymgr_dpe_same_csr_outstanding.2176160431
Directory	/workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.3980735764
Short name	T249
Test name
Test status
Simulation time	93768030 ps
CPU time	1.91 seconds
Started	May 11 03:53:49 PM PDT 24
Finished	May 11 03:53:51 PM PDT 24
Peak memory	213092 kb
Host	smart-6939c954-561f-42b3-b8f4-b6b9aa6798ad
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980735764 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym gr_dpe_shadow_reg_errors.3980735764
Directory	/workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.562026712
Short name	T240
Test name
Test status
Simulation time	261421776 ps
CPU time	3.32 seconds
Started	May 11 03:53:51 PM PDT 24
Finished	May 11 03:53:55 PM PDT 24
Peak memory	221196 kb
Host	smart-585c9e0f-030b-4856-93d3-d15c6745e8f9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562026712 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_ TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.562026712
Directory	/workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.737506400
Short name	T203
Test name
Test status
Simulation time	321520791 ps
CPU time	2.35 seconds
Started	May 11 03:53:54 PM PDT 24
Finished	May 11 03:53:57 PM PDT 24
Peak memory	212784 kb
Host	smart-358c3607-4b43-45c6-99dd-7cf72717e74f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737506400 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.737506400
Directory	/workspace/9.keymgr_dpe_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1613276125
Short name	T54
Test name
Test status
Simulation time	659884641 ps
CPU time	6.49 seconds
Started	May 11 03:53:50 PM PDT 24
Finished	May 11 03:53:57 PM PDT 24
Peak memory	213964 kb
Host	smart-b4891b32-8738-4ab4-a379-644a97f7cc18
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613276125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe _tl_intg_err.1613276125
Directory	/workspace/9.keymgr_dpe_tl_intg_err/latest

Test location	/workspace/coverage/default/0.keymgr_dpe_alert_test.3099964846
Short name	T133
Test name
Test status
Simulation time	23824890 ps
CPU time	0.78 seconds
Started	May 11 01:38:29 PM PDT 24
Finished	May 11 01:38:31 PM PDT 24
Peak memory	205420 kb
Host	smart-021f2bc9-3ed4-4cd0-9a55-59f2d3b29916
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099964846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.3 099964846
Directory	/workspace/0.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/1.keymgr_dpe_alert_test.2644794335
Short name	T138
Test name
Test status
Simulation time	12398305 ps
CPU time	0.89 seconds
Started	May 11 01:38:29 PM PDT 24
Finished	May 11 01:38:30 PM PDT 24
Peak memory	205404 kb
Host	smart-7e320a60-aed3-4420-aeea-99ad2a588144
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644794335 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.2 644794335
Directory	/workspace/1.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/10.keymgr_dpe_alert_test.180965050
Short name	T148
Test name
Test status
Simulation time	13439124 ps
CPU time	0.87 seconds
Started	May 11 01:38:34 PM PDT 24
Finished	May 11 01:38:35 PM PDT 24
Peak memory	205388 kb
Host	smart-c6605b80-ccaa-4c90-8dd7-e70364426706
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180965050 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.180965050
Directory	/workspace/10.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/10.keymgr_dpe_smoke.2922879735
Short name	T161
Test name
Test status
Simulation time	1889982474 ps
CPU time	32.17 seconds
Started	May 11 01:38:34 PM PDT 24
Finished	May 11 01:39:07 PM PDT 24
Peak memory	207820 kb
Host	smart-e44df842-f6d5-4d1b-bde4-c781acf073c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922879735 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.2922879735
Directory	/workspace/10.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/11.keymgr_dpe_alert_test.4231811589
Short name	T126
Test name
Test status
Simulation time	16125716 ps
CPU time	0.72 seconds
Started	May 11 01:38:35 PM PDT 24
Finished	May 11 01:38:36 PM PDT 24
Peak memory	205332 kb
Host	smart-856f7544-bccc-4fb7-8e30-92bcb5ae459c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231811589 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test. 4231811589
Directory	/workspace/11.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/11.keymgr_dpe_smoke.1760671546
Short name	T129
Test name
Test status
Simulation time	754343848 ps
CPU time	19.08 seconds
Started	May 11 01:38:33 PM PDT 24
Finished	May 11 01:38:52 PM PDT 24
Peak memory	208352 kb
Host	smart-e53d60a6-c4f8-4044-b734-637a9dc030d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760671546 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.1760671546
Directory	/workspace/11.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/12.keymgr_dpe_alert_test.374966852
Short name	T123
Test name
Test status
Simulation time	34276891 ps
CPU time	0.89 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:39 PM PDT 24
Peak memory	205420 kb
Host	smart-8b0d6bf9-dcbe-4475-95cf-1dfe9920f04d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374966852 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.374966852
Directory	/workspace/12.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/12.keymgr_dpe_smoke.3482637955
Short name	T26
Test name
Test status
Simulation time	13003130130 ps
CPU time	48.09 seconds
Started	May 11 01:38:32 PM PDT 24
Finished	May 11 01:39:20 PM PDT 24
Peak memory	208236 kb
Host	smart-310e4590-5110-42a8-a0a1-9675ef76b2eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482637955 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.3482637955
Directory	/workspace/12.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/13.keymgr_dpe_smoke.3304176242
Short name	T132
Test name
Test status
Simulation time	354185495 ps
CPU time	13.54 seconds
Started	May 11 01:38:31 PM PDT 24
Finished	May 11 01:38:45 PM PDT 24
Peak memory	206300 kb
Host	smart-25f8b717-f578-4111-a736-c2f76133cfb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304176242 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.3304176242
Directory	/workspace/13.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/14.keymgr_dpe_alert_test.1221995297
Short name	T143
Test name
Test status
Simulation time	11122501 ps
CPU time	0.87 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:39 PM PDT 24
Peak memory	205364 kb
Host	smart-06b2dcd1-772e-4d7a-8ac1-b0826057a705
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221995297 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test. 1221995297
Directory	/workspace/14.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/15.keymgr_dpe_alert_test.198538880
Short name	T154
Test name
Test status
Simulation time	11930223 ps
CPU time	0.72 seconds
Started	May 11 01:38:33 PM PDT 24
Finished	May 11 01:38:34 PM PDT 24
Peak memory	205408 kb
Host	smart-740a5601-cef2-4dad-b067-7e105fbba18e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198538880 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.198538880
Directory	/workspace/15.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/16.keymgr_dpe_alert_test.4275320564
Short name	T113
Test name
Test status
Simulation time	18063881 ps
CPU time	0.77 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:40 PM PDT 24
Peak memory	205440 kb
Host	smart-7b06be8f-db39-41e4-85c4-c23921bc400f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275320564 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test. 4275320564
Directory	/workspace/16.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/17.keymgr_dpe_alert_test.856970641
Short name	T14
Test name
Test status
Simulation time	31657690 ps
CPU time	0.74 seconds
Started	May 11 01:38:36 PM PDT 24
Finished	May 11 01:38:37 PM PDT 24
Peak memory	205396 kb
Host	smart-46b59261-56cd-4195-91a8-b46eddf37a6c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856970641 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.856970641
Directory	/workspace/17.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/18.keymgr_dpe_alert_test.3658206840
Short name	T162
Test name
Test status
Simulation time	49939397 ps
CPU time	0.72 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:40 PM PDT 24
Peak memory	205360 kb
Host	smart-d1de6292-d96f-41b3-9294-09fe921ed950
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658206840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test. 3658206840
Directory	/workspace/18.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/18.keymgr_dpe_smoke.4099489169
Short name	T151
Test name
Test status
Simulation time	1087129900 ps
CPU time	18.67 seconds
Started	May 11 01:38:35 PM PDT 24
Finished	May 11 01:38:54 PM PDT 24
Peak memory	208160 kb
Host	smart-71e4a837-2312-4b46-82fb-5cad122e5d34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4099489169 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.4099489169
Directory	/workspace/18.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/19.keymgr_dpe_alert_test.2673195496
Short name	T163
Test name
Test status
Simulation time	41720282 ps
CPU time	0.87 seconds
Started	May 11 01:38:36 PM PDT 24
Finished	May 11 01:38:37 PM PDT 24
Peak memory	205408 kb
Host	smart-3abe121d-f2b8-49c6-82ce-e4a79ab046ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673195496 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test. 2673195496
Directory	/workspace/19.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/19.keymgr_dpe_smoke.2141658189
Short name	T25
Test name
Test status
Simulation time	3565250310 ps
CPU time	16.85 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:56 PM PDT 24
Peak memory	207972 kb
Host	smart-3db94a47-6787-44ee-81e6-ea59eb1a655f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141658189 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.2141658189
Directory	/workspace/19.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/2.keymgr_dpe_alert_test.2980452887
Short name	T130
Test name
Test status
Simulation time	19903180 ps
CPU time	0.81 seconds
Started	May 11 01:38:29 PM PDT 24
Finished	May 11 01:38:30 PM PDT 24
Peak memory	205272 kb
Host	smart-72e538a6-96b3-4af9-9cc4-f45df7522fd4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980452887 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.2 980452887
Directory	/workspace/2.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/2.keymgr_dpe_sec_cm.3148083317
Short name	T6
Test name
Test status
Simulation time	546199263 ps
CPU time	5.77 seconds
Started	May 11 01:38:32 PM PDT 24
Finished	May 11 01:38:38 PM PDT 24
Peak memory	232844 kb
Host	smart-fb25b997-b46c-48d7-88c3-cc9c58fd2941
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148083317 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.3148083317
Directory	/workspace/2.keymgr_dpe_sec_cm/latest

Test location	/workspace/coverage/default/20.keymgr_dpe_alert_test.4118572855
Short name	T116
Test name
Test status
Simulation time	34452741 ps
CPU time	0.75 seconds
Started	May 11 01:38:36 PM PDT 24
Finished	May 11 01:38:37 PM PDT 24
Peak memory	205424 kb
Host	smart-c92c162a-6264-4969-ab99-e5f07f84ce0d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118572855 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test. 4118572855
Directory	/workspace/20.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/21.keymgr_dpe_alert_test.1391769826
Short name	T139
Test name
Test status
Simulation time	55060733 ps
CPU time	0.73 seconds
Started	May 11 01:38:39 PM PDT 24
Finished	May 11 01:38:40 PM PDT 24
Peak memory	205348 kb
Host	smart-38b6ec63-abc2-4bec-9c2f-5502bdb4d15d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391769826 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test. 1391769826
Directory	/workspace/21.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/21.keymgr_dpe_smoke.3685547934
Short name	T10
Test name
Test status
Simulation time	5991630351 ps
CPU time	22.73 seconds
Started	May 11 01:38:36 PM PDT 24
Finished	May 11 01:38:59 PM PDT 24
Peak memory	206656 kb
Host	smart-99691c73-e702-4119-b006-3b01c2836094
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685547934 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.3685547934
Directory	/workspace/21.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/22.keymgr_dpe_alert_test.2655915451
Short name	T118
Test name
Test status
Simulation time	11100722 ps
CPU time	0.74 seconds
Started	May 11 01:38:37 PM PDT 24
Finished	May 11 01:38:39 PM PDT 24
Peak memory	205396 kb
Host	smart-32cb3568-0c57-47d7-b537-d2496d282a80
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655915451 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test. 2655915451
Directory	/workspace/22.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/22.keymgr_dpe_smoke.493759522
Short name	T75
Test name
Test status
Simulation time	1320859885 ps
CPU time	22.07 seconds
Started	May 11 01:38:35 PM PDT 24
Finished	May 11 01:38:58 PM PDT 24
Peak memory	207808 kb
Host	smart-ab95636d-a299-4067-b456-edff89d92e00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493759522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.493759522
Directory	/workspace/22.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/23.keymgr_dpe_alert_test.354393813
Short name	T152
Test name
Test status
Simulation time	10656296 ps
CPU time	0.72 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:39 PM PDT 24
Peak memory	205356 kb
Host	smart-d2ba5239-f02d-4b82-a764-25079dec0ef4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354393813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.354393813
Directory	/workspace/23.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/24.keymgr_dpe_alert_test.3859812900
Short name	T15
Test name
Test status
Simulation time	135735729 ps
CPU time	0.91 seconds
Started	May 11 01:38:37 PM PDT 24
Finished	May 11 01:38:39 PM PDT 24
Peak memory	205588 kb
Host	smart-c9e304b3-138b-4f2b-a17c-370cb6db2bce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859812900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test. 3859812900
Directory	/workspace/24.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/25.keymgr_dpe_alert_test.3806099606
Short name	T24
Test name
Test status
Simulation time	33160365 ps
CPU time	0.72 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:39 PM PDT 24
Peak memory	205324 kb
Host	smart-780add34-1308-4ced-84ad-36e26946fa21
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806099606 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test. 3806099606
Directory	/workspace/25.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/25.keymgr_dpe_smoke.4068970607
Short name	T104
Test name
Test status
Simulation time	672783450 ps
CPU time	21.44 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:39:00 PM PDT 24
Peak memory	208184 kb
Host	smart-a880c753-065b-42fa-ac57-aa57944957e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068970607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.4068970607
Directory	/workspace/25.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/26.keymgr_dpe_alert_test.1823239966
Short name	T74
Test name
Test status
Simulation time	20759701 ps
CPU time	1.04 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:39 PM PDT 24
Peak memory	205548 kb
Host	smart-bfe2b9e2-9b71-4b31-9f5d-027410903fce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823239966 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test. 1823239966
Directory	/workspace/26.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/26.keymgr_dpe_smoke.7970953
Short name	T28
Test name
Test status
Simulation time	936167472 ps
CPU time	13.06 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:52 PM PDT 24
Peak memory	208188 kb
Host	smart-7d00c66a-e26d-4c5a-804a-6b592a7985f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7970953 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.7970953
Directory	/workspace/26.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/27.keymgr_dpe_alert_test.87534780
Short name	T115
Test name
Test status
Simulation time	45671191 ps
CPU time	0.9 seconds
Started	May 11 01:38:42 PM PDT 24
Finished	May 11 01:38:43 PM PDT 24
Peak memory	205316 kb
Host	smart-94ff0284-1f24-4bcb-bc97-f7a9479b3f94
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87534780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.87534780
Directory	/workspace/27.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/27.keymgr_dpe_smoke.432981888
Short name	T99
Test name
Test status
Simulation time	47380632395 ps
CPU time	196.51 seconds
Started	May 11 01:38:40 PM PDT 24
Finished	May 11 01:41:56 PM PDT 24
Peak memory	207884 kb
Host	smart-e2bcc1e4-b03e-4e6d-afdf-4232eb323872
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432981888 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.432981888
Directory	/workspace/27.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/28.keymgr_dpe_alert_test.1010729840
Short name	T111
Test name
Test status
Simulation time	39156658 ps
CPU time	0.83 seconds
Started	May 11 01:38:42 PM PDT 24
Finished	May 11 01:38:43 PM PDT 24
Peak memory	205396 kb
Host	smart-2778649f-e808-40e0-8895-c0e05adef73f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010729840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test. 1010729840
Directory	/workspace/28.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/28.keymgr_dpe_smoke.263610298
Short name	T149
Test name
Test status
Simulation time	939074270 ps
CPU time	25.29 seconds
Started	May 11 01:38:43 PM PDT 24
Finished	May 11 01:39:08 PM PDT 24
Peak memory	208192 kb
Host	smart-93513ab7-b690-4a82-bedb-8ca8a0ac4e78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=263610298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.263610298
Directory	/workspace/28.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/29.keymgr_dpe_alert_test.454422174
Short name	T159
Test name
Test status
Simulation time	17561659 ps
CPU time	0.76 seconds
Started	May 11 01:38:41 PM PDT 24
Finished	May 11 01:38:42 PM PDT 24
Peak memory	205396 kb
Host	smart-b146838b-066d-4347-b2a0-fe541c19d808
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454422174 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.454422174
Directory	/workspace/29.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/3.keymgr_dpe_alert_test.1370893370
Short name	T71
Test name
Test status
Simulation time	12885169 ps
CPU time	0.79 seconds
Started	May 11 01:38:34 PM PDT 24
Finished	May 11 01:38:35 PM PDT 24
Peak memory	205408 kb
Host	smart-f7bcd495-3b0d-4ae2-8fa0-41d71315a259
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370893370 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.1 370893370
Directory	/workspace/3.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/3.keymgr_dpe_sec_cm.501153099
Short name	T22
Test name
Test status
Simulation time	2051983531 ps
CPU time	16.31 seconds
Started	May 11 01:38:29 PM PDT 24
Finished	May 11 01:38:46 PM PDT 24
Peak memory	233944 kb
Host	smart-0466953d-a90e-4433-8c48-657494ab9652
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501153099 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.501153099
Directory	/workspace/3.keymgr_dpe_sec_cm/latest

Test location	/workspace/coverage/default/3.keymgr_dpe_smoke.1442410202
Short name	T121
Test name
Test status
Simulation time	2708437617 ps
CPU time	22.42 seconds
Started	May 11 01:38:29 PM PDT 24
Finished	May 11 01:38:52 PM PDT 24
Peak memory	207512 kb
Host	smart-719da258-20f9-4b30-94e9-135fc4259848
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442410202 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.1442410202
Directory	/workspace/3.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/30.keymgr_dpe_alert_test.2280621707
Short name	T117
Test name
Test status
Simulation time	42380931 ps
CPU time	0.72 seconds
Started	May 11 01:38:39 PM PDT 24
Finished	May 11 01:38:40 PM PDT 24
Peak memory	205400 kb
Host	smart-e04dccac-2c71-449b-8111-ddb3c2c58c6f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280621707 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test. 2280621707
Directory	/workspace/30.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/31.keymgr_dpe_alert_test.922334656
Short name	T127
Test name
Test status
Simulation time	14211318 ps
CPU time	0.76 seconds
Started	May 11 01:38:39 PM PDT 24
Finished	May 11 01:38:41 PM PDT 24
Peak memory	205328 kb
Host	smart-d8290448-8980-4083-b901-75c315fae526
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922334656 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.922334656
Directory	/workspace/31.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/32.keymgr_dpe_alert_test.1398091439
Short name	T128
Test name
Test status
Simulation time	143607628 ps
CPU time	0.84 seconds
Started	May 11 01:38:39 PM PDT 24
Finished	May 11 01:38:40 PM PDT 24
Peak memory	205428 kb
Host	smart-059936a1-1c00-454f-a363-ac1e21f16fdf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398091439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test. 1398091439
Directory	/workspace/32.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/33.keymgr_dpe_alert_test.2444833450
Short name	T141
Test name
Test status
Simulation time	43798125 ps
CPU time	0.81 seconds
Started	May 11 01:38:42 PM PDT 24
Finished	May 11 01:38:43 PM PDT 24
Peak memory	205144 kb
Host	smart-0d81bdc5-7e67-4160-a7f8-baa8eb219c5b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444833450 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test. 2444833450
Directory	/workspace/33.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/34.keymgr_dpe_alert_test.3869526662
Short name	T158
Test name
Test status
Simulation time	100049763 ps
CPU time	0.78 seconds
Started	May 11 01:38:40 PM PDT 24
Finished	May 11 01:38:41 PM PDT 24
Peak memory	205336 kb
Host	smart-2d9c2209-ab97-46ff-bb22-a42b24daa290
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869526662 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test. 3869526662
Directory	/workspace/34.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/35.keymgr_dpe_alert_test.249161523
Short name	T131
Test name
Test status
Simulation time	41121992 ps
CPU time	0.8 seconds
Started	May 11 01:38:44 PM PDT 24
Finished	May 11 01:38:45 PM PDT 24
Peak memory	205416 kb
Host	smart-47e06dcf-4cfe-4fc2-b597-f000ef68ebd1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249161523 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.249161523
Directory	/workspace/35.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/35.keymgr_dpe_smoke.3799558361
Short name	T124
Test name
Test status
Simulation time	742451434 ps
CPU time	22.33 seconds
Started	May 11 01:38:40 PM PDT 24
Finished	May 11 01:39:03 PM PDT 24
Peak memory	206080 kb
Host	smart-4639c35a-9919-4f9d-bb4d-c6e956b6bcd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799558361 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.3799558361
Directory	/workspace/35.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/36.keymgr_dpe_alert_test.3024525468
Short name	T140
Test name
Test status
Simulation time	26582523 ps
CPU time	0.72 seconds
Started	May 11 01:38:49 PM PDT 24
Finished	May 11 01:38:50 PM PDT 24
Peak memory	205408 kb
Host	smart-116e6e94-455a-4ba8-9c78-985c3cd7043e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024525468 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test. 3024525468
Directory	/workspace/36.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/36.keymgr_dpe_smoke.1636562879
Short name	T105
Test name
Test status
Simulation time	6712653546 ps
CPU time	38.2 seconds
Started	May 11 01:38:44 PM PDT 24
Finished	May 11 01:39:23 PM PDT 24
Peak memory	207656 kb
Host	smart-96fa0ded-4d5a-430e-94e0-45bf6081feda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636562879 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.1636562879
Directory	/workspace/36.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/37.keymgr_dpe_alert_test.2396091990
Short name	T122
Test name
Test status
Simulation time	15230949 ps
CPU time	0.9 seconds
Started	May 11 01:38:43 PM PDT 24
Finished	May 11 01:38:44 PM PDT 24
Peak memory	205504 kb
Host	smart-3f080c40-4573-4f7b-b41b-c62a90236f54
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396091990 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test. 2396091990
Directory	/workspace/37.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/37.keymgr_dpe_smoke.1034643098
Short name	T164
Test name
Test status
Simulation time	2006203117 ps
CPU time	29.44 seconds
Started	May 11 01:38:46 PM PDT 24
Finished	May 11 01:39:15 PM PDT 24
Peak memory	207516 kb
Host	smart-49ab5786-fcaf-4607-acea-cd31e515c538
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1034643098 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.1034643098
Directory	/workspace/37.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/38.keymgr_dpe_alert_test.1078039201
Short name	T70
Test name
Test status
Simulation time	45167330 ps
CPU time	0.81 seconds
Started	May 11 01:38:46 PM PDT 24
Finished	May 11 01:38:47 PM PDT 24
Peak memory	205312 kb
Host	smart-cebd1155-99f4-495a-9778-803c623f8172
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078039201 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test. 1078039201
Directory	/workspace/38.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/39.keymgr_dpe_alert_test.2453996199
Short name	T146
Test name
Test status
Simulation time	102214049 ps
CPU time	0.7 seconds
Started	May 11 01:38:54 PM PDT 24
Finished	May 11 01:38:56 PM PDT 24
Peak memory	205416 kb
Host	smart-aace0072-1195-469c-ad0d-d3e6b6b52b6b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453996199 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test. 2453996199
Directory	/workspace/39.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/39.keymgr_dpe_smoke.27487110
Short name	T9
Test name
Test status
Simulation time	155587346 ps
CPU time	9.8 seconds
Started	May 11 01:38:46 PM PDT 24
Finished	May 11 01:38:56 PM PDT 24
Peak memory	206264 kb
Host	smart-f41a14c1-72c1-48a6-8fef-1e6eed371ff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27487110 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.27487110
Directory	/workspace/39.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/4.keymgr_dpe_alert_test.395972240
Short name	T120
Test name
Test status
Simulation time	33312014 ps
CPU time	0.82 seconds
Started	May 11 01:38:32 PM PDT 24
Finished	May 11 01:38:33 PM PDT 24
Peak memory	205424 kb
Host	smart-933c41c4-dfbc-4802-9068-fd05ae4708ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395972240 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.395972240
Directory	/workspace/4.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/4.keymgr_dpe_sec_cm.2338170176
Short name	T5
Test name
Test status
Simulation time	2477481878 ps
CPU time	7.29 seconds
Started	May 11 01:38:34 PM PDT 24
Finished	May 11 01:38:41 PM PDT 24
Peak memory	230188 kb
Host	smart-4b56f445-7c86-411a-9f6c-21aeb92e49c0
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338170176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.2338170176
Directory	/workspace/4.keymgr_dpe_sec_cm/latest

Test location	/workspace/coverage/default/40.keymgr_dpe_alert_test.1142881173
Short name	T23
Test name
Test status
Simulation time	31077818 ps
CPU time	0.75 seconds
Started	May 11 01:38:44 PM PDT 24
Finished	May 11 01:38:45 PM PDT 24
Peak memory	205332 kb
Host	smart-2d078629-c117-4397-8f74-41fc41315a2d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142881173 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test. 1142881173
Directory	/workspace/40.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/40.keymgr_dpe_smoke.1247084717
Short name	T135
Test name
Test status
Simulation time	2208579980 ps
CPU time	18.32 seconds
Started	May 11 01:38:45 PM PDT 24
Finished	May 11 01:39:03 PM PDT 24
Peak memory	207796 kb
Host	smart-db97654f-c1cf-4106-8311-7c277b9d51a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1247084717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.1247084717
Directory	/workspace/40.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/41.keymgr_dpe_alert_test.215959583
Short name	T144
Test name
Test status
Simulation time	40072896 ps
CPU time	0.81 seconds
Started	May 11 01:38:42 PM PDT 24
Finished	May 11 01:38:43 PM PDT 24
Peak memory	205404 kb
Host	smart-bcd1c11d-22cb-4393-b200-5cc19e8f40fc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215959583 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.215959583
Directory	/workspace/41.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/41.keymgr_dpe_smoke.201864504
Short name	T134
Test name
Test status
Simulation time	1012999731 ps
CPU time	14.34 seconds
Started	May 11 01:38:45 PM PDT 24
Finished	May 11 01:39:00 PM PDT 24
Peak memory	206652 kb
Host	smart-bad57913-e898-4ba2-bcbe-ff404a6c928c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=201864504 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.201864504
Directory	/workspace/41.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/42.keymgr_dpe_alert_test.1529011875
Short name	T142
Test name
Test status
Simulation time	170835554 ps
CPU time	0.74 seconds
Started	May 11 01:38:49 PM PDT 24
Finished	May 11 01:38:50 PM PDT 24
Peak memory	205324 kb
Host	smart-c983bf93-8e89-4fd5-8462-4a1614abe9a4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529011875 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test. 1529011875
Directory	/workspace/42.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/43.keymgr_dpe_alert_test.1282852097
Short name	T110
Test name
Test status
Simulation time	24963356 ps
CPU time	0.96 seconds
Started	May 11 01:38:47 PM PDT 24
Finished	May 11 01:38:48 PM PDT 24
Peak memory	205520 kb
Host	smart-cb7a00ee-9c1f-474e-a3ae-6e5804aaa1a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282852097 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test. 1282852097
Directory	/workspace/43.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/44.keymgr_dpe_alert_test.2398205763
Short name	T137
Test name
Test status
Simulation time	45058720 ps
CPU time	0.76 seconds
Started	May 11 01:38:48 PM PDT 24
Finished	May 11 01:38:48 PM PDT 24
Peak memory	205428 kb
Host	smart-5bc70600-f8a2-4b1b-a622-483698558650
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398205763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test. 2398205763
Directory	/workspace/44.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/44.keymgr_dpe_smoke.3143568593
Short name	T156
Test name
Test status
Simulation time	2710773292 ps
CPU time	23.23 seconds
Started	May 11 01:38:48 PM PDT 24
Finished	May 11 01:39:11 PM PDT 24
Peak memory	207680 kb
Host	smart-a7ce9ef5-1d99-448d-a567-7649d9a62dab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143568593 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.3143568593
Directory	/workspace/44.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/45.keymgr_dpe_alert_test.1426388808
Short name	T153
Test name
Test status
Simulation time	14572620 ps
CPU time	0.73 seconds
Started	May 11 01:38:49 PM PDT 24
Finished	May 11 01:38:50 PM PDT 24
Peak memory	205396 kb
Host	smart-be920a51-ff93-4e4c-ab62-f817b967eb0f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426388808 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test. 1426388808
Directory	/workspace/45.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/45.keymgr_dpe_smoke.1948183533
Short name	T27
Test name
Test status
Simulation time	53860051697 ps
CPU time	207.65 seconds
Started	May 11 01:38:47 PM PDT 24
Finished	May 11 01:42:15 PM PDT 24
Peak memory	208420 kb
Host	smart-59f71f53-f6d7-4bc8-ad87-86c193b021c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948183533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.1948183533
Directory	/workspace/45.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/46.keymgr_dpe_alert_test.1389507413
Short name	T16
Test name
Test status
Simulation time	41386075 ps
CPU time	0.75 seconds
Started	May 11 01:38:50 PM PDT 24
Finished	May 11 01:38:51 PM PDT 24
Peak memory	205408 kb
Host	smart-b58c731e-73f9-4a20-abe0-5612e3e46d19
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389507413 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test. 1389507413
Directory	/workspace/46.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/46.keymgr_dpe_smoke.832278883
Short name	T125
Test name
Test status
Simulation time	6844662659 ps
CPU time	18.74 seconds
Started	May 11 01:38:46 PM PDT 24
Finished	May 11 01:39:06 PM PDT 24
Peak memory	206732 kb
Host	smart-5067d1ba-71a9-411e-9374-9e9c2b0e6d17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832278883 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.832278883
Directory	/workspace/46.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/47.keymgr_dpe_alert_test.1022824064
Short name	T17
Test name
Test status
Simulation time	49122513 ps
CPU time	0.76 seconds
Started	May 11 01:38:47 PM PDT 24
Finished	May 11 01:38:48 PM PDT 24
Peak memory	205400 kb
Host	smart-7adee71d-b526-457b-a77f-887c8e47909d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022824064 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test. 1022824064
Directory	/workspace/47.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/47.keymgr_dpe_smoke.3003367152
Short name	T165
Test name
Test status
Simulation time	818192101 ps
CPU time	18.58 seconds
Started	May 11 01:38:50 PM PDT 24
Finished	May 11 01:39:09 PM PDT 24
Peak memory	208080 kb
Host	smart-3b99843c-99ad-4989-87d7-414f0b66550a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003367152 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3003367152
Directory	/workspace/47.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/48.keymgr_dpe_alert_test.978850876
Short name	T114
Test name
Test status
Simulation time	97195270 ps
CPU time	0.98 seconds
Started	May 11 01:38:46 PM PDT 24
Finished	May 11 01:38:48 PM PDT 24
Peak memory	205448 kb
Host	smart-5b0f0878-0427-4d09-8753-61eef6edae11
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978850876 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.978850876
Directory	/workspace/48.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/48.keymgr_dpe_smoke.1660920735
Short name	T29
Test name
Test status
Simulation time	2471792516 ps
CPU time	18.33 seconds
Started	May 11 01:38:46 PM PDT 24
Finished	May 11 01:39:05 PM PDT 24
Peak memory	208488 kb
Host	smart-cf40c502-6365-4b27-b0b1-b6704a25c654
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660920735 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.1660920735
Directory	/workspace/48.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/49.keymgr_dpe_alert_test.2138999652
Short name	T145
Test name
Test status
Simulation time	39292988 ps
CPU time	0.86 seconds
Started	May 11 01:38:47 PM PDT 24
Finished	May 11 01:38:48 PM PDT 24
Peak memory	205388 kb
Host	smart-bf1f2462-37b8-4ef9-a315-64601f3771b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138999652 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test. 2138999652
Directory	/workspace/49.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/49.keymgr_dpe_smoke.2334233319
Short name	T107
Test name
Test status
Simulation time	428650467 ps
CPU time	11.05 seconds
Started	May 11 01:38:50 PM PDT 24
Finished	May 11 01:39:01 PM PDT 24
Peak memory	206520 kb
Host	smart-822d7224-bf5e-4576-8777-4b75c5beb803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334233319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.2334233319
Directory	/workspace/49.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/5.keymgr_dpe_alert_test.837648717
Short name	T157
Test name
Test status
Simulation time	44658317 ps
CPU time	1.11 seconds
Started	May 11 01:38:37 PM PDT 24
Finished	May 11 01:38:39 PM PDT 24
Peak memory	205572 kb
Host	smart-bb3646de-8b97-4649-a21d-51d7909fdb09
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837648717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.837648717
Directory	/workspace/5.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/5.keymgr_dpe_smoke.3120362623
Short name	T155
Test name
Test status
Simulation time	23960933654 ps
CPU time	165.57 seconds
Started	May 11 01:38:27 PM PDT 24
Finished	May 11 01:41:13 PM PDT 24
Peak memory	207364 kb
Host	smart-6e7b3288-4eda-4c58-9ad6-2a5547288c96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120362623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.3120362623
Directory	/workspace/5.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/6.keymgr_dpe_alert_test.253637695
Short name	T69
Test name
Test status
Simulation time	49415769 ps
CPU time	0.75 seconds
Started	May 11 01:38:31 PM PDT 24
Finished	May 11 01:38:32 PM PDT 24
Peak memory	205304 kb
Host	smart-f56739da-7052-484d-bb87-700972eade22
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253637695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.253637695
Directory	/workspace/6.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/6.keymgr_dpe_smoke.1618550938
Short name	T160
Test name
Test status
Simulation time	8206643631 ps
CPU time	27.47 seconds
Started	May 11 01:38:29 PM PDT 24
Finished	May 11 01:38:57 PM PDT 24
Peak memory	207480 kb
Host	smart-e95eb709-be62-41f6-a0d8-6ea0cfefed75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618550938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.1618550938
Directory	/workspace/6.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/7.keymgr_dpe_alert_test.1982314462
Short name	T150
Test name
Test status
Simulation time	19386639 ps
CPU time	0.82 seconds
Started	May 11 01:38:35 PM PDT 24
Finished	May 11 01:38:36 PM PDT 24
Peak memory	205352 kb
Host	smart-4f6676ba-ed1b-43f0-ae33-36eec2e6a576
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982314462 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.1 982314462
Directory	/workspace/7.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/7.keymgr_dpe_smoke.1148989217
Short name	T2
Test name
Test status
Simulation time	2745464669 ps
CPU time	46.85 seconds
Started	May 11 01:38:35 PM PDT 24
Finished	May 11 01:39:22 PM PDT 24
Peak memory	207696 kb
Host	smart-f6ca25d8-e75a-4e38-88fa-1dc5ddd3e0a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148989217 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.1148989217
Directory	/workspace/7.keymgr_dpe_smoke/latest

Test location	/workspace/coverage/default/8.keymgr_dpe_alert_test.2290411497
Short name	T147
Test name
Test status
Simulation time	77986061 ps
CPU time	0.86 seconds
Started	May 11 01:38:30 PM PDT 24
Finished	May 11 01:38:32 PM PDT 24
Peak memory	205224 kb
Host	smart-2abffbfa-bdc9-4b0c-be4c-0719eb47b5ed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290411497 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.2 290411497
Directory	/workspace/8.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/9.keymgr_dpe_alert_test.4025391299
Short name	T119
Test name
Test status
Simulation time	9046814 ps
CPU time	0.81 seconds
Started	May 11 01:38:38 PM PDT 24
Finished	May 11 01:38:39 PM PDT 24
Peak memory	205360 kb
Host	smart-e84af499-b003-4886-a415-5b37b002ba5c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025391299 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.4 025391299
Directory	/workspace/9.keymgr_dpe_alert_test/latest

Test location	/workspace/coverage/default/9.keymgr_dpe_smoke.1170104007
Short name	T8
Test name
Test status
Simulation time	4199613312 ps
CPU time	35.9 seconds
Started	May 11 01:38:31 PM PDT 24
Finished	May 11 01:39:08 PM PDT 24
Peak memory	208256 kb
Host	smart-01dae6c1-b50c-4bd7-8b28-665941a2f37d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170104007 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.1170104007
Directory	/workspace/9.keymgr_dpe_smoke/latest