Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.26 97.60 90.64 57.52 76.92 94.97 98.34 17.82


Total test records in report: 309
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T256 /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.768859522 May 18 01:45:04 PM PDT 24 May 18 01:45:06 PM PDT 24 16051918 ps
T257 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2951140283 May 18 01:45:16 PM PDT 24 May 18 01:45:21 PM PDT 24 92989834 ps
T258 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.2474156736 May 18 01:45:17 PM PDT 24 May 18 01:45:21 PM PDT 24 31668212 ps
T259 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.2440793474 May 18 01:45:21 PM PDT 24 May 18 01:45:27 PM PDT 24 360090614 ps
T260 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1844945137 May 18 01:44:39 PM PDT 24 May 18 01:44:48 PM PDT 24 175141620 ps
T261 /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.2641469695 May 18 01:45:30 PM PDT 24 May 18 01:45:34 PM PDT 24 30194552 ps
T262 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.3493510735 May 18 01:45:06 PM PDT 24 May 18 01:45:09 PM PDT 24 12820662 ps
T263 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.4019702394 May 18 01:45:13 PM PDT 24 May 18 01:45:18 PM PDT 24 588250710 ps
T264 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.2128653065 May 18 01:45:32 PM PDT 24 May 18 01:45:37 PM PDT 24 162730761 ps
T265 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.4060096643 May 18 01:44:42 PM PDT 24 May 18 01:44:43 PM PDT 24 48822909 ps
T266 /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.3963937726 May 18 01:45:21 PM PDT 24 May 18 01:45:25 PM PDT 24 133644755 ps
T267 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.2251297651 May 18 01:45:07 PM PDT 24 May 18 01:45:11 PM PDT 24 145126833 ps
T268 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2125885748 May 18 01:45:23 PM PDT 24 May 18 01:45:28 PM PDT 24 183623548 ps
T269 /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3842689765 May 18 01:45:30 PM PDT 24 May 18 01:45:33 PM PDT 24 25170196 ps
T270 /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.2193700314 May 18 01:44:34 PM PDT 24 May 18 01:44:37 PM PDT 24 74666974 ps
T271 /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.889793439 May 18 01:45:29 PM PDT 24 May 18 01:45:33 PM PDT 24 9362698 ps
T272 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1420733667 May 18 01:45:23 PM PDT 24 May 18 01:45:28 PM PDT 24 107918983 ps
T273 /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.4261345207 May 18 01:45:18 PM PDT 24 May 18 01:45:21 PM PDT 24 90421163 ps
T274 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.556558799 May 18 01:45:05 PM PDT 24 May 18 01:45:09 PM PDT 24 43950403 ps
T275 /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.874777300 May 18 01:45:18 PM PDT 24 May 18 01:45:22 PM PDT 24 30556511 ps
T276 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3430617215 May 18 01:45:20 PM PDT 24 May 18 01:45:30 PM PDT 24 898838959 ps
T277 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.1254382200 May 18 01:45:06 PM PDT 24 May 18 01:45:09 PM PDT 24 33979577 ps
T52 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.2841891814 May 18 01:45:24 PM PDT 24 May 18 01:45:30 PM PDT 24 170679360 ps
T278 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.495924819 May 18 01:44:34 PM PDT 24 May 18 01:44:37 PM PDT 24 21005406 ps
T279 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.2654632379 May 18 01:44:41 PM PDT 24 May 18 01:44:43 PM PDT 24 51101757 ps
T280 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.3034830490 May 18 01:45:06 PM PDT 24 May 18 01:45:10 PM PDT 24 190791669 ps
T281 /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.146395062 May 18 01:45:22 PM PDT 24 May 18 01:45:26 PM PDT 24 36786012 ps
T282 /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.2714546539 May 18 01:45:23 PM PDT 24 May 18 01:45:28 PM PDT 24 82201319 ps
T48 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.1736546144 May 18 01:45:14 PM PDT 24 May 18 01:45:22 PM PDT 24 177407923 ps
T283 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.2343102956 May 18 01:44:47 PM PDT 24 May 18 01:44:54 PM PDT 24 242986230 ps
T284 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1583791788 May 18 01:45:14 PM PDT 24 May 18 01:45:17 PM PDT 24 35692765 ps
T285 /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.1571481297 May 18 01:45:33 PM PDT 24 May 18 01:45:37 PM PDT 24 10431811 ps
T286 /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.2741138792 May 18 01:45:31 PM PDT 24 May 18 01:45:36 PM PDT 24 91707537 ps
T55 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.2253061979 May 18 01:45:16 PM PDT 24 May 18 01:45:23 PM PDT 24 91337586 ps
T287 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.771485671 May 18 01:44:49 PM PDT 24 May 18 01:44:54 PM PDT 24 321028775 ps
T288 /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.1475710978 May 18 01:45:17 PM PDT 24 May 18 01:45:21 PM PDT 24 11233516 ps
T289 /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3197915464 May 18 01:45:30 PM PDT 24 May 18 01:45:34 PM PDT 24 8462156 ps
T56 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3622467364 May 18 01:45:00 PM PDT 24 May 18 01:45:04 PM PDT 24 167919816 ps
T290 /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.360706089 May 18 01:45:30 PM PDT 24 May 18 01:45:34 PM PDT 24 11989402 ps
T291 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.3129159223 May 18 01:44:43 PM PDT 24 May 18 01:44:49 PM PDT 24 108211684 ps
T292 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.3692957413 May 18 01:44:48 PM PDT 24 May 18 01:44:50 PM PDT 24 33884138 ps
T293 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.577707587 May 18 01:44:49 PM PDT 24 May 18 01:44:52 PM PDT 24 88792671 ps
T294 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.660308559 May 18 01:44:58 PM PDT 24 May 18 01:45:01 PM PDT 24 275162646 ps
T295 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.1557748176 May 18 01:45:22 PM PDT 24 May 18 01:45:29 PM PDT 24 106092665 ps
T296 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.1967369879 May 18 01:44:48 PM PDT 24 May 18 01:44:50 PM PDT 24 123633303 ps
T297 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.2207480854 May 18 01:44:49 PM PDT 24 May 18 01:44:53 PM PDT 24 20573355 ps
T298 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.3188669798 May 18 01:44:57 PM PDT 24 May 18 01:45:01 PM PDT 24 291709948 ps
T51 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.4032624634 May 18 01:44:58 PM PDT 24 May 18 01:45:04 PM PDT 24 326536358 ps
T299 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.3801733785 May 18 01:45:18 PM PDT 24 May 18 01:45:23 PM PDT 24 34590948 ps
T300 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.200649054 May 18 01:45:29 PM PDT 24 May 18 01:45:32 PM PDT 24 15642282 ps
T301 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.987855717 May 18 01:45:14 PM PDT 24 May 18 01:45:17 PM PDT 24 53721088 ps
T302 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.2873194538 May 18 01:44:49 PM PDT 24 May 18 01:44:56 PM PDT 24 309286334 ps
T303 /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.1305495606 May 18 01:45:16 PM PDT 24 May 18 01:45:21 PM PDT 24 390045847 ps
T304 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.1626700310 May 18 01:45:23 PM PDT 24 May 18 01:45:31 PM PDT 24 283297835 ps
T305 /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.1833190870 May 18 01:45:29 PM PDT 24 May 18 01:45:32 PM PDT 24 12186144 ps
T306 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1437134683 May 18 01:45:14 PM PDT 24 May 18 01:45:23 PM PDT 24 3281328567 ps
T307 /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.1545951982 May 18 01:44:57 PM PDT 24 May 18 01:44:59 PM PDT 24 7705289 ps
T308 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.4232416463 May 18 01:45:24 PM PDT 24 May 18 01:45:28 PM PDT 24 37458273 ps
T309 /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1671917562 May 18 01:45:22 PM PDT 24 May 18 01:45:26 PM PDT 24 31969322 ps

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.4038666386
Short name T3
Test name
Test status
Simulation time 1367762162 ps
CPU time 10.05 seconds
Started May 18 01:44:16 PM PDT 24
Finished May 18 01:44:29 PM PDT 24
Peak memory 206420 kb
Host smart-6a51f0a0-3699-4201-863d-784fd068f773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038666386 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.4038666386
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.3400158479
Short name T6
Test name
Test status
Simulation time 550783904 ps
CPU time 14.15 seconds
Started May 18 01:44:08 PM PDT 24
Finished May 18 01:44:24 PM PDT 24
Peak memory 229176 kb
Host smart-9145a841-86ad-4745-a5b2-e1630cca5974
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400158479 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.3400158479
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.1731254715
Short name T19
Test name
Test status
Simulation time 241821580 ps
CPU time 8.88 seconds
Started May 18 01:45:07 PM PDT 24
Finished May 18 01:45:18 PM PDT 24
Peak memory 213904 kb
Host smart-478c1d33-27ed-482e-9044-d901b11ae82d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731254715 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.1731254715
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.1223030405
Short name T35
Test name
Test status
Simulation time 124045277 ps
CPU time 4.77 seconds
Started May 18 01:45:14 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 220940 kb
Host smart-35a7dc8b-ea34-40a5-a8bc-729726531a54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223030405 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
1223030405
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3459099210
Short name T33
Test name
Test status
Simulation time 55006902 ps
CPU time 2.65 seconds
Started May 18 01:44:41 PM PDT 24
Finished May 18 01:44:45 PM PDT 24
Peak memory 213052 kb
Host smart-0e46007f-4aa5-40f5-b293-d7efea82754f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459099210 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3459099210
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.397774325
Short name T9
Test name
Test status
Simulation time 1285414913 ps
CPU time 30.97 seconds
Started May 18 01:44:15 PM PDT 24
Finished May 18 01:44:49 PM PDT 24
Peak memory 208460 kb
Host smart-5d89f6a7-3346-48a1-9ed2-4018f016f64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397774325 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.397774325
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.251357170
Short name T86
Test name
Test status
Simulation time 39065169 ps
CPU time 0.73 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:26 PM PDT 24
Peak memory 204372 kb
Host smart-367591bc-af07-4f0b-ac1b-c3c0f05c82a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251357170 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.251357170
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.2752788706
Short name T24
Test name
Test status
Simulation time 34367409 ps
CPU time 0.83 seconds
Started May 18 01:44:17 PM PDT 24
Finished May 18 01:44:22 PM PDT 24
Peak memory 205508 kb
Host smart-7604774a-c085-4ee6-8843-c81a440294c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752788706 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
2752788706
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.27781629
Short name T40
Test name
Test status
Simulation time 590391142 ps
CPU time 5.32 seconds
Started May 18 01:45:15 PM PDT 24
Finished May 18 01:45:23 PM PDT 24
Peak memory 214816 kb
Host smart-250ba526-b898-4f3b-a46a-e8252794e8e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27781629 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.27781629
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.3357751626
Short name T184
Test name
Test status
Simulation time 295621714 ps
CPU time 5.92 seconds
Started May 18 01:44:33 PM PDT 24
Finished May 18 01:44:41 PM PDT 24
Peak memory 213040 kb
Host smart-5460e1a5-2977-4fc3-a643-df85edaf12f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357751626 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.3357751626
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.2951970285
Short name T97
Test name
Test status
Simulation time 469076191 ps
CPU time 13.42 seconds
Started May 18 01:44:15 PM PDT 24
Finished May 18 01:44:32 PM PDT 24
Peak memory 208164 kb
Host smart-c999e70e-459c-48cd-92c9-9d5e658d2119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951970285 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.2951970285
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.1736546144
Short name T48
Test name
Test status
Simulation time 177407923 ps
CPU time 6.43 seconds
Started May 18 01:45:14 PM PDT 24
Finished May 18 01:45:22 PM PDT 24
Peak memory 214064 kb
Host smart-7401d1fd-3af4-4cb1-87c6-447ff40067a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736546144 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.1736546144
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.2841891814
Short name T52
Test name
Test status
Simulation time 170679360 ps
CPU time 3.89 seconds
Started May 18 01:45:24 PM PDT 24
Finished May 18 01:45:30 PM PDT 24
Peak memory 213948 kb
Host smart-c619b8e1-2d78-496b-bdbf-045b0d788232
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841891814 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.2841891814
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.2825080093
Short name T209
Test name
Test status
Simulation time 431047354 ps
CPU time 2.96 seconds
Started May 18 01:44:34 PM PDT 24
Finished May 18 01:44:39 PM PDT 24
Peak memory 212664 kb
Host smart-2311f144-5a57-46e5-a977-7939c7509a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825080093 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.2
825080093
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.2543397821
Short name T46
Test name
Test status
Simulation time 144068124 ps
CPU time 4.62 seconds
Started May 18 01:45:22 PM PDT 24
Finished May 18 01:45:30 PM PDT 24
Peak memory 213020 kb
Host smart-60694283-694e-411c-a4d6-0aa275049e55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543397821 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.2543397821
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.1263990971
Short name T5
Test name
Test status
Simulation time 1625544033 ps
CPU time 6.86 seconds
Started May 18 01:43:59 PM PDT 24
Finished May 18 01:44:08 PM PDT 24
Peak memory 229584 kb
Host smart-4e57db17-325b-47f8-9cde-b39dc6aa283d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263990971 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.1263990971
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.4032624634
Short name T51
Test name
Test status
Simulation time 326536358 ps
CPU time 4.39 seconds
Started May 18 01:44:58 PM PDT 24
Finished May 18 01:45:04 PM PDT 24
Peak memory 212732 kb
Host smart-4ffb0ec1-eaca-4161-82d8-eff601279d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032624634 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.4032624634
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.3001751341
Short name T95
Test name
Test status
Simulation time 1124641693 ps
CPU time 20.8 seconds
Started May 18 01:44:24 PM PDT 24
Finished May 18 01:44:46 PM PDT 24
Peak memory 208176 kb
Host smart-1d67adfb-2f56-4330-8ca7-d1db5e1aae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001751341 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3001751341
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.800732715
Short name T18
Test name
Test status
Simulation time 43743164 ps
CPU time 1.04 seconds
Started May 18 01:44:38 PM PDT 24
Finished May 18 01:44:40 PM PDT 24
Peak memory 204436 kb
Host smart-f339b9a1-1937-434b-8132-f90f17ae49b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800732715 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.800732715
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3897572938
Short name T37
Test name
Test status
Simulation time 167310815 ps
CPU time 4.93 seconds
Started May 18 01:44:33 PM PDT 24
Finished May 18 01:44:40 PM PDT 24
Peak memory 212704 kb
Host smart-693f96f3-6887-45f1-a78a-1a5cc7c7004c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897572938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.3897572938
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.3148594391
Short name T171
Test name
Test status
Simulation time 11794406 ps
CPU time 0.81 seconds
Started May 18 01:44:40 PM PDT 24
Finished May 18 01:44:42 PM PDT 24
Peak memory 204280 kb
Host smart-83807cae-f29a-4c6a-b0e7-00b7a977682e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148594391 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.3
148594391
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.777305481
Short name T101
Test name
Test status
Simulation time 1535689045 ps
CPU time 23.66 seconds
Started May 18 01:44:00 PM PDT 24
Finished May 18 01:44:26 PM PDT 24
Peak memory 208032 kb
Host smart-3787258c-a619-4f47-a736-c58c06fe6046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777305481 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.777305481
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.1165585691
Short name T91
Test name
Test status
Simulation time 3803143930 ps
CPU time 18.76 seconds
Started May 18 01:44:18 PM PDT 24
Finished May 18 01:44:40 PM PDT 24
Peak memory 206508 kb
Host smart-cf52a05e-fc85-4bae-865a-16895ce4abe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165585691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.1165585691
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.1050839456
Short name T4
Test name
Test status
Simulation time 1385710047 ps
CPU time 34.98 seconds
Started May 18 01:43:59 PM PDT 24
Finished May 18 01:44:35 PM PDT 24
Peak memory 207772 kb
Host smart-c63968ba-efd1-4eff-a098-f6cc0e66dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050839456 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.1050839456
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.2170070252
Short name T94
Test name
Test status
Simulation time 1043257109 ps
CPU time 20.05 seconds
Started May 18 01:44:23 PM PDT 24
Finished May 18 01:44:44 PM PDT 24
Peak memory 207492 kb
Host smart-8bebacfd-1bd0-4ec7-9641-2613c58d5d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170070252 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.2170070252
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.1291713062
Short name T93
Test name
Test status
Simulation time 415469177 ps
CPU time 15.91 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:44 PM PDT 24
Peak memory 207616 kb
Host smart-255fdaf1-7f06-40a6-b4e7-8a48929887ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291713062 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.1291713062
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.1544882468
Short name T68
Test name
Test status
Simulation time 12426583487 ps
CPU time 35.16 seconds
Started May 18 01:44:27 PM PDT 24
Finished May 18 01:45:05 PM PDT 24
Peak memory 207500 kb
Host smart-e66b8082-5ed0-4b14-a059-a1d28e03c7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544882468 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.1544882468
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.1130331409
Short name T92
Test name
Test status
Simulation time 2371995905 ps
CPU time 19.63 seconds
Started May 18 01:44:10 PM PDT 24
Finished May 18 01:44:32 PM PDT 24
Peak memory 206336 kb
Host smart-01f224c4-22dd-474c-af1b-abb5846bacfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130331409 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.1130331409
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.2819822098
Short name T90
Test name
Test status
Simulation time 11866676100 ps
CPU time 147.47 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:46:56 PM PDT 24
Peak memory 208560 kb
Host smart-046dc6d6-ff89-430a-af26-912d077c29e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819822098 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.2819822098
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.1838575363
Short name T89
Test name
Test status
Simulation time 7778626748 ps
CPU time 36.14 seconds
Started May 18 01:44:25 PM PDT 24
Finished May 18 01:45:03 PM PDT 24
Peak memory 207548 kb
Host smart-8be9ed68-c458-403c-be59-01657ed8c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838575363 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.1838575363
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.212651766
Short name T10
Test name
Test status
Simulation time 2215052900 ps
CPU time 18 seconds
Started May 18 01:44:24 PM PDT 24
Finished May 18 01:44:43 PM PDT 24
Peak memory 207676 kb
Host smart-1c2a1703-3157-4505-b039-208790cd0655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212651766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.212651766
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.1087467116
Short name T14
Test name
Test status
Simulation time 347604407 ps
CPU time 9.01 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:37 PM PDT 24
Peak memory 208384 kb
Host smart-201437d9-444e-406b-b126-a3dd09da9466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087467116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.1087467116
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.3069648416
Short name T74
Test name
Test status
Simulation time 6144126463 ps
CPU time 26.12 seconds
Started May 18 01:44:32 PM PDT 24
Finished May 18 01:45:00 PM PDT 24
Peak memory 208248 kb
Host smart-16c9acbe-0ce0-4126-8fd7-babc19c31389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069648416 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.3069648416
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.960903234
Short name T34
Test name
Test status
Simulation time 4024792469 ps
CPU time 31.24 seconds
Started May 18 01:44:35 PM PDT 24
Finished May 18 01:45:08 PM PDT 24
Peak memory 207696 kb
Host smart-2a949a1e-2b88-493d-a0dc-4e9b706d48db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960903234 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.960903234
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.1194866023
Short name T77
Test name
Test status
Simulation time 897350064 ps
CPU time 17.35 seconds
Started May 18 01:44:34 PM PDT 24
Finished May 18 01:44:53 PM PDT 24
Peak memory 207340 kb
Host smart-421ba78b-738f-4415-ab46-523930a1c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194866023 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.1194866023
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.3137954018
Short name T96
Test name
Test status
Simulation time 2965432272 ps
CPU time 29.14 seconds
Started May 18 01:44:08 PM PDT 24
Finished May 18 01:44:38 PM PDT 24
Peak memory 207996 kb
Host smart-764fe60a-876b-4b5d-893a-e1d2b097a1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137954018 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.3137954018
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.2161092390
Short name T83
Test name
Test status
Simulation time 708314764 ps
CPU time 6.13 seconds
Started May 18 01:44:40 PM PDT 24
Finished May 18 01:44:47 PM PDT 24
Peak memory 204456 kb
Host smart-ca673d66-26a2-47f6-8bff-e9f265467812
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161092390 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.2161092390
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.2910404568
Short name T192
Test name
Test status
Simulation time 290587417 ps
CPU time 8.81 seconds
Started May 18 01:44:41 PM PDT 24
Finished May 18 01:44:51 PM PDT 24
Peak memory 204564 kb
Host smart-8098690d-1b97-4bf0-9c8b-c3c45e0a9461
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910404568 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.2910404568
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.190180724
Short name T232
Test name
Test status
Simulation time 42066303 ps
CPU time 0.96 seconds
Started May 18 01:44:34 PM PDT 24
Finished May 18 01:44:37 PM PDT 24
Peak memory 204452 kb
Host smart-bfb47dd1-5b1b-48e6-8eeb-3f4895d7f575
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190180724 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_hw_reset.190180724
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.495924819
Short name T278
Test name
Test status
Simulation time 21005406 ps
CPU time 0.91 seconds
Started May 18 01:44:34 PM PDT 24
Finished May 18 01:44:37 PM PDT 24
Peak memory 204260 kb
Host smart-656d774f-14d8-406d-abe6-082da601428a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495924819 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.495924819
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.1485427705
Short name T207
Test name
Test status
Simulation time 45793002 ps
CPU time 0.85 seconds
Started May 18 01:44:33 PM PDT 24
Finished May 18 01:44:36 PM PDT 24
Peak memory 204344 kb
Host smart-8f654ebb-b5e3-440c-a977-9e170f49ea79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485427705 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.1
485427705
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.1518043452
Short name T87
Test name
Test status
Simulation time 153842223 ps
CPU time 1.71 seconds
Started May 18 01:44:39 PM PDT 24
Finished May 18 01:44:42 PM PDT 24
Peak memory 204548 kb
Host smart-4d0bd991-719e-435b-ad6d-00497dcbf091
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518043452 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.1518043452
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.2193700314
Short name T270
Test name
Test status
Simulation time 74666974 ps
CPU time 1.81 seconds
Started May 18 01:44:34 PM PDT 24
Finished May 18 01:44:37 PM PDT 24
Peak memory 213108 kb
Host smart-1e58e40b-7704-4630-abd8-1b4c372b0c49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193700314 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.2193700314
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.1205982676
Short name T241
Test name
Test status
Simulation time 609628057 ps
CPU time 5.08 seconds
Started May 18 01:44:41 PM PDT 24
Finished May 18 01:44:47 PM PDT 24
Peak memory 204492 kb
Host smart-bc493e5d-2e26-4bbb-9aef-c9aa6a4f0b20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205982676 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.1205982676
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1844945137
Short name T260
Test name
Test status
Simulation time 175141620 ps
CPU time 8.17 seconds
Started May 18 01:44:39 PM PDT 24
Finished May 18 01:44:48 PM PDT 24
Peak memory 204548 kb
Host smart-6b603dae-7417-4db0-87c9-06ee177ce487
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844945137 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.1844945137
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.2867069673
Short name T181
Test name
Test status
Simulation time 58354421 ps
CPU time 1.13 seconds
Started May 18 01:44:41 PM PDT 24
Finished May 18 01:44:43 PM PDT 24
Peak memory 204520 kb
Host smart-a00d9300-6a3a-4e44-8f41-c714bb83aa5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867069673 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.2867069673
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.2654632379
Short name T279
Test name
Test status
Simulation time 51101757 ps
CPU time 1.25 seconds
Started May 18 01:44:41 PM PDT 24
Finished May 18 01:44:43 PM PDT 24
Peak memory 212768 kb
Host smart-610452fd-1db9-4207-b58d-8f42a3c2676a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654632379 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.2654632379
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.4060096643
Short name T265
Test name
Test status
Simulation time 48822909 ps
CPU time 0.89 seconds
Started May 18 01:44:42 PM PDT 24
Finished May 18 01:44:43 PM PDT 24
Peak memory 204404 kb
Host smart-35c8f8d7-8933-4c39-b138-71754a0ad09b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060096643 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.4
060096643
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.3576703306
Short name T223
Test name
Test status
Simulation time 155323282 ps
CPU time 1.77 seconds
Started May 18 01:44:43 PM PDT 24
Finished May 18 01:44:46 PM PDT 24
Peak memory 204516 kb
Host smart-888b3ca4-cece-4345-ad2e-f9da5e1c0a4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576703306 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.3576703306
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.4041146027
Short name T204
Test name
Test status
Simulation time 343283057 ps
CPU time 1.98 seconds
Started May 18 01:44:38 PM PDT 24
Finished May 18 01:44:41 PM PDT 24
Peak memory 213052 kb
Host smart-cc882061-888a-491e-bbc0-af6250b3dd0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041146027 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.4041146027
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.890632439
Short name T175
Test name
Test status
Simulation time 20400993 ps
CPU time 1.62 seconds
Started May 18 01:44:40 PM PDT 24
Finished May 18 01:44:42 PM PDT 24
Peak memory 212760 kb
Host smart-ab5c07ce-dc69-4e7d-9a03-9292f70f9d75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890632439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.890632439
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.1293308770
Short name T49
Test name
Test status
Simulation time 806369957 ps
CPU time 3.08 seconds
Started May 18 01:44:43 PM PDT 24
Finished May 18 01:44:48 PM PDT 24
Peak memory 212668 kb
Host smart-945aeeaa-e93c-40f8-8faa-cb9aa37e5dae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293308770 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.1293308770
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2951140283
Short name T257
Test name
Test status
Simulation time 92989834 ps
CPU time 1.18 seconds
Started May 18 01:45:16 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 204408 kb
Host smart-a8a99e06-23bc-4aab-9596-a7638a7947a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951140283 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.2951140283
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.699388322
Short name T222
Test name
Test status
Simulation time 31298958 ps
CPU time 0.82 seconds
Started May 18 01:45:20 PM PDT 24
Finished May 18 01:45:24 PM PDT 24
Peak memory 204316 kb
Host smart-cf8056ec-72bf-40eb-86c4-7bb372c0cad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699388322 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.699388322
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.4261345207
Short name T273
Test name
Test status
Simulation time 90421163 ps
CPU time 0.74 seconds
Started May 18 01:45:18 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 204288 kb
Host smart-d178623b-7b39-4944-970e-d04ee9913513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261345207 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
4261345207
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.2469858737
Short name T176
Test name
Test status
Simulation time 21005956 ps
CPU time 1.5 seconds
Started May 18 01:45:13 PM PDT 24
Finished May 18 01:45:15 PM PDT 24
Peak memory 204528 kb
Host smart-b4ad4d2a-2b28-4787-b670-bd980b816531
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469858737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.2469858737
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.3034830490
Short name T280
Test name
Test status
Simulation time 190791669 ps
CPU time 2.68 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:10 PM PDT 24
Peak memory 213112 kb
Host smart-c9cf8073-cd58-4c4b-a89e-2a07164bffa8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034830490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.3034830490
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3665996469
Short name T233
Test name
Test status
Simulation time 268418848 ps
CPU time 3.38 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:12 PM PDT 24
Peak memory 217988 kb
Host smart-16f30e58-e3ed-4eed-a786-3a39b3c1b927
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665996469 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3665996469
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.1609020681
Short name T244
Test name
Test status
Simulation time 87097692 ps
CPU time 1.89 seconds
Started May 18 01:45:08 PM PDT 24
Finished May 18 01:45:12 PM PDT 24
Peak memory 212756 kb
Host smart-975ed68a-35b2-4cf6-8c49-500696e2e4e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609020681 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
1609020681
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.3306205647
Short name T47
Test name
Test status
Simulation time 183947813 ps
CPU time 4.98 seconds
Started May 18 01:45:16 PM PDT 24
Finished May 18 01:45:23 PM PDT 24
Peak memory 212688 kb
Host smart-646493da-1821-464e-85eb-2f4f3b7ef21b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306205647 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.3306205647
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.303595417
Short name T201
Test name
Test status
Simulation time 60410240 ps
CPU time 1.19 seconds
Started May 18 01:45:14 PM PDT 24
Finished May 18 01:45:17 PM PDT 24
Peak memory 212668 kb
Host smart-9b6cb2b0-7b69-4b27-88a6-62cb1067172c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303595417 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.303595417
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.2812656104
Short name T202
Test name
Test status
Simulation time 101238905 ps
CPU time 1 seconds
Started May 18 01:45:18 PM PDT 24
Finished May 18 01:45:22 PM PDT 24
Peak memory 204424 kb
Host smart-4adbb828-f701-4d54-ac5c-9d5ef3b53d81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812656104 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
2812656104
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.3039638946
Short name T172
Test name
Test status
Simulation time 39840772 ps
CPU time 0.71 seconds
Started May 18 01:45:18 PM PDT 24
Finished May 18 01:45:22 PM PDT 24
Peak memory 204320 kb
Host smart-3279022b-66da-41f1-856e-3cb99f58ff36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039638946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
3039638946
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.2797395459
Short name T173
Test name
Test status
Simulation time 262252520 ps
CPU time 1.85 seconds
Started May 18 01:45:16 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 204472 kb
Host smart-870a35aa-9cd3-448b-a252-bb601274f117
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797395459 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.2797395459
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.4019702394
Short name T263
Test name
Test status
Simulation time 588250710 ps
CPU time 3.52 seconds
Started May 18 01:45:13 PM PDT 24
Finished May 18 01:45:18 PM PDT 24
Peak memory 212964 kb
Host smart-fd581d86-03e0-4f20-ab20-760d6b0b25fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019702394 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.4019702394
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1437134683
Short name T306
Test name
Test status
Simulation time 3281328567 ps
CPU time 7.32 seconds
Started May 18 01:45:14 PM PDT 24
Finished May 18 01:45:23 PM PDT 24
Peak memory 213076 kb
Host smart-75c52133-c479-4038-8115-f5526cf5175a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437134683 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1437134683
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.717670240
Short name T219
Test name
Test status
Simulation time 29758320 ps
CPU time 1.6 seconds
Started May 18 01:45:16 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 212636 kb
Host smart-bcc4664c-4e83-4b8a-988c-31274276c63f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717670240 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.717670240
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.282868097
Short name T234
Test name
Test status
Simulation time 24704348 ps
CPU time 0.86 seconds
Started May 18 01:45:15 PM PDT 24
Finished May 18 01:45:18 PM PDT 24
Peak memory 204336 kb
Host smart-66998e76-c199-4c89-a809-72d9504a7386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282868097 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.282868097
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.3613509493
Short name T230
Test name
Test status
Simulation time 21065527 ps
CPU time 0.89 seconds
Started May 18 01:45:18 PM PDT 24
Finished May 18 01:45:22 PM PDT 24
Peak memory 204300 kb
Host smart-fb29fad0-e36d-49c7-b877-bd9fafa1d675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613509493 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
3613509493
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.1862644999
Short name T217
Test name
Test status
Simulation time 103528404 ps
CPU time 1.81 seconds
Started May 18 01:45:16 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 204492 kb
Host smart-6b7b252a-cc5e-4030-b2d2-e1153b57d7a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862644999 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.1862644999
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.1305495606
Short name T303
Test name
Test status
Simulation time 390045847 ps
CPU time 3.07 seconds
Started May 18 01:45:16 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 213012 kb
Host smart-5fa9e66d-985f-4b9f-9a61-afe86f375f63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305495606 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.1305495606
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1672676115
Short name T60
Test name
Test status
Simulation time 180366420 ps
CPU time 2.35 seconds
Started May 18 01:45:17 PM PDT 24
Finished May 18 01:45:22 PM PDT 24
Peak memory 213032 kb
Host smart-c966fbf2-7de5-4a46-a104-512c3d22ce1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672676115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1672676115
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.229083893
Short name T53
Test name
Test status
Simulation time 321994586 ps
CPU time 4.03 seconds
Started May 18 01:45:16 PM PDT 24
Finished May 18 01:45:23 PM PDT 24
Peak memory 212980 kb
Host smart-a0e38d52-2fc9-4313-be38-02795beb3a07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229083893 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe
_tl_intg_err.229083893
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.987855717
Short name T301
Test name
Test status
Simulation time 53721088 ps
CPU time 1.21 seconds
Started May 18 01:45:14 PM PDT 24
Finished May 18 01:45:17 PM PDT 24
Peak memory 212652 kb
Host smart-0a11b75a-19c1-4cac-8cce-796562ceaa73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987855717 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.987855717
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1583791788
Short name T284
Test name
Test status
Simulation time 35692765 ps
CPU time 1.09 seconds
Started May 18 01:45:14 PM PDT 24
Finished May 18 01:45:17 PM PDT 24
Peak memory 204384 kb
Host smart-90696502-1694-43d8-a927-369a01aa73fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583791788 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
1583791788
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.1475710978
Short name T288
Test name
Test status
Simulation time 11233516 ps
CPU time 0.86 seconds
Started May 18 01:45:17 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 204324 kb
Host smart-639ae397-bd92-464d-a051-eb3d2fb9e1aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475710978 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
1475710978
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.2897568398
Short name T165
Test name
Test status
Simulation time 78851720 ps
CPU time 1.91 seconds
Started May 18 01:45:17 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 204312 kb
Host smart-04af7620-57b2-4915-8d60-79608177cfb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897568398 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.2897568398
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.709192075
Short name T218
Test name
Test status
Simulation time 291676176 ps
CPU time 1.69 seconds
Started May 18 01:45:15 PM PDT 24
Finished May 18 01:45:19 PM PDT 24
Peak memory 213100 kb
Host smart-4c017bf8-db43-487b-adc2-c35800633c33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709192075 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keym
gr_dpe_shadow_reg_errors.709192075
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.804797845
Short name T245
Test name
Test status
Simulation time 160742368 ps
CPU time 5.54 seconds
Started May 18 01:45:17 PM PDT 24
Finished May 18 01:45:26 PM PDT 24
Peak memory 212932 kb
Host smart-e4ce4a9b-cde9-4569-9066-247526472bc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804797845 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.804797845
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.874777300
Short name T275
Test name
Test status
Simulation time 30556511 ps
CPU time 1.77 seconds
Started May 18 01:45:18 PM PDT 24
Finished May 18 01:45:22 PM PDT 24
Peak memory 213896 kb
Host smart-a8ca23ad-9478-42ad-96fd-e4906e0f25a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874777300 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.874777300
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.3389622550
Short name T28
Test name
Test status
Simulation time 90292535 ps
CPU time 2.67 seconds
Started May 18 01:45:14 PM PDT 24
Finished May 18 01:45:19 PM PDT 24
Peak memory 213664 kb
Host smart-94486739-163a-44c3-a16b-e8c6225a653f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389622550 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.3389622550
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.4235016893
Short name T81
Test name
Test status
Simulation time 211382481 ps
CPU time 1.51 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:27 PM PDT 24
Peak memory 212872 kb
Host smart-eb3d9728-0d0e-4e2a-87aa-57142a319835
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235016893 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.4235016893
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.2474156736
Short name T258
Test name
Test status
Simulation time 31668212 ps
CPU time 1.12 seconds
Started May 18 01:45:17 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 204480 kb
Host smart-eac7c0a6-fb6c-4f3d-bbfc-c295116e61d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474156736 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
2474156736
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.3966818965
Short name T42
Test name
Test status
Simulation time 19216046 ps
CPU time 0.75 seconds
Started May 18 01:45:17 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 204288 kb
Host smart-a33f76e2-884b-4e97-91a8-5d59c4bc9dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966818965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
3966818965
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.879587199
Short name T72
Test name
Test status
Simulation time 33797147 ps
CPU time 1.72 seconds
Started May 18 01:45:17 PM PDT 24
Finished May 18 01:45:21 PM PDT 24
Peak memory 212552 kb
Host smart-1fd49044-aca4-49a2-af9f-dfee8a677029
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879587199 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_dpe_same_csr_outstanding.879587199
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.2099146340
Short name T195
Test name
Test status
Simulation time 282674989 ps
CPU time 1.74 seconds
Started May 18 01:45:16 PM PDT 24
Finished May 18 01:45:20 PM PDT 24
Peak memory 213032 kb
Host smart-93a106c1-bd16-47df-ba61-ce7f28595a54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099146340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.2099146340
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2500813995
Short name T85
Test name
Test status
Simulation time 2182758204 ps
CPU time 3.42 seconds
Started May 18 01:45:17 PM PDT 24
Finished May 18 01:45:23 PM PDT 24
Peak memory 213032 kb
Host smart-3bf2155b-ed3f-47d8-af85-371feff40f1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500813995 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2500813995
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.3801733785
Short name T299
Test name
Test status
Simulation time 34590948 ps
CPU time 2.26 seconds
Started May 18 01:45:18 PM PDT 24
Finished May 18 01:45:23 PM PDT 24
Peak memory 212608 kb
Host smart-981a7047-dbf5-4b98-b447-e47d0945382f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801733785 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
3801733785
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.2253061979
Short name T55
Test name
Test status
Simulation time 91337586 ps
CPU time 3.7 seconds
Started May 18 01:45:16 PM PDT 24
Finished May 18 01:45:23 PM PDT 24
Peak memory 212668 kb
Host smart-4aec4b7c-7818-43bf-ab15-ecf3abc7402a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253061979 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.2253061979
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.3896245377
Short name T246
Test name
Test status
Simulation time 32413947 ps
CPU time 0.98 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:27 PM PDT 24
Peak memory 204444 kb
Host smart-d9bc9fc7-a2a0-49ef-a489-015b9327c7d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896245377 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.3896245377
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.4258257726
Short name T216
Test name
Test status
Simulation time 96315965 ps
CPU time 1.11 seconds
Started May 18 01:45:21 PM PDT 24
Finished May 18 01:45:25 PM PDT 24
Peak memory 204520 kb
Host smart-3b3a23e2-8377-4a18-85c6-b876aefe3812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258257726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
4258257726
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.146395062
Short name T281
Test name
Test status
Simulation time 36786012 ps
CPU time 0.83 seconds
Started May 18 01:45:22 PM PDT 24
Finished May 18 01:45:26 PM PDT 24
Peak memory 204276 kb
Host smart-8e2249d6-441c-4fbe-854a-0f093ad057e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146395062 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.146395062
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.1562511328
Short name T32
Test name
Test status
Simulation time 85370712 ps
CPU time 2.38 seconds
Started May 18 01:45:27 PM PDT 24
Finished May 18 01:45:31 PM PDT 24
Peak memory 204500 kb
Host smart-76746767-f49e-46da-982b-abe6f80b6afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562511328 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.1562511328
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2125885748
Short name T268
Test name
Test status
Simulation time 183623548 ps
CPU time 2.37 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:28 PM PDT 24
Peak memory 213296 kb
Host smart-b0ae9e66-fc56-44f1-8631-4c2984d1c89e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125885748 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.2125885748
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3430617215
Short name T276
Test name
Test status
Simulation time 898838959 ps
CPU time 6.48 seconds
Started May 18 01:45:20 PM PDT 24
Finished May 18 01:45:30 PM PDT 24
Peak memory 213016 kb
Host smart-6146ced5-5a34-41d7-aeeb-6d0a2c42c5f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430617215 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3430617215
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.4126411337
Short name T38
Test name
Test status
Simulation time 68293069 ps
CPU time 3.09 seconds
Started May 18 01:45:21 PM PDT 24
Finished May 18 01:45:27 PM PDT 24
Peak memory 214956 kb
Host smart-9a884c9e-6237-4bbe-a3ef-799b34538698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126411337 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
4126411337
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.1306649056
Short name T251
Test name
Test status
Simulation time 31426752 ps
CPU time 1.25 seconds
Started May 18 01:45:28 PM PDT 24
Finished May 18 01:45:31 PM PDT 24
Peak memory 212748 kb
Host smart-0e6c139a-0561-48ba-8dea-1239794f9ec3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306649056 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.1306649056
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.2791962551
Short name T104
Test name
Test status
Simulation time 17546336 ps
CPU time 0.86 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:27 PM PDT 24
Peak memory 204448 kb
Host smart-1bc84699-afa9-4c44-a171-ac79a48e5d48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791962551 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
2791962551
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.398391998
Short name T206
Test name
Test status
Simulation time 27651658 ps
CPU time 0.7 seconds
Started May 18 01:45:21 PM PDT 24
Finished May 18 01:45:24 PM PDT 24
Peak memory 204348 kb
Host smart-eb0c2b4c-1910-42f4-a12a-792643ef5b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398391998 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.398391998
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.3963937726
Short name T266
Test name
Test status
Simulation time 133644755 ps
CPU time 1.38 seconds
Started May 18 01:45:21 PM PDT 24
Finished May 18 01:45:25 PM PDT 24
Peak memory 204496 kb
Host smart-3706113e-d640-4df5-b3e8-12aa2941c1b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963937726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.3963937726
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2305185649
Short name T84
Test name
Test status
Simulation time 120971830 ps
CPU time 3.4 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:29 PM PDT 24
Peak memory 212912 kb
Host smart-734b06d0-ff66-4987-9db5-671c00f0d685
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305185649 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.2305185649
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2526378063
Short name T197
Test name
Test status
Simulation time 177222811 ps
CPU time 3.56 seconds
Started May 18 01:45:24 PM PDT 24
Finished May 18 01:45:30 PM PDT 24
Peak memory 213080 kb
Host smart-619f6689-dce4-4b9d-b797-dc5e4d44c3be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526378063 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2526378063
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.4232416463
Short name T308
Test name
Test status
Simulation time 37458273 ps
CPU time 1.89 seconds
Started May 18 01:45:24 PM PDT 24
Finished May 18 01:45:28 PM PDT 24
Peak memory 214320 kb
Host smart-3877bb01-350f-44a4-a63e-0afd12dcf72b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232416463 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
4232416463
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.2440793474
Short name T259
Test name
Test status
Simulation time 360090614 ps
CPU time 2.99 seconds
Started May 18 01:45:21 PM PDT 24
Finished May 18 01:45:27 PM PDT 24
Peak memory 212704 kb
Host smart-74c68473-d9fc-4476-963e-d9dac94641d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440793474 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.2440793474
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.4003827691
Short name T27
Test name
Test status
Simulation time 39460966 ps
CPU time 1.29 seconds
Started May 18 01:45:22 PM PDT 24
Finished May 18 01:45:26 PM PDT 24
Peak memory 212660 kb
Host smart-857685f5-de0f-4a4e-9b1e-e8e4508381ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003827691 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.4003827691
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.1509320268
Short name T221
Test name
Test status
Simulation time 21412330 ps
CPU time 0.94 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:27 PM PDT 24
Peak memory 204388 kb
Host smart-5153147f-6249-4dfb-9b6b-61a738d0248d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509320268 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
1509320268
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.290745956
Short name T243
Test name
Test status
Simulation time 11215262 ps
CPU time 0.79 seconds
Started May 18 01:45:26 PM PDT 24
Finished May 18 01:45:29 PM PDT 24
Peak memory 204272 kb
Host smart-cd797a94-a779-4cc7-a203-7d21e44bd935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290745956 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.290745956
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.425533521
Short name T73
Test name
Test status
Simulation time 76021321 ps
CPU time 2.29 seconds
Started May 18 01:45:22 PM PDT 24
Finished May 18 01:45:27 PM PDT 24
Peak memory 204440 kb
Host smart-94f735cc-afb1-4387-8686-f9fe495bf0ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425533521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.k
eymgr_dpe_same_csr_outstanding.425533521
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.2128653065
Short name T264
Test name
Test status
Simulation time 162730761 ps
CPU time 2.01 seconds
Started May 18 01:45:32 PM PDT 24
Finished May 18 01:45:37 PM PDT 24
Peak memory 213100 kb
Host smart-62174d1c-ab62-4428-8327-c90cb5a1091c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128653065 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.2128653065
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.1626700310
Short name T304
Test name
Test status
Simulation time 283297835 ps
CPU time 5.48 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:31 PM PDT 24
Peak memory 213004 kb
Host smart-20598cb7-785c-4c86-94ab-dbede2958dd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626700310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.1626700310
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.1557748176
Short name T295
Test name
Test status
Simulation time 106092665 ps
CPU time 3.97 seconds
Started May 18 01:45:22 PM PDT 24
Finished May 18 01:45:29 PM PDT 24
Peak memory 220920 kb
Host smart-0c453935-c39c-4f6e-bb13-1d2393b1e460
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557748176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
1557748176
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2866201353
Short name T80
Test name
Test status
Simulation time 67604987 ps
CPU time 1.5 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:27 PM PDT 24
Peak memory 212808 kb
Host smart-25417dc2-2445-4024-835a-0942a5614afd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866201353 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.2866201353
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.1059193102
Short name T65
Test name
Test status
Simulation time 55197454 ps
CPU time 0.87 seconds
Started May 18 01:45:25 PM PDT 24
Finished May 18 01:45:28 PM PDT 24
Peak memory 204368 kb
Host smart-8924315b-7bee-4cc1-ac56-27c2b869202d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059193102 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
1059193102
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1420733667
Short name T272
Test name
Test status
Simulation time 107918983 ps
CPU time 2.06 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:28 PM PDT 24
Peak memory 204412 kb
Host smart-c6a2d1cf-c447-4bd8-b6f2-dc78c8616bc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420733667 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.1420733667
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.2714546539
Short name T282
Test name
Test status
Simulation time 82201319 ps
CPU time 1.92 seconds
Started May 18 01:45:23 PM PDT 24
Finished May 18 01:45:28 PM PDT 24
Peak memory 213040 kb
Host smart-c49c2d82-7480-487a-ad8d-7dca244ce97a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714546539 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.2714546539
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2452692227
Short name T242
Test name
Test status
Simulation time 538053220 ps
CPU time 5.16 seconds
Started May 18 01:45:25 PM PDT 24
Finished May 18 01:45:32 PM PDT 24
Peak memory 212968 kb
Host smart-6a05b117-f162-4605-8b52-48f32dd184f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452692227 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2452692227
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.527742861
Short name T199
Test name
Test status
Simulation time 32234043 ps
CPU time 1.88 seconds
Started May 18 01:45:29 PM PDT 24
Finished May 18 01:45:32 PM PDT 24
Peak memory 220912 kb
Host smart-ba818807-7416-45e1-b563-9f09c0e4e521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527742861 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.527742861
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.876976695
Short name T57
Test name
Test status
Simulation time 305818402 ps
CPU time 4.27 seconds
Started May 18 01:45:21 PM PDT 24
Finished May 18 01:45:29 PM PDT 24
Peak memory 212748 kb
Host smart-e22f3541-357c-42de-97a4-726aed4967e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876976695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe
_tl_intg_err.876976695
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.843515019
Short name T20
Test name
Test status
Simulation time 91405054 ps
CPU time 1.26 seconds
Started May 18 01:45:32 PM PDT 24
Finished May 18 01:45:37 PM PDT 24
Peak memory 212696 kb
Host smart-a841d243-bbcc-4065-a168-7bd103c30ede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843515019 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.843515019
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1671917562
Short name T309
Test name
Test status
Simulation time 31969322 ps
CPU time 0.95 seconds
Started May 18 01:45:22 PM PDT 24
Finished May 18 01:45:26 PM PDT 24
Peak memory 204376 kb
Host smart-22956236-7d57-46e5-84f1-dfd30bd86575
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671917562 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
1671917562
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.2833281382
Short name T43
Test name
Test status
Simulation time 21715403 ps
CPU time 0.84 seconds
Started May 18 01:45:27 PM PDT 24
Finished May 18 01:45:29 PM PDT 24
Peak memory 204364 kb
Host smart-5541acb5-5d0e-4b86-b637-563aed5f3842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833281382 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
2833281382
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.658115908
Short name T239
Test name
Test status
Simulation time 29176755 ps
CPU time 1.6 seconds
Started May 18 01:45:26 PM PDT 24
Finished May 18 01:45:29 PM PDT 24
Peak memory 204532 kb
Host smart-7b8c00a8-8b56-49a1-b2e3-750995377354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658115908 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k
eymgr_dpe_same_csr_outstanding.658115908
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2816839093
Short name T240
Test name
Test status
Simulation time 90821086 ps
CPU time 2.05 seconds
Started May 18 01:45:25 PM PDT 24
Finished May 18 01:45:29 PM PDT 24
Peak memory 213016 kb
Host smart-10102c43-667a-4966-b763-d752a0ead406
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816839093 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2816839093
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.2054285292
Short name T58
Test name
Test status
Simulation time 543101984 ps
CPU time 4.66 seconds
Started May 18 01:45:20 PM PDT 24
Finished May 18 01:45:28 PM PDT 24
Peak memory 213000 kb
Host smart-c24ee3d0-9096-4214-ba15-ca07e6403937
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054285292 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.2054285292
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.1735074332
Short name T188
Test name
Test status
Simulation time 432553620 ps
CPU time 2.72 seconds
Started May 18 01:45:25 PM PDT 24
Finished May 18 01:45:30 PM PDT 24
Peak memory 212632 kb
Host smart-e1e502fc-8374-4efc-9770-8e00746de8ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735074332 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
1735074332
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.2526204371
Short name T45
Test name
Test status
Simulation time 115036017 ps
CPU time 4.53 seconds
Started May 18 01:45:27 PM PDT 24
Finished May 18 01:45:33 PM PDT 24
Peak memory 212720 kb
Host smart-dce82e7d-ab3a-4553-a345-41ef41765629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526204371 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.2526204371
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.2593391853
Short name T166
Test name
Test status
Simulation time 882832774 ps
CPU time 6.06 seconds
Started May 18 01:44:40 PM PDT 24
Finished May 18 01:44:47 PM PDT 24
Peak memory 204532 kb
Host smart-bddc1e74-2b2d-4026-b52a-2fafab928378
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593391853 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.2593391853
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.166944759
Short name T250
Test name
Test status
Simulation time 1783995043 ps
CPU time 11.67 seconds
Started May 18 01:44:41 PM PDT 24
Finished May 18 01:44:54 PM PDT 24
Peak memory 204576 kb
Host smart-8dbe6edd-8178-4c08-b450-94fc7763d7ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166944759 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_bit_bash.166944759
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2896848907
Short name T226
Test name
Test status
Simulation time 212106913 ps
CPU time 1.28 seconds
Started May 18 01:44:41 PM PDT 24
Finished May 18 01:44:43 PM PDT 24
Peak memory 204408 kb
Host smart-04c9e2e3-c773-4c71-9b7f-e739d9eeea51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896848907 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.2896848907
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.2207480854
Short name T297
Test name
Test status
Simulation time 20573355 ps
CPU time 1.76 seconds
Started May 18 01:44:49 PM PDT 24
Finished May 18 01:44:53 PM PDT 24
Peak memory 212684 kb
Host smart-931a69aa-9800-4d5a-9bf3-511ea0c2c41c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207480854 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.2207480854
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2036626191
Short name T238
Test name
Test status
Simulation time 56033827 ps
CPU time 0.94 seconds
Started May 18 01:44:40 PM PDT 24
Finished May 18 01:44:42 PM PDT 24
Peak memory 204356 kb
Host smart-76340e09-3d28-4a74-b19d-32802b548fbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036626191 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.2
036626191
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.2668538568
Short name T41
Test name
Test status
Simulation time 16280137 ps
CPU time 0.77 seconds
Started May 18 01:44:38 PM PDT 24
Finished May 18 01:44:39 PM PDT 24
Peak memory 204288 kb
Host smart-31a001b3-151f-44ce-8b60-3a0b79d184c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668538568 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.2
668538568
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.577707587
Short name T293
Test name
Test status
Simulation time 88792671 ps
CPU time 1.91 seconds
Started May 18 01:44:49 PM PDT 24
Finished May 18 01:44:52 PM PDT 24
Peak memory 204452 kb
Host smart-f1854038-e3be-41b2-927a-93333e11635b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577707587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.ke
ymgr_dpe_same_csr_outstanding.577707587
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.3914371745
Short name T82
Test name
Test status
Simulation time 267555779 ps
CPU time 2.39 seconds
Started May 18 01:44:40 PM PDT 24
Finished May 18 01:44:43 PM PDT 24
Peak memory 212940 kb
Host smart-285db827-48fc-47a3-9fac-48194d052b00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914371745 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.3914371745
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.560471779
Short name T61
Test name
Test status
Simulation time 785339951 ps
CPU time 5.34 seconds
Started May 18 01:44:40 PM PDT 24
Finished May 18 01:44:47 PM PDT 24
Peak memory 212952 kb
Host smart-455fa8fb-a4df-4942-b535-494f496a93bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560471779 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.560471779
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.2358756298
Short name T198
Test name
Test status
Simulation time 75843943 ps
CPU time 1.97 seconds
Started May 18 01:44:40 PM PDT 24
Finished May 18 01:44:43 PM PDT 24
Peak memory 212716 kb
Host smart-12bd580d-3631-4a23-ab2e-7e012dcb3dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358756298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.2
358756298
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.3129159223
Short name T291
Test name
Test status
Simulation time 108211684 ps
CPU time 4.5 seconds
Started May 18 01:44:43 PM PDT 24
Finished May 18 01:44:49 PM PDT 24
Peak memory 213252 kb
Host smart-490fe018-4df2-4fec-8c05-18cec32ea9e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129159223 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.3129159223
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.3088594180
Short name T164
Test name
Test status
Simulation time 14105821 ps
CPU time 0.79 seconds
Started May 18 01:45:30 PM PDT 24
Finished May 18 01:45:34 PM PDT 24
Peak memory 204388 kb
Host smart-f45f4c45-8884-4dd3-a258-490c10817c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088594180 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
3088594180
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.768463350
Short name T252
Test name
Test status
Simulation time 11675315 ps
CPU time 0.72 seconds
Started May 18 01:45:30 PM PDT 24
Finished May 18 01:45:34 PM PDT 24
Peak memory 204240 kb
Host smart-c981492f-4439-49f0-a146-170334b37178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768463350 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.768463350
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.2268714159
Short name T170
Test name
Test status
Simulation time 10083991 ps
CPU time 0.69 seconds
Started May 18 01:45:31 PM PDT 24
Finished May 18 01:45:35 PM PDT 24
Peak memory 204292 kb
Host smart-2b4305d2-da2d-4d93-a727-0d2c32729c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268714159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
2268714159
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.2779974769
Short name T179
Test name
Test status
Simulation time 14943178 ps
CPU time 0.71 seconds
Started May 18 01:45:33 PM PDT 24
Finished May 18 01:45:37 PM PDT 24
Peak memory 204416 kb
Host smart-c01555d0-dc56-48b7-a056-af46859a7297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779974769 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
2779974769
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.3940037506
Short name T248
Test name
Test status
Simulation time 20413887 ps
CPU time 0.71 seconds
Started May 18 01:45:31 PM PDT 24
Finished May 18 01:45:35 PM PDT 24
Peak memory 204344 kb
Host smart-5d0df448-05df-48f2-bea2-d26f5fee3b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940037506 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
3940037506
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.3645344743
Short name T253
Test name
Test status
Simulation time 11336443 ps
CPU time 0.84 seconds
Started May 18 01:45:32 PM PDT 24
Finished May 18 01:45:36 PM PDT 24
Peak memory 204252 kb
Host smart-3cf7d191-3efc-4f96-a4f4-df009d9c14f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645344743 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
3645344743
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.3801420040
Short name T177
Test name
Test status
Simulation time 13243607 ps
CPU time 0.76 seconds
Started May 18 01:45:31 PM PDT 24
Finished May 18 01:45:35 PM PDT 24
Peak memory 204260 kb
Host smart-9531bb9b-cefc-43db-94d6-86f1329607f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801420040 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
3801420040
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.360706089
Short name T290
Test name
Test status
Simulation time 11989402 ps
CPU time 0.78 seconds
Started May 18 01:45:30 PM PDT 24
Finished May 18 01:45:34 PM PDT 24
Peak memory 204336 kb
Host smart-fed2bed9-89f0-45a6-99f0-e2095e72e28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360706089 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.360706089
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.3926173319
Short name T186
Test name
Test status
Simulation time 18489547 ps
CPU time 0.71 seconds
Started May 18 01:45:30 PM PDT 24
Finished May 18 01:45:34 PM PDT 24
Peak memory 204292 kb
Host smart-f0a6c20b-8d99-4192-a1af-c0bb9b9a34ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926173319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
3926173319
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.4140521667
Short name T236
Test name
Test status
Simulation time 11982281 ps
CPU time 0.87 seconds
Started May 18 01:45:31 PM PDT 24
Finished May 18 01:45:35 PM PDT 24
Peak memory 204324 kb
Host smart-caca1dfb-d019-40b1-aaf4-47ed3e6ed916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140521667 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
4140521667
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.2873194538
Short name T302
Test name
Test status
Simulation time 309286334 ps
CPU time 5.57 seconds
Started May 18 01:44:49 PM PDT 24
Finished May 18 01:44:56 PM PDT 24
Peak memory 204404 kb
Host smart-3c5f0df7-4bce-4f3c-8e89-81e47498cd6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873194538 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.2873194538
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.2358914024
Short name T187
Test name
Test status
Simulation time 343095094 ps
CPU time 10.52 seconds
Started May 18 01:44:47 PM PDT 24
Finished May 18 01:44:58 PM PDT 24
Peak memory 204564 kb
Host smart-622ca322-c480-452e-9a70-9681858bb77b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358914024 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.2358914024
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.973202589
Short name T167
Test name
Test status
Simulation time 18006593 ps
CPU time 1.01 seconds
Started May 18 01:44:48 PM PDT 24
Finished May 18 01:44:50 PM PDT 24
Peak memory 204392 kb
Host smart-02f41f78-2b24-4d84-b57c-cae04ae665c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973202589 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_hw_reset.973202589
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.3692957413
Short name T292
Test name
Test status
Simulation time 33884138 ps
CPU time 1.41 seconds
Started May 18 01:44:48 PM PDT 24
Finished May 18 01:44:50 PM PDT 24
Peak memory 212664 kb
Host smart-2d6bfd71-6d8d-477a-8bdc-297e3d79858f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692957413 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.3692957413
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.1886078641
Short name T191
Test name
Test status
Simulation time 45840052 ps
CPU time 1.35 seconds
Started May 18 01:44:47 PM PDT 24
Finished May 18 01:44:49 PM PDT 24
Peak memory 204468 kb
Host smart-25b41357-a3cf-4376-bb53-1abb6da92654
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886078641 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.1
886078641
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.4065514885
Short name T66
Test name
Test status
Simulation time 23819482 ps
CPU time 0.74 seconds
Started May 18 01:44:50 PM PDT 24
Finished May 18 01:44:52 PM PDT 24
Peak memory 204256 kb
Host smart-d7a14b88-26fc-45ba-ba7d-e483aa8a6154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065514885 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.4
065514885
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.1691385219
Short name T174
Test name
Test status
Simulation time 280858448 ps
CPU time 2.55 seconds
Started May 18 01:44:48 PM PDT 24
Finished May 18 01:44:52 PM PDT 24
Peak memory 204444 kb
Host smart-61a05ac0-621b-4eb0-ab67-cdeedf0bc18a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691385219 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.1691385219
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.1378923208
Short name T235
Test name
Test status
Simulation time 47271501 ps
CPU time 1.44 seconds
Started May 18 01:44:51 PM PDT 24
Finished May 18 01:44:53 PM PDT 24
Peak memory 212992 kb
Host smart-343d054f-ad18-4d56-8ddf-29e518973dda
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378923208 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.1378923208
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3841351981
Short name T62
Test name
Test status
Simulation time 184390337 ps
CPU time 5.65 seconds
Started May 18 01:44:51 PM PDT 24
Finished May 18 01:44:58 PM PDT 24
Peak memory 218156 kb
Host smart-6458db9b-d40e-4529-a1b8-f7b2a23be8ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841351981 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3841351981
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.2574136682
Short name T39
Test name
Test status
Simulation time 111810811 ps
CPU time 2.31 seconds
Started May 18 01:44:48 PM PDT 24
Finished May 18 01:44:52 PM PDT 24
Peak memory 220860 kb
Host smart-2746763a-a806-407c-8141-02d292fec11d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574136682 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.2
574136682
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.771485671
Short name T287
Test name
Test status
Simulation time 321028775 ps
CPU time 3.49 seconds
Started May 18 01:44:49 PM PDT 24
Finished May 18 01:44:54 PM PDT 24
Peak memory 212808 kb
Host smart-4117226d-187e-4418-b90d-f7edbf4c7a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771485671 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_
tl_intg_err.771485671
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.1282836781
Short name T208
Test name
Test status
Simulation time 47075695 ps
CPU time 0.87 seconds
Started May 18 01:45:29 PM PDT 24
Finished May 18 01:45:31 PM PDT 24
Peak memory 204328 kb
Host smart-cde18e5c-a42e-4dd2-be1b-ea7904769be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282836781 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
1282836781
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.1735163496
Short name T64
Test name
Test status
Simulation time 17488287 ps
CPU time 0.72 seconds
Started May 18 01:45:32 PM PDT 24
Finished May 18 01:45:36 PM PDT 24
Peak memory 204336 kb
Host smart-ed946c36-2430-4e80-87e4-08f376b1adf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735163496 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
1735163496
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.1833190870
Short name T305
Test name
Test status
Simulation time 12186144 ps
CPU time 0.82 seconds
Started May 18 01:45:29 PM PDT 24
Finished May 18 01:45:32 PM PDT 24
Peak memory 204312 kb
Host smart-320aedba-2a05-4b66-b33c-1f65bce379fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833190870 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
1833190870
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.2815547950
Short name T105
Test name
Test status
Simulation time 46339575 ps
CPU time 0.7 seconds
Started May 18 01:45:29 PM PDT 24
Finished May 18 01:45:32 PM PDT 24
Peak memory 204340 kb
Host smart-dbd5ea81-c95b-4c4d-878f-576084fad31d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815547950 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
2815547950
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.1094914073
Short name T182
Test name
Test status
Simulation time 15590072 ps
CPU time 0.79 seconds
Started May 18 01:45:35 PM PDT 24
Finished May 18 01:45:38 PM PDT 24
Peak memory 204328 kb
Host smart-b7699870-a987-45ef-b8eb-fd1642be9f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094914073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
1094914073
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.1571481297
Short name T285
Test name
Test status
Simulation time 10431811 ps
CPU time 0.82 seconds
Started May 18 01:45:33 PM PDT 24
Finished May 18 01:45:37 PM PDT 24
Peak memory 204292 kb
Host smart-cb000583-58bd-4166-9a53-c5c98259996d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571481297 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
1571481297
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.1630568820
Short name T183
Test name
Test status
Simulation time 9635481 ps
CPU time 0.71 seconds
Started May 18 01:45:31 PM PDT 24
Finished May 18 01:45:35 PM PDT 24
Peak memory 204336 kb
Host smart-61c02a82-ece9-4032-85fa-feb9926ccb38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630568820 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
1630568820
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.1922786998
Short name T63
Test name
Test status
Simulation time 9851875 ps
CPU time 0.73 seconds
Started May 18 01:45:29 PM PDT 24
Finished May 18 01:45:32 PM PDT 24
Peak memory 204320 kb
Host smart-a5ff14ab-84a8-48e2-877a-dbec850fde6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922786998 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
1922786998
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3197915464
Short name T289
Test name
Test status
Simulation time 8462156 ps
CPU time 0.78 seconds
Started May 18 01:45:30 PM PDT 24
Finished May 18 01:45:34 PM PDT 24
Peak memory 204356 kb
Host smart-cdf82583-12e0-42b8-a7f5-2c71f23d80b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197915464 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
3197915464
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3491187118
Short name T200
Test name
Test status
Simulation time 11438671 ps
CPU time 0.92 seconds
Started May 18 01:45:31 PM PDT 24
Finished May 18 01:45:36 PM PDT 24
Peak memory 204304 kb
Host smart-67f86016-0517-4392-8476-2d45cd3fe565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491187118 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
3491187118
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.3125087274
Short name T205
Test name
Test status
Simulation time 87891517 ps
CPU time 5.54 seconds
Started May 18 01:44:59 PM PDT 24
Finished May 18 01:45:06 PM PDT 24
Peak memory 204400 kb
Host smart-7557a0eb-4a34-4f8f-b743-ce10a0e4f5a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125087274 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.3125087274
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.4071309765
Short name T163
Test name
Test status
Simulation time 296957702 ps
CPU time 8.5 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:16 PM PDT 24
Peak memory 204616 kb
Host smart-104d09e5-595f-45ef-b229-5f16149628e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071309765 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.4071309765
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.1967369879
Short name T296
Test name
Test status
Simulation time 123633303 ps
CPU time 1.08 seconds
Started May 18 01:44:48 PM PDT 24
Finished May 18 01:44:50 PM PDT 24
Peak memory 204432 kb
Host smart-f8a8a3ed-11b2-48e2-aa00-b5c887dc08c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967369879 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.1967369879
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1894002102
Short name T30
Test name
Test status
Simulation time 21701693 ps
CPU time 1.47 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:10 PM PDT 24
Peak memory 212704 kb
Host smart-75604345-380c-48ad-a81a-331982469d2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894002102 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.1894002102
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1043404856
Short name T220
Test name
Test status
Simulation time 12582827 ps
CPU time 0.87 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:09 PM PDT 24
Peak memory 204452 kb
Host smart-a0e1984f-6452-45ca-99e5-eaaab3df028d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043404856 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1
043404856
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.488631990
Short name T193
Test name
Test status
Simulation time 22244145 ps
CPU time 1 seconds
Started May 18 01:44:48 PM PDT 24
Finished May 18 01:44:51 PM PDT 24
Peak memory 204444 kb
Host smart-16667378-1cf1-42f2-9239-97b173658e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488631990 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.488631990
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.1828133842
Short name T185
Test name
Test status
Simulation time 40235381 ps
CPU time 1.85 seconds
Started May 18 01:44:56 PM PDT 24
Finished May 18 01:44:59 PM PDT 24
Peak memory 204400 kb
Host smart-c2f9988f-8814-4a5c-bf32-23274673633f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828133842 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.1828133842
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.1885191305
Short name T249
Test name
Test status
Simulation time 249426553 ps
CPU time 2.48 seconds
Started May 18 01:44:48 PM PDT 24
Finished May 18 01:44:51 PM PDT 24
Peak memory 213068 kb
Host smart-f2ab320d-7530-4bca-a458-757489be5998
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885191305 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.1885191305
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.2343102956
Short name T283
Test name
Test status
Simulation time 242986230 ps
CPU time 6.15 seconds
Started May 18 01:44:47 PM PDT 24
Finished May 18 01:44:54 PM PDT 24
Peak memory 213028 kb
Host smart-94906232-0a5f-4bc5-9b4e-baeefde64a12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343102956 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.2343102956
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.3850220739
Short name T227
Test name
Test status
Simulation time 64550963 ps
CPU time 1.78 seconds
Started May 18 01:44:49 PM PDT 24
Finished May 18 01:44:53 PM PDT 24
Peak memory 212968 kb
Host smart-f50a0b5d-b3a4-46a0-bef3-af9f57123dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850220739 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.3
850220739
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.1118627748
Short name T54
Test name
Test status
Simulation time 680118807 ps
CPU time 2.44 seconds
Started May 18 01:44:49 PM PDT 24
Finished May 18 01:44:53 PM PDT 24
Peak memory 212732 kb
Host smart-48e75545-bdf9-4c67-b17d-6f5eca5dd022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118627748 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.1118627748
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.2924451689
Short name T247
Test name
Test status
Simulation time 33788848 ps
CPU time 0.69 seconds
Started May 18 01:45:34 PM PDT 24
Finished May 18 01:45:37 PM PDT 24
Peak memory 204352 kb
Host smart-109ffa4e-413a-4ab0-ab5a-027b4ed85e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924451689 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
2924451689
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.200649054
Short name T300
Test name
Test status
Simulation time 15642282 ps
CPU time 0.71 seconds
Started May 18 01:45:29 PM PDT 24
Finished May 18 01:45:32 PM PDT 24
Peak memory 204288 kb
Host smart-89cc76e8-22dc-42e6-9e89-3e2e1a36cfbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200649054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.200649054
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.2249358318
Short name T168
Test name
Test status
Simulation time 9538403 ps
CPU time 0.71 seconds
Started May 18 01:45:30 PM PDT 24
Finished May 18 01:45:33 PM PDT 24
Peak memory 204344 kb
Host smart-14d7ebd8-c6a2-41c2-bd02-326120ba7a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249358318 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
2249358318
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.3908887448
Short name T189
Test name
Test status
Simulation time 15689652 ps
CPU time 0.82 seconds
Started May 18 01:45:31 PM PDT 24
Finished May 18 01:45:36 PM PDT 24
Peak memory 204316 kb
Host smart-35fef821-788a-4710-a50d-e44712ec9e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908887448 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
3908887448
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.2741138792
Short name T286
Test name
Test status
Simulation time 91707537 ps
CPU time 0.73 seconds
Started May 18 01:45:31 PM PDT 24
Finished May 18 01:45:36 PM PDT 24
Peak memory 204296 kb
Host smart-b488d2f7-ddad-4da8-9173-740b6722e0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741138792 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
2741138792
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.889793439
Short name T271
Test name
Test status
Simulation time 9362698 ps
CPU time 0.73 seconds
Started May 18 01:45:29 PM PDT 24
Finished May 18 01:45:33 PM PDT 24
Peak memory 204348 kb
Host smart-872ef388-27bc-4b73-8997-7bae6992a7fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889793439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.889793439
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.2688343208
Short name T254
Test name
Test status
Simulation time 46954576 ps
CPU time 0.97 seconds
Started May 18 01:45:32 PM PDT 24
Finished May 18 01:45:36 PM PDT 24
Peak memory 204488 kb
Host smart-86c4c750-83aa-4a4c-9e4a-1cb8473df874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688343208 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
2688343208
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3842689765
Short name T269
Test name
Test status
Simulation time 25170196 ps
CPU time 0.75 seconds
Started May 18 01:45:30 PM PDT 24
Finished May 18 01:45:33 PM PDT 24
Peak memory 204292 kb
Host smart-382d4d0d-4eb3-4599-9871-2aca13944c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842689765 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
3842689765
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.83022568
Short name T203
Test name
Test status
Simulation time 15117469 ps
CPU time 0.82 seconds
Started May 18 01:45:29 PM PDT 24
Finished May 18 01:45:31 PM PDT 24
Peak memory 204360 kb
Host smart-3c431d56-d606-4385-900b-9a2e4ee460cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83022568 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.83022568
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.2641469695
Short name T261
Test name
Test status
Simulation time 30194552 ps
CPU time 0.77 seconds
Started May 18 01:45:30 PM PDT 24
Finished May 18 01:45:34 PM PDT 24
Peak memory 204292 kb
Host smart-75076bcc-fa5a-4b67-86fe-1b26768cf762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641469695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
2641469695
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.2103407837
Short name T88
Test name
Test status
Simulation time 166943635 ps
CPU time 1.1 seconds
Started May 18 01:44:56 PM PDT 24
Finished May 18 01:44:58 PM PDT 24
Peak memory 204452 kb
Host smart-5d3eeb0e-158e-44f1-a3fe-faab11597d14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103407837 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.2103407837
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.115154578
Short name T211
Test name
Test status
Simulation time 41596440 ps
CPU time 1.08 seconds
Started May 18 01:44:57 PM PDT 24
Finished May 18 01:45:00 PM PDT 24
Peak memory 204408 kb
Host smart-e44cf7e9-0b8c-489a-8bd9-37546f986582
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115154578 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.115154578
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.1545951982
Short name T307
Test name
Test status
Simulation time 7705289 ps
CPU time 0.73 seconds
Started May 18 01:44:57 PM PDT 24
Finished May 18 01:44:59 PM PDT 24
Peak memory 204336 kb
Host smart-c6d04ffd-d7e7-4963-a432-3b655a8b0110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545951982 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.1
545951982
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.3001275459
Short name T210
Test name
Test status
Simulation time 41078696 ps
CPU time 2.14 seconds
Started May 18 01:45:00 PM PDT 24
Finished May 18 01:45:03 PM PDT 24
Peak memory 204444 kb
Host smart-7b0e5401-7a06-4be7-9b9a-8a46cab191f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001275459 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.3001275459
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.3188669798
Short name T298
Test name
Test status
Simulation time 291709948 ps
CPU time 2.44 seconds
Started May 18 01:44:57 PM PDT 24
Finished May 18 01:45:01 PM PDT 24
Peak memory 212960 kb
Host smart-2c1415d4-ad0b-4dae-bf9f-9217dfa556df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188669798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.3188669798
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.903588794
Short name T255
Test name
Test status
Simulation time 1600045745 ps
CPU time 5.62 seconds
Started May 18 01:44:58 PM PDT 24
Finished May 18 01:45:05 PM PDT 24
Peak memory 213108 kb
Host smart-6f48cf6a-a039-4f20-9e5a-67dc7976645f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903588794 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.903588794
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.4161830041
Short name T26
Test name
Test status
Simulation time 276507987 ps
CPU time 2.33 seconds
Started May 18 01:44:58 PM PDT 24
Finished May 18 01:45:02 PM PDT 24
Peak memory 220864 kb
Host smart-41c31c18-2355-47e7-a5d7-0d5fa2f62203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161830041 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.4
161830041
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.987083747
Short name T50
Test name
Test status
Simulation time 915738376 ps
CPU time 5.93 seconds
Started May 18 01:44:57 PM PDT 24
Finished May 18 01:45:05 PM PDT 24
Peak memory 213672 kb
Host smart-2d39cf3e-df02-4861-89f0-25a650ec514e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987083747 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_
tl_intg_err.987083747
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.880859822
Short name T190
Test name
Test status
Simulation time 18431842 ps
CPU time 1.59 seconds
Started May 18 01:44:58 PM PDT 24
Finished May 18 01:45:01 PM PDT 24
Peak memory 212648 kb
Host smart-9b9c1056-5618-4e4a-9865-1348cc705e77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880859822 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.880859822
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.1622535075
Short name T169
Test name
Test status
Simulation time 15726548 ps
CPU time 0.99 seconds
Started May 18 01:44:57 PM PDT 24
Finished May 18 01:44:59 PM PDT 24
Peak memory 204396 kb
Host smart-c27115c8-cb5c-4e4a-8e97-35e90617a347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622535075 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.1
622535075
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.4288740616
Short name T196
Test name
Test status
Simulation time 15775140 ps
CPU time 0.75 seconds
Started May 18 01:44:59 PM PDT 24
Finished May 18 01:45:01 PM PDT 24
Peak memory 204372 kb
Host smart-8ac0dcb1-89fb-4aff-bd9f-fdf04edd3ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288740616 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.4
288740616
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.3392462462
Short name T237
Test name
Test status
Simulation time 846735600 ps
CPU time 2.56 seconds
Started May 18 01:44:57 PM PDT 24
Finished May 18 01:45:00 PM PDT 24
Peak memory 204536 kb
Host smart-17a819b1-cb70-4916-91af-725ec9dd6325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392462462 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.3392462462
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.2699345038
Short name T229
Test name
Test status
Simulation time 129029863 ps
CPU time 2.03 seconds
Started May 18 01:45:08 PM PDT 24
Finished May 18 01:45:12 PM PDT 24
Peak memory 213028 kb
Host smart-89260e38-7e3b-4193-8b6f-9fec50946e56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699345038 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.2699345038
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.1652353996
Short name T59
Test name
Test status
Simulation time 222437313 ps
CPU time 7.27 seconds
Started May 18 01:44:57 PM PDT 24
Finished May 18 01:45:06 PM PDT 24
Peak memory 213008 kb
Host smart-2956758d-3ee5-47e0-9a2c-eee0e261728f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652353996 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.1652353996
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.3008095972
Short name T36
Test name
Test status
Simulation time 37768315 ps
CPU time 2.96 seconds
Started May 18 01:44:57 PM PDT 24
Finished May 18 01:45:02 PM PDT 24
Peak memory 220800 kb
Host smart-5cbeb3c1-de17-4a27-8fe7-7ae4f40bf5d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008095972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.3
008095972
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3622467364
Short name T56
Test name
Test status
Simulation time 167919816 ps
CPU time 3.67 seconds
Started May 18 01:45:00 PM PDT 24
Finished May 18 01:45:04 PM PDT 24
Peak memory 212688 kb
Host smart-705fc717-cb97-4de1-8403-4fc8f8f30806
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622467364 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.3622467364
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.2062948343
Short name T214
Test name
Test status
Simulation time 39731495 ps
CPU time 0.94 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:09 PM PDT 24
Peak memory 204432 kb
Host smart-e3e99bbe-793a-4216-8452-90c3a0c56508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062948343 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.2062948343
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.216710847
Short name T178
Test name
Test status
Simulation time 34634409 ps
CPU time 0.92 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:09 PM PDT 24
Peak memory 204336 kb
Host smart-97c5bd8d-5bd5-4404-a74d-d819425cff33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216710847 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.216710847
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.3280806030
Short name T215
Test name
Test status
Simulation time 11023573 ps
CPU time 0.83 seconds
Started May 18 01:45:05 PM PDT 24
Finished May 18 01:45:07 PM PDT 24
Peak memory 204276 kb
Host smart-3398ace3-11a5-4dc8-8b09-64b718f9003f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280806030 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.3
280806030
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.3509185600
Short name T225
Test name
Test status
Simulation time 21783165 ps
CPU time 1.11 seconds
Started May 18 01:45:07 PM PDT 24
Finished May 18 01:45:09 PM PDT 24
Peak memory 204444 kb
Host smart-290fa753-8650-4783-b93b-01fc5882aae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509185600 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.3509185600
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.2099006924
Short name T180
Test name
Test status
Simulation time 77077562 ps
CPU time 1 seconds
Started May 18 01:44:57 PM PDT 24
Finished May 18 01:44:58 PM PDT 24
Peak memory 213020 kb
Host smart-c5913f01-bc11-4205-b7c2-281c9d6a9db1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099006924 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.2099006924
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3365393206
Short name T31
Test name
Test status
Simulation time 117984506 ps
CPU time 3.34 seconds
Started May 18 01:44:58 PM PDT 24
Finished May 18 01:45:03 PM PDT 24
Peak memory 213052 kb
Host smart-1a4ed3db-d192-4119-853d-c125c7eaecce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365393206 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3365393206
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.660308559
Short name T294
Test name
Test status
Simulation time 275162646 ps
CPU time 2 seconds
Started May 18 01:44:58 PM PDT 24
Finished May 18 01:45:01 PM PDT 24
Peak memory 212776 kb
Host smart-2487a71f-6969-4c38-aeba-a6a7bc9c094e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660308559 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.660308559
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.1254382200
Short name T277
Test name
Test status
Simulation time 33979577 ps
CPU time 1.4 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:09 PM PDT 24
Peak memory 220224 kb
Host smart-3ea9d4e8-127e-4487-b67d-7a62400a129a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254382200 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.1254382200
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.3809976884
Short name T231
Test name
Test status
Simulation time 8521499 ps
CPU time 0.98 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:09 PM PDT 24
Peak memory 204468 kb
Host smart-5f5f8f1f-de7a-430d-81bc-545b85aed77b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809976884 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.3
809976884
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.768859522
Short name T256
Test name
Test status
Simulation time 16051918 ps
CPU time 0.87 seconds
Started May 18 01:45:04 PM PDT 24
Finished May 18 01:45:06 PM PDT 24
Peak memory 204320 kb
Host smart-74a051a5-4920-459d-9714-f03fd7486968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768859522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.768859522
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.638106769
Short name T213
Test name
Test status
Simulation time 257755207 ps
CPU time 1.3 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:09 PM PDT 24
Peak memory 204440 kb
Host smart-b3574db4-291c-486d-8bef-cba62181d3d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638106769 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_dpe_same_csr_outstanding.638106769
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.556558799
Short name T274
Test name
Test status
Simulation time 43950403 ps
CPU time 1.77 seconds
Started May 18 01:45:05 PM PDT 24
Finished May 18 01:45:09 PM PDT 24
Peak memory 212968 kb
Host smart-065dc8cb-b694-4a5a-8ea5-733b71500da7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556558799 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymg
r_dpe_shadow_reg_errors.556558799
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3254666276
Short name T228
Test name
Test status
Simulation time 111305498 ps
CPU time 3.13 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:11 PM PDT 24
Peak memory 213040 kb
Host smart-ef5f8d6f-a1ca-4d87-912d-c9db6a079760
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254666276 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3254666276
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3557046537
Short name T44
Test name
Test status
Simulation time 379871167 ps
CPU time 2.75 seconds
Started May 18 01:45:05 PM PDT 24
Finished May 18 01:45:10 PM PDT 24
Peak memory 215080 kb
Host smart-bb91f406-d3ec-4c06-b50b-9b7afb0353e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557046537 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.3
557046537
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.1863223048
Short name T79
Test name
Test status
Simulation time 26588580 ps
CPU time 0.98 seconds
Started May 18 01:45:05 PM PDT 24
Finished May 18 01:45:08 PM PDT 24
Peak memory 204420 kb
Host smart-22b0ddbd-ebcd-4ee1-89d8-10e7ae7ee346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863223048 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.1863223048
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.3493510735
Short name T262
Test name
Test status
Simulation time 12820662 ps
CPU time 0.91 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:09 PM PDT 24
Peak memory 204456 kb
Host smart-649e320d-696b-4630-8778-981415a819d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493510735 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.3
493510735
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.3786730819
Short name T224
Test name
Test status
Simulation time 8850043 ps
CPU time 0.72 seconds
Started May 18 01:45:04 PM PDT 24
Finished May 18 01:45:06 PM PDT 24
Peak memory 204344 kb
Host smart-7800f618-7252-4cd8-ab50-7e93363f0f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786730819 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.3
786730819
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.52153096
Short name T71
Test name
Test status
Simulation time 356028562 ps
CPU time 2.98 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:11 PM PDT 24
Peak memory 204476 kb
Host smart-a40d51af-c4d1-4a2b-8733-59ac9ea3fc10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52153096 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=k
eymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.key
mgr_dpe_same_csr_outstanding.52153096
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.2251297651
Short name T267
Test name
Test status
Simulation time 145126833 ps
CPU time 2.5 seconds
Started May 18 01:45:07 PM PDT 24
Finished May 18 01:45:11 PM PDT 24
Peak memory 213088 kb
Host smart-ff4410bb-889e-4a1e-9ef7-66d84a9ec362
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251297651 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.2251297651
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.26222776
Short name T212
Test name
Test status
Simulation time 128782862 ps
CPU time 5.81 seconds
Started May 18 01:45:07 PM PDT 24
Finished May 18 01:45:15 PM PDT 24
Peak memory 213156 kb
Host smart-786c6041-ac5e-4962-8d53-cb4acfb23e39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.26222776
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.827936540
Short name T194
Test name
Test status
Simulation time 50266876 ps
CPU time 3 seconds
Started May 18 01:45:04 PM PDT 24
Finished May 18 01:45:08 PM PDT 24
Peak memory 220900 kb
Host smart-cc8ba3af-4475-4b45-bd90-6c338a3a0cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827936540 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.827936540
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1590512533
Short name T29
Test name
Test status
Simulation time 254517208 ps
CPU time 7.42 seconds
Started May 18 01:45:06 PM PDT 24
Finished May 18 01:45:15 PM PDT 24
Peak memory 213996 kb
Host smart-66693b71-b193-482b-a77a-a3717b418506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590512533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.1590512533
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.125995694
Short name T125
Test name
Test status
Simulation time 21786098 ps
CPU time 0.84 seconds
Started May 18 01:44:00 PM PDT 24
Finished May 18 01:44:03 PM PDT 24
Peak memory 205488 kb
Host smart-7dfc163f-f29d-478a-b708-7af69541672b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125995694 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.125995694
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.2567303863
Short name T7
Test name
Test status
Simulation time 1247630856 ps
CPU time 8.3 seconds
Started May 18 01:44:00 PM PDT 24
Finished May 18 01:44:10 PM PDT 24
Peak memory 230784 kb
Host smart-8f741056-4a02-4b8f-9df4-1156bd103b57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567303863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.2567303863
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.3283375102
Short name T76
Test name
Test status
Simulation time 1687808758 ps
CPU time 15.74 seconds
Started May 18 01:44:00 PM PDT 24
Finished May 18 01:44:18 PM PDT 24
Peak memory 206280 kb
Host smart-06d41542-9965-4e69-818c-0f244502099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283375102 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.3283375102
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.2982180378
Short name T135
Test name
Test status
Simulation time 12216726 ps
CPU time 0.84 seconds
Started May 18 01:43:58 PM PDT 24
Finished May 18 01:44:00 PM PDT 24
Peak memory 205436 kb
Host smart-b08d3619-b8b9-45b1-a3d4-26d9fd47ebf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982180378 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.2
982180378
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.778227726
Short name T78
Test name
Test status
Simulation time 1684418252 ps
CPU time 17.57 seconds
Started May 18 01:44:16 PM PDT 24
Finished May 18 01:44:37 PM PDT 24
Peak memory 206580 kb
Host smart-8d0f479a-9f66-4327-9f87-9127bebc8d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778227726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.778227726
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.2037814534
Short name T156
Test name
Test status
Simulation time 37332625 ps
CPU time 0.84 seconds
Started May 18 01:44:16 PM PDT 24
Finished May 18 01:44:20 PM PDT 24
Peak memory 205380 kb
Host smart-c4054c9f-f6b7-453a-9ced-d0064db30abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037814534 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
2037814534
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.1258127733
Short name T138
Test name
Test status
Simulation time 20986038 ps
CPU time 0.75 seconds
Started May 18 01:44:15 PM PDT 24
Finished May 18 01:44:19 PM PDT 24
Peak memory 205456 kb
Host smart-0afeb7ce-1b8d-47d5-8159-3eaa3d967c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258127733 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
1258127733
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.2921476958
Short name T144
Test name
Test status
Simulation time 1055168062 ps
CPU time 27.06 seconds
Started May 18 01:44:15 PM PDT 24
Finished May 18 01:44:46 PM PDT 24
Peak memory 207544 kb
Host smart-d572756a-5959-4ff9-a730-2d88b7edc838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921476958 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.2921476958
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.1538922978
Short name T118
Test name
Test status
Simulation time 10012190 ps
CPU time 0.82 seconds
Started May 18 01:44:17 PM PDT 24
Finished May 18 01:44:21 PM PDT 24
Peak memory 205452 kb
Host smart-27811b8f-c712-4a69-958e-1fb91b8532dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538922978 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
1538922978
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.227138643
Short name T13
Test name
Test status
Simulation time 3408812547 ps
CPU time 55.85 seconds
Started May 18 01:44:16 PM PDT 24
Finished May 18 01:45:16 PM PDT 24
Peak memory 207608 kb
Host smart-0cbf9369-d611-499b-b33b-1938aabf94e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227138643 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.227138643
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.635544123
Short name T130
Test name
Test status
Simulation time 246050946 ps
CPU time 0.95 seconds
Started May 18 01:44:16 PM PDT 24
Finished May 18 01:44:20 PM PDT 24
Peak memory 205416 kb
Host smart-f1439a7b-1c0e-48cd-99ef-b83b9b3dbf2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635544123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.635544123
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.4106068224
Short name T124
Test name
Test status
Simulation time 1764648363 ps
CPU time 17.85 seconds
Started May 18 01:44:15 PM PDT 24
Finished May 18 01:44:35 PM PDT 24
Peak memory 206100 kb
Host smart-ce74bebd-9840-4888-8003-1531e2aad876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106068224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.4106068224
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.1678165687
Short name T132
Test name
Test status
Simulation time 14559354 ps
CPU time 0.98 seconds
Started May 18 01:44:17 PM PDT 24
Finished May 18 01:44:21 PM PDT 24
Peak memory 205512 kb
Host smart-5e881608-8005-4f0a-bb88-42551cc2d139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678165687 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
1678165687
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.304350833
Short name T148
Test name
Test status
Simulation time 398922288 ps
CPU time 15.93 seconds
Started May 18 01:44:19 PM PDT 24
Finished May 18 01:44:38 PM PDT 24
Peak memory 207776 kb
Host smart-e5e11a3c-586b-4679-a05e-98e0a3829e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304350833 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.304350833
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.3439279722
Short name T150
Test name
Test status
Simulation time 48775492 ps
CPU time 0.91 seconds
Started May 18 01:44:16 PM PDT 24
Finished May 18 01:44:20 PM PDT 24
Peak memory 205528 kb
Host smart-a04797b7-b13b-4ebe-8300-46c8e07d7633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439279722 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
3439279722
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.2359846441
Short name T121
Test name
Test status
Simulation time 1334770059 ps
CPU time 25.84 seconds
Started May 18 01:44:17 PM PDT 24
Finished May 18 01:44:47 PM PDT 24
Peak memory 207448 kb
Host smart-c013b171-70ca-48d2-b645-c41890279981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359846441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.2359846441
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.1491657074
Short name T139
Test name
Test status
Simulation time 29326825 ps
CPU time 0.73 seconds
Started May 18 01:44:16 PM PDT 24
Finished May 18 01:44:21 PM PDT 24
Peak memory 205528 kb
Host smart-b58c7f9a-893c-4345-af29-23bb5bc47b24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491657074 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
1491657074
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.971716624
Short name T116
Test name
Test status
Simulation time 16061289 ps
CPU time 0.93 seconds
Started May 18 01:44:15 PM PDT 24
Finished May 18 01:44:18 PM PDT 24
Peak memory 205624 kb
Host smart-d2cd53a7-543d-436f-a36d-0d922b538519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971716624 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.971716624
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.976474858
Short name T120
Test name
Test status
Simulation time 54708806 ps
CPU time 0.93 seconds
Started May 18 01:44:16 PM PDT 24
Finished May 18 01:44:20 PM PDT 24
Peak memory 205684 kb
Host smart-e756e2fc-7ce4-4828-ad6a-f59bd44d9931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976474858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.976474858
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.187551796
Short name T142
Test name
Test status
Simulation time 43566043 ps
CPU time 0.73 seconds
Started May 18 01:44:00 PM PDT 24
Finished May 18 01:44:02 PM PDT 24
Peak memory 205436 kb
Host smart-52ff1c1c-827e-4188-9bf9-b9bff0aca1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187551796 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.187551796
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.3279202926
Short name T22
Test name
Test status
Simulation time 1420595526 ps
CPU time 11.61 seconds
Started May 18 01:44:00 PM PDT 24
Finished May 18 01:44:13 PM PDT 24
Peak memory 234116 kb
Host smart-6e39117c-a71e-4a7f-a3c1-c6a33fa79e7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279202926 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.3279202926
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.1534696247
Short name T153
Test name
Test status
Simulation time 23386195 ps
CPU time 0.76 seconds
Started May 18 01:44:17 PM PDT 24
Finished May 18 01:44:21 PM PDT 24
Peak memory 205492 kb
Host smart-84d74490-06c0-4228-8ae9-90dfe1dd4f56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534696247 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
1534696247
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.358472699
Short name T12
Test name
Test status
Simulation time 2030137962 ps
CPU time 18.4 seconds
Started May 18 01:44:14 PM PDT 24
Finished May 18 01:44:34 PM PDT 24
Peak memory 208536 kb
Host smart-91f7db0f-73ce-4699-a601-e7f9a45efc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358472699 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.358472699
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.1455620646
Short name T154
Test name
Test status
Simulation time 18638464 ps
CPU time 0.79 seconds
Started May 18 01:44:17 PM PDT 24
Finished May 18 01:44:21 PM PDT 24
Peak memory 205456 kb
Host smart-e246a900-4beb-4e26-83c5-baa47502ecfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455620646 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
1455620646
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.3975440264
Short name T109
Test name
Test status
Simulation time 449215823 ps
CPU time 14.5 seconds
Started May 18 01:44:15 PM PDT 24
Finished May 18 01:44:33 PM PDT 24
Peak memory 207288 kb
Host smart-03444d2e-29ed-4ab9-8499-455320547322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975440264 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.3975440264
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.2560105862
Short name T151
Test name
Test status
Simulation time 14597772 ps
CPU time 0.75 seconds
Started May 18 01:44:18 PM PDT 24
Finished May 18 01:44:22 PM PDT 24
Peak memory 205512 kb
Host smart-4ddd73a4-26e7-4a7e-a966-d82a2c2beb55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560105862 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
2560105862
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.3773284484
Short name T115
Test name
Test status
Simulation time 310815479 ps
CPU time 13.42 seconds
Started May 18 01:44:18 PM PDT 24
Finished May 18 01:44:34 PM PDT 24
Peak memory 206612 kb
Host smart-1335c8bb-a271-4282-ac4e-9c3f9cd937de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773284484 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.3773284484
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.3881282056
Short name T16
Test name
Test status
Simulation time 27721083 ps
CPU time 0.71 seconds
Started May 18 01:44:25 PM PDT 24
Finished May 18 01:44:27 PM PDT 24
Peak memory 205532 kb
Host smart-e1e43b38-29d1-40c6-aeb8-d8a878158e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881282056 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
3881282056
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.1892929522
Short name T134
Test name
Test status
Simulation time 13351581 ps
CPU time 0.75 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:29 PM PDT 24
Peak memory 205472 kb
Host smart-968df08e-7ea0-4b89-a6c8-334ed27ce757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892929522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
1892929522
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.2961187786
Short name T114
Test name
Test status
Simulation time 12690589 ps
CPU time 0.91 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:30 PM PDT 24
Peak memory 205464 kb
Host smart-97951b30-e355-4c89-b367-fc5242a41e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961187786 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
2961187786
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.4124722426
Short name T160
Test name
Test status
Simulation time 41112420 ps
CPU time 0.75 seconds
Started May 18 01:44:27 PM PDT 24
Finished May 18 01:44:31 PM PDT 24
Peak memory 205464 kb
Host smart-415c4c5f-2c5f-49d9-90d6-080ea4d48424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124722426 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
4124722426
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.1799591558
Short name T102
Test name
Test status
Simulation time 330536287 ps
CPU time 12.79 seconds
Started May 18 01:44:31 PM PDT 24
Finished May 18 01:44:46 PM PDT 24
Peak memory 206388 kb
Host smart-0d7dc756-f238-4d53-bffa-535466fd64a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799591558 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.1799591558
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.2429535555
Short name T145
Test name
Test status
Simulation time 34731495 ps
CPU time 0.84 seconds
Started May 18 01:44:25 PM PDT 24
Finished May 18 01:44:27 PM PDT 24
Peak memory 205520 kb
Host smart-a9c633d5-235a-4af0-a1ba-d423c570ff1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429535555 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
2429535555
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.260563613
Short name T70
Test name
Test status
Simulation time 8905220264 ps
CPU time 64.56 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:45:34 PM PDT 24
Peak memory 208324 kb
Host smart-19aa88a8-c5d0-4793-866a-8ea12188f4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260563613 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.260563613
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.3598848120
Short name T158
Test name
Test status
Simulation time 25593523 ps
CPU time 0.77 seconds
Started May 18 01:44:23 PM PDT 24
Finished May 18 01:44:25 PM PDT 24
Peak memory 205528 kb
Host smart-4836ce94-4ab3-4113-aca3-9acc99703fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598848120 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
3598848120
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.2427162645
Short name T110
Test name
Test status
Simulation time 11376405 ps
CPU time 0.78 seconds
Started May 18 01:44:28 PM PDT 24
Finished May 18 01:44:31 PM PDT 24
Peak memory 205512 kb
Host smart-5eb95c71-16fc-45f8-9332-5bc155fd6956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427162645 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
2427162645
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.3206470721
Short name T143
Test name
Test status
Simulation time 28580371694 ps
CPU time 139.9 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:46:49 PM PDT 24
Peak memory 208812 kb
Host smart-246f7e50-8f80-405b-972d-c1eba388270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206470721 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.3206470721
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.1305582254
Short name T67
Test name
Test status
Simulation time 58970231 ps
CPU time 0.87 seconds
Started May 18 01:44:07 PM PDT 24
Finished May 18 01:44:08 PM PDT 24
Peak memory 205396 kb
Host smart-9706b598-8663-475c-a50a-c8ca9e68b63d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305582254 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.1
305582254
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.2713155983
Short name T21
Test name
Test status
Simulation time 1984518386 ps
CPU time 9.96 seconds
Started May 18 01:44:08 PM PDT 24
Finished May 18 01:44:20 PM PDT 24
Peak memory 230248 kb
Host smart-96eeb0aa-e54b-4d3e-8c45-5690a75d69a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713155983 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.2713155983
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.2011065529
Short name T112
Test name
Test status
Simulation time 13623594 ps
CPU time 0.73 seconds
Started May 18 01:44:24 PM PDT 24
Finished May 18 01:44:26 PM PDT 24
Peak memory 205464 kb
Host smart-ab1e3c8f-dcdf-46c5-be51-eda895c82ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011065529 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
2011065529
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.3026666805
Short name T123
Test name
Test status
Simulation time 24707627 ps
CPU time 0.9 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:29 PM PDT 24
Peak memory 205504 kb
Host smart-64e71bc6-f84d-403c-a4b4-425ea519a4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026666805 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
3026666805
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.3452094677
Short name T133
Test name
Test status
Simulation time 16278054 ps
CPU time 0.76 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:29 PM PDT 24
Peak memory 205352 kb
Host smart-049c49ee-9c04-4f5c-9ff6-3ec6c2bcf683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452094677 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
3452094677
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.2269626658
Short name T146
Test name
Test status
Simulation time 7942249945 ps
CPU time 39.25 seconds
Started May 18 01:44:28 PM PDT 24
Finished May 18 01:45:10 PM PDT 24
Peak memory 207716 kb
Host smart-61567a90-4423-4b71-89e7-fbc4d16062fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269626658 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.2269626658
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.2749166164
Short name T108
Test name
Test status
Simulation time 10574278 ps
CPU time 0.73 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:28 PM PDT 24
Peak memory 205400 kb
Host smart-b16c8652-be1a-4785-b695-b0caa4b5dbca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749166164 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
2749166164
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.2942239221
Short name T8
Test name
Test status
Simulation time 269696767 ps
CPU time 14 seconds
Started May 18 01:44:25 PM PDT 24
Finished May 18 01:44:41 PM PDT 24
Peak memory 208208 kb
Host smart-d11be57a-6cdb-48fd-ac51-0f15917730ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942239221 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.2942239221
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.2502109278
Short name T128
Test name
Test status
Simulation time 20822504 ps
CPU time 0.76 seconds
Started May 18 01:44:27 PM PDT 24
Finished May 18 01:44:31 PM PDT 24
Peak memory 205480 kb
Host smart-5a190ce1-6d0b-4feb-93c8-06e5958fb027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502109278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
2502109278
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.3892044617
Short name T98
Test name
Test status
Simulation time 584973171 ps
CPU time 10.56 seconds
Started May 18 01:44:25 PM PDT 24
Finished May 18 01:44:38 PM PDT 24
Peak memory 206792 kb
Host smart-b8539153-b4a5-49d1-bb93-86526cd595b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892044617 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.3892044617
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.260499998
Short name T23
Test name
Test status
Simulation time 50173089 ps
CPU time 0.81 seconds
Started May 18 01:44:27 PM PDT 24
Finished May 18 01:44:31 PM PDT 24
Peak memory 205452 kb
Host smart-15475a1e-6b73-49da-bc3e-b5deaad14536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260499998 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.260499998
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.588777794
Short name T152
Test name
Test status
Simulation time 39600909 ps
CPU time 0.82 seconds
Started May 18 01:44:24 PM PDT 24
Finished May 18 01:44:26 PM PDT 24
Peak memory 205528 kb
Host smart-7fdc41b9-2232-4fab-ac1b-9ecadc62154b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588777794 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.588777794
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.1257170929
Short name T159
Test name
Test status
Simulation time 3590280388 ps
CPU time 27.53 seconds
Started May 18 01:44:31 PM PDT 24
Finished May 18 01:45:01 PM PDT 24
Peak memory 206764 kb
Host smart-a4167a02-0a78-47a7-b5b8-e26f68b20dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257170929 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.1257170929
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.1789844711
Short name T161
Test name
Test status
Simulation time 20092210 ps
CPU time 0.8 seconds
Started May 18 01:44:27 PM PDT 24
Finished May 18 01:44:30 PM PDT 24
Peak memory 205456 kb
Host smart-5c242779-5385-40e8-93cb-9302fb2bda08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789844711 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
1789844711
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.2343027455
Short name T100
Test name
Test status
Simulation time 1614417178 ps
CPU time 14.78 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:44 PM PDT 24
Peak memory 208248 kb
Host smart-6f18cc14-b0b0-4ea8-9201-cc48232173f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343027455 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.2343027455
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.2282978840
Short name T162
Test name
Test status
Simulation time 18337708 ps
CPU time 0.91 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:30 PM PDT 24
Peak memory 205664 kb
Host smart-16c8bcc6-b4fb-4dc6-94cd-f0f532b20e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282978840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
2282978840
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.3283821809
Short name T75
Test name
Test status
Simulation time 980209269 ps
CPU time 15.29 seconds
Started May 18 01:44:26 PM PDT 24
Finished May 18 01:44:43 PM PDT 24
Peak memory 208556 kb
Host smart-0910bbd3-1274-4408-bb61-fd6344813aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283821809 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.3283821809
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.812258215
Short name T107
Test name
Test status
Simulation time 26899551 ps
CPU time 1.07 seconds
Started May 18 01:44:27 PM PDT 24
Finished May 18 01:44:31 PM PDT 24
Peak memory 205704 kb
Host smart-8f48650b-5eb1-420b-8f79-34a1c461cb29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812258215 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.812258215
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.3269112196
Short name T149
Test name
Test status
Simulation time 979024405 ps
CPU time 17.68 seconds
Started May 18 01:44:25 PM PDT 24
Finished May 18 01:44:44 PM PDT 24
Peak memory 206348 kb
Host smart-4d5aca4d-b631-4e16-8c2e-5759014e5c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269112196 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.3269112196
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.38649873
Short name T1
Test name
Test status
Simulation time 45171204 ps
CPU time 0.82 seconds
Started May 18 01:44:09 PM PDT 24
Finished May 18 01:44:12 PM PDT 24
Peak memory 205540 kb
Host smart-2ec6533a-a370-4def-9a9c-e44e19aa4e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649873 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.38649873
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.1603446533
Short name T157
Test name
Test status
Simulation time 13120796 ps
CPU time 0.91 seconds
Started May 18 01:44:24 PM PDT 24
Finished May 18 01:44:26 PM PDT 24
Peak memory 205492 kb
Host smart-6bd0dc57-bd9b-4600-a690-1d740be456cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603446533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
1603446533
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.3161111091
Short name T155
Test name
Test status
Simulation time 10268630120 ps
CPU time 47.81 seconds
Started May 18 01:44:24 PM PDT 24
Finished May 18 01:45:12 PM PDT 24
Peak memory 208044 kb
Host smart-b9c1bcca-5b29-4fff-aea8-55ef8ae998cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161111091 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.3161111091
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.2980065261
Short name T131
Test name
Test status
Simulation time 23239041 ps
CPU time 0.76 seconds
Started May 18 01:44:34 PM PDT 24
Finished May 18 01:44:37 PM PDT 24
Peak memory 205536 kb
Host smart-8f0a1408-6073-4856-80b7-93a98365c054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980065261 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
2980065261
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.2650819466
Short name T147
Test name
Test status
Simulation time 8368357 ps
CPU time 0.83 seconds
Started May 18 01:44:32 PM PDT 24
Finished May 18 01:44:35 PM PDT 24
Peak memory 205532 kb
Host smart-8d8e9e9a-9b66-489c-916e-9e559e606e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650819466 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
2650819466
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.3504189440
Short name T141
Test name
Test status
Simulation time 115788591 ps
CPU time 0.78 seconds
Started May 18 01:44:31 PM PDT 24
Finished May 18 01:44:33 PM PDT 24
Peak memory 205508 kb
Host smart-bf7a5fa0-a849-49ef-b4f4-a08ad6f65b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504189440 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
3504189440
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.3313263555
Short name T99
Test name
Test status
Simulation time 7489712868 ps
CPU time 97.26 seconds
Started May 18 01:44:32 PM PDT 24
Finished May 18 01:46:11 PM PDT 24
Peak memory 208404 kb
Host smart-0e9efa45-67dc-48fa-b301-f0b2f866011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313263555 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.3313263555
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.2903718981
Short name T122
Test name
Test status
Simulation time 147862199 ps
CPU time 1.11 seconds
Started May 18 01:44:34 PM PDT 24
Finished May 18 01:44:37 PM PDT 24
Peak memory 205684 kb
Host smart-f8fff6a0-986f-4422-ae2b-9019ca659192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903718981 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
2903718981
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.4027978140
Short name T103
Test name
Test status
Simulation time 659759727 ps
CPU time 18.56 seconds
Started May 18 01:44:32 PM PDT 24
Finished May 18 01:44:52 PM PDT 24
Peak memory 207956 kb
Host smart-3332e07c-bcad-40ef-bd69-7646478e6e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027978140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.4027978140
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.1221370356
Short name T140
Test name
Test status
Simulation time 9691764 ps
CPU time 0.85 seconds
Started May 18 01:44:33 PM PDT 24
Finished May 18 01:44:36 PM PDT 24
Peak memory 205432 kb
Host smart-22c87196-ecd3-48a0-b855-d1183bf93108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221370356 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
1221370356
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.540907299
Short name T17
Test name
Test status
Simulation time 19396721 ps
CPU time 0.98 seconds
Started May 18 01:44:34 PM PDT 24
Finished May 18 01:44:37 PM PDT 24
Peak memory 205684 kb
Host smart-d95da284-aadc-4d26-8630-8f1b6a08c5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540907299 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.540907299
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.1942897794
Short name T113
Test name
Test status
Simulation time 16030653 ps
CPU time 0.74 seconds
Started May 18 01:44:33 PM PDT 24
Finished May 18 01:44:35 PM PDT 24
Peak memory 205528 kb
Host smart-e33bbe17-4c1e-48ed-9515-60d1170186c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942897794 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
1942897794
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.2478886567
Short name T11
Test name
Test status
Simulation time 498876452 ps
CPU time 17.23 seconds
Started May 18 01:44:33 PM PDT 24
Finished May 18 01:44:52 PM PDT 24
Peak memory 208508 kb
Host smart-c05a0618-07c1-454b-a972-76973196f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478886567 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.2478886567
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.188287769
Short name T126
Test name
Test status
Simulation time 12021595 ps
CPU time 0.75 seconds
Started May 18 01:44:31 PM PDT 24
Finished May 18 01:44:34 PM PDT 24
Peak memory 205416 kb
Host smart-1de70b05-8b0c-43aa-8f36-f4c47f7d5804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188287769 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.188287769
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.2013045570
Short name T136
Test name
Test status
Simulation time 2292080701 ps
CPU time 21.29 seconds
Started May 18 01:44:35 PM PDT 24
Finished May 18 01:44:58 PM PDT 24
Peak memory 207392 kb
Host smart-28b99b3e-acb2-4f59-a43c-3bb793ff66a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013045570 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.2013045570
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.318919862
Short name T106
Test name
Test status
Simulation time 185665475 ps
CPU time 0.85 seconds
Started May 18 01:44:32 PM PDT 24
Finished May 18 01:44:35 PM PDT 24
Peak memory 205544 kb
Host smart-647a79d9-f9e9-4832-aa5c-f1c45d1c2080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318919862 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.318919862
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.2525611261
Short name T2
Test name
Test status
Simulation time 948397409 ps
CPU time 18.13 seconds
Started May 18 01:44:33 PM PDT 24
Finished May 18 01:44:53 PM PDT 24
Peak memory 208408 kb
Host smart-75819aac-fb77-400a-b712-11cffde12d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525611261 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.2525611261
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.3006462439
Short name T127
Test name
Test status
Simulation time 10572307 ps
CPU time 0.85 seconds
Started May 18 01:44:12 PM PDT 24
Finished May 18 01:44:16 PM PDT 24
Peak memory 205372 kb
Host smart-2ef9b533-3caa-4268-bc3e-4e1aac390a3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006462439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.3
006462439
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.3122630694
Short name T117
Test name
Test status
Simulation time 58422465 ps
CPU time 0.96 seconds
Started May 18 01:44:08 PM PDT 24
Finished May 18 01:44:10 PM PDT 24
Peak memory 205684 kb
Host smart-222cc743-6df7-4588-9e2f-a853b014a9a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122630694 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.3
122630694
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.1223286082
Short name T119
Test name
Test status
Simulation time 546433046 ps
CPU time 16.94 seconds
Started May 18 01:44:12 PM PDT 24
Finished May 18 01:44:31 PM PDT 24
Peak memory 207440 kb
Host smart-dbb0648f-034e-4d4c-aea7-dd8556860e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223286082 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.1223286082
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.1107705785
Short name T15
Test name
Test status
Simulation time 64132994 ps
CPU time 1 seconds
Started May 18 01:44:09 PM PDT 24
Finished May 18 01:44:11 PM PDT 24
Peak memory 205640 kb
Host smart-4ffe550c-7e6a-4afd-a2dc-8cbccbcf22a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107705785 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.1
107705785
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.2432321808
Short name T69
Test name
Test status
Simulation time 2357593786 ps
CPU time 20.19 seconds
Started May 18 01:44:12 PM PDT 24
Finished May 18 01:44:35 PM PDT 24
Peak memory 207356 kb
Host smart-ede67847-02d3-48f3-a788-0f0fe70824f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432321808 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.2432321808
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.3991623988
Short name T137
Test name
Test status
Simulation time 25769508 ps
CPU time 0.85 seconds
Started May 18 01:44:10 PM PDT 24
Finished May 18 01:44:13 PM PDT 24
Peak memory 205528 kb
Host smart-0e4586f0-0884-47c3-830a-f0e43be6eec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991623988 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.3
991623988
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.3337339579
Short name T25
Test name
Test status
Simulation time 2763897884 ps
CPU time 20.41 seconds
Started May 18 01:44:10 PM PDT 24
Finished May 18 01:44:32 PM PDT 24
Peak memory 206484 kb
Host smart-db710e19-652f-466f-9e4e-3aa94d001e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337339579 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.3337339579
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.1965779081
Short name T111
Test name
Test status
Simulation time 31560937 ps
CPU time 0.71 seconds
Started May 18 01:44:14 PM PDT 24
Finished May 18 01:44:18 PM PDT 24
Peak memory 205528 kb
Host smart-7719e836-e081-4b0f-afd5-97c61efccf92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965779081 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.1
965779081
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.3504911944
Short name T129
Test name
Test status
Simulation time 1169052863 ps
CPU time 19.51 seconds
Started May 18 01:44:13 PM PDT 24
Finished May 18 01:44:34 PM PDT 24
Peak memory 208208 kb
Host smart-14604e88-1246-4b0b-860b-fb0aeea81b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504911944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.3504911944
Directory /workspace/9.keymgr_dpe_smoke/latest
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