Unified Coverage Report :: Group :: keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

Group : keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
17.51	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv

---

Summary for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	17	4	13	76.47
Crosses	240	208	32	13.33

Variables for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	1	1	50.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	1	4	80.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	4	2	2	50.00	100	1	1	0

Crosses for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	160	144	16	10.00	100	1	1	0
op_x_status_cross	80	64	16	20.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cdi_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[Attestation]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

6645

1

T2

130

T3

123

T4

135

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	1655	1			T2	31		T3	29		T4	30
auto[Aes]	1699	1			T2	31		T3	37		T4	25
auto[Kmac]	1687	1			T2	36		T3	29		T4	52
auto[Otbn]	1604	1			T2	32		T3	28		T4	28

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDpeErase]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpDpeAdvance]	1515	1			T2	33		T3	29		T4	29
auto[OpDpeGenSwOut]	3325	1			T2	68		T3	58		T4	67
auto[OpDpeGenHwOut]	3320	1			T2	62		T3	65		T4	68
auto[OpDpeDisable]	98	1			T2	2		T3	2		T4	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

3573

1

T2

102

T3

48

T4

79

auto[OpDoneFail]

4685

1

T2

63

T3

106

T4

87

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	2	2	50.00

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StWorkDpeDisabled]	0	1	1
auto[StWorkDpeInvalid]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[StWorkDpeReset]

287

1

T2

2

T3

13

T4

9

auto[StWorkDpeAvailable]

7971

1

T2

163

T3

141

T4

157

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	160	144	16	10.00	144

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	64
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Sealing]]	*	[auto[StWorkDpeDisabled] , auto[StWorkDpeInvalid]]	--	--	16
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	32
[auto[OpDpeDisable]]	*	*	*	--	--	32

Covered bins

op_cp

cdi_cp

dest_cp

state_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

20

1

T4

1

T8

3

T110

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

811

1

T2

21

T3

15

T4

14

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

17

1

T3

2

T10

2

T100

2

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

823

1

T2

14

T3

17

T4

11

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

25

1

T3

1

T8

2

T98

5

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

829

1

T2

14

T3

12

T4

28

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

22

1

T3

1

T4

1

T8

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

778

1

T2

19

T3

10

T4

12

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

26

1

T3

4

T4

1

T8

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

798

1

T2

10

T3

10

T4

14

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

24

1

T3

2

T4

2

T98

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

835

1

T2

17

T3

16

T4

12

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

24

1

T4

1

T10

2

T98

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

809

1

T2

22

T3

16

T4

23

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

31

1

T3

1

T4

1

T110

3

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

773

1

T2

13

T3

16

T4

14

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	64	16	20.00	64

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	32
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	16
[auto[OpDpeDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase] , auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut] , auto[OpDpeDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp

cdi_cp

dest_cp

op_status_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

399

1

T2

15

T3

7

T4

8

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

432

1

T2

6

T3

8

T4

7

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

361

1

T2

7

T3

3

T4

4

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

479

1

T2

7

T3

16

T4

7

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

384

1

T2

9

T3

5

T4

15

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

470

1

T2

5

T3

8

T4

13

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

368

1

T2

15

T3

2

T4

5

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

432

1

T2

4

T3

9

T4

8

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

419

1

T2

8

T3

3

T4

9

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

405

1

T2

2

T3

11

T4

6

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

393

1

T2

10

T3

5

T4

8

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

466

1

T2

7

T3

13

T4

6

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

400

1

T2

18

T3

5

T4

10

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

433

1

T2

4

T3

11

T4

14

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

381

1

T2

10

T3

8

T4

10

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

423

1

T2

3

T3

9

T4

5