Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.24 97.60 90.55 57.52 76.92 94.97 98.34 17.82


Total test records in report: 309
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T255 /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.4037615284 May 25 01:53:10 PM PDT 24 May 25 01:53:14 PM PDT 24 470194121 ps
T256 /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.483209048 May 25 01:53:17 PM PDT 24 May 25 01:53:19 PM PDT 24 21707029 ps
T257 /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.3755172596 May 25 01:52:50 PM PDT 24 May 25 01:52:52 PM PDT 24 47974118 ps
T258 /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.3995032536 May 25 01:53:10 PM PDT 24 May 25 01:53:12 PM PDT 24 14834072 ps
T259 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.4153049570 May 25 01:53:11 PM PDT 24 May 25 01:53:15 PM PDT 24 90813696 ps
T260 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1880343056 May 25 01:53:15 PM PDT 24 May 25 01:53:17 PM PDT 24 102891095 ps
T261 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2942602649 May 25 01:53:10 PM PDT 24 May 25 01:53:12 PM PDT 24 22497322 ps
T262 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1100739188 May 25 01:53:10 PM PDT 24 May 25 01:53:16 PM PDT 24 142387388 ps
T263 /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.8011435 May 25 01:53:17 PM PDT 24 May 25 01:53:20 PM PDT 24 39650044 ps
T264 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.815512030 May 25 01:52:54 PM PDT 24 May 25 01:52:57 PM PDT 24 150921356 ps
T265 /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.785937480 May 25 01:53:09 PM PDT 24 May 25 01:53:11 PM PDT 24 230002357 ps
T266 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.128471599 May 25 01:52:48 PM PDT 24 May 25 01:53:02 PM PDT 24 3438343899 ps
T267 /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2519004435 May 25 01:53:11 PM PDT 24 May 25 01:53:14 PM PDT 24 90862911 ps
T268 /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.3739751189 May 25 01:53:10 PM PDT 24 May 25 01:53:14 PM PDT 24 333952056 ps
T269 /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2053795869 May 25 01:53:10 PM PDT 24 May 25 01:53:14 PM PDT 24 190191365 ps
T62 /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.888478681 May 25 01:52:46 PM PDT 24 May 25 01:52:51 PM PDT 24 115932557 ps
T270 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3180743826 May 25 01:53:11 PM PDT 24 May 25 01:53:13 PM PDT 24 21531275 ps
T271 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1820747067 May 25 01:53:14 PM PDT 24 May 25 01:53:18 PM PDT 24 400536418 ps
T272 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.673799428 May 25 01:52:47 PM PDT 24 May 25 01:52:54 PM PDT 24 878088441 ps
T273 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.2052003599 May 25 01:53:19 PM PDT 24 May 25 01:53:21 PM PDT 24 11390032 ps
T274 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.47009479 May 25 01:52:51 PM PDT 24 May 25 01:53:02 PM PDT 24 1190797197 ps
T275 /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.3023963798 May 25 01:52:54 PM PDT 24 May 25 01:52:56 PM PDT 24 77637555 ps
T276 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.4112777483 May 25 01:53:12 PM PDT 24 May 25 01:53:17 PM PDT 24 279027589 ps
T277 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2642569246 May 25 01:52:45 PM PDT 24 May 25 01:52:48 PM PDT 24 43848411 ps
T278 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.4167050115 May 25 01:52:54 PM PDT 24 May 25 01:52:55 PM PDT 24 33385778 ps
T279 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.3623637601 May 25 01:53:10 PM PDT 24 May 25 01:53:12 PM PDT 24 25968641 ps
T280 /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1280426968 May 25 01:53:10 PM PDT 24 May 25 01:53:14 PM PDT 24 142451914 ps
T281 /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2858934085 May 25 01:52:51 PM PDT 24 May 25 01:52:54 PM PDT 24 47161628 ps
T282 /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.4242333303 May 25 01:53:15 PM PDT 24 May 25 01:53:18 PM PDT 24 14711201 ps
T283 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.3887816159 May 25 01:52:51 PM PDT 24 May 25 01:52:54 PM PDT 24 47568406 ps
T284 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.453789546 May 25 01:52:47 PM PDT 24 May 25 01:52:48 PM PDT 24 43457929 ps
T53 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.641829287 May 25 01:53:06 PM PDT 24 May 25 01:53:15 PM PDT 24 3661760472 ps
T285 /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.907790352 May 25 01:53:13 PM PDT 24 May 25 01:53:16 PM PDT 24 44223166 ps
T286 /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.3326090440 May 25 01:53:11 PM PDT 24 May 25 01:53:13 PM PDT 24 47376533 ps
T287 /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.2646844944 May 25 01:53:20 PM PDT 24 May 25 01:53:22 PM PDT 24 8756607 ps
T288 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2790692045 May 25 01:53:14 PM PDT 24 May 25 01:53:16 PM PDT 24 92465330 ps
T289 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.2823809076 May 25 01:53:12 PM PDT 24 May 25 01:53:16 PM PDT 24 649127316 ps
T290 /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.2676393089 May 25 01:53:19 PM PDT 24 May 25 01:53:22 PM PDT 24 15310258 ps
T291 /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.3302672722 May 25 01:53:10 PM PDT 24 May 25 01:53:13 PM PDT 24 64587094 ps
T292 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1742632938 May 25 01:53:14 PM PDT 24 May 25 01:53:16 PM PDT 24 12918594 ps
T51 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.1616193495 May 25 01:52:39 PM PDT 24 May 25 01:52:45 PM PDT 24 463119152 ps
T293 /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.1521711454 May 25 01:52:47 PM PDT 24 May 25 01:52:48 PM PDT 24 14873708 ps
T294 /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.200612198 May 25 01:52:50 PM PDT 24 May 25 01:52:52 PM PDT 24 150962818 ps
T295 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.3784994733 May 25 01:53:18 PM PDT 24 May 25 01:53:23 PM PDT 24 1252341590 ps
T296 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.681612604 May 25 01:52:39 PM PDT 24 May 25 01:52:42 PM PDT 24 80282995 ps
T297 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.1528901243 May 25 01:52:55 PM PDT 24 May 25 01:52:57 PM PDT 24 26241754 ps
T298 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.1952033545 May 25 01:53:11 PM PDT 24 May 25 01:53:13 PM PDT 24 180012635 ps
T299 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1222436292 May 25 01:53:14 PM PDT 24 May 25 01:53:17 PM PDT 24 325160431 ps
T300 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.320714050 May 25 01:52:49 PM PDT 24 May 25 01:52:54 PM PDT 24 795084784 ps
T301 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.4136112143 May 25 01:52:51 PM PDT 24 May 25 01:52:53 PM PDT 24 12032146 ps
T302 /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3458413604 May 25 01:53:18 PM PDT 24 May 25 01:53:20 PM PDT 24 29581962 ps
T63 /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.4042045286 May 25 01:53:13 PM PDT 24 May 25 01:53:18 PM PDT 24 312376642 ps
T303 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.3820879348 May 25 01:52:47 PM PDT 24 May 25 01:52:49 PM PDT 24 55440249 ps
T304 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.2433509075 May 25 01:52:51 PM PDT 24 May 25 01:52:53 PM PDT 24 56097725 ps
T305 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.1843528820 May 25 01:52:53 PM PDT 24 May 25 01:52:58 PM PDT 24 327361967 ps
T306 /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.1961521302 May 25 01:53:16 PM PDT 24 May 25 01:53:18 PM PDT 24 20906253 ps
T307 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3168236216 May 25 01:53:11 PM PDT 24 May 25 01:53:20 PM PDT 24 841635443 ps
T308 /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.1997560524 May 25 01:52:55 PM PDT 24 May 25 01:52:58 PM PDT 24 376418643 ps
T309 /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.540645477 May 25 01:52:56 PM PDT 24 May 25 01:53:01 PM PDT 24 486487526 ps

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.2756860416
Short name T10
Test name
Test status
Simulation time 1391099732 ps
CPU time 16.02 seconds
Started May 25 01:02:18 PM PDT 24
Finished May 25 01:02:35 PM PDT 24
Peak memory 208132 kb
Host smart-3d4c5445-a186-4e2f-9713-600dfd0eb48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756860416 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.2756860416
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.3060395923
Short name T20
Test name
Test status
Simulation time 387001178 ps
CPU time 3.33 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:53:00 PM PDT 24
Peak memory 212736 kb
Host smart-a120a29f-b424-4ad2-8bed-5eddd24d78b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060395923 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.3060395923
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.1401398931
Short name T6
Test name
Test status
Simulation time 555868651 ps
CPU time 9.39 seconds
Started May 25 01:02:06 PM PDT 24
Finished May 25 01:02:16 PM PDT 24
Peak memory 229436 kb
Host smart-b3d96ed7-6ea9-4ea1-bba8-29dcbb4abd3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401398931 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.1401398931
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.3567502276
Short name T39
Test name
Test status
Simulation time 2456745676 ps
CPU time 3.32 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 212820 kb
Host smart-805ffcd2-60b5-4fea-9139-7f45144a7fad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567502276 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.3
567502276
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.387046230
Short name T38
Test name
Test status
Simulation time 450756955 ps
CPU time 4.99 seconds
Started May 25 01:52:39 PM PDT 24
Finished May 25 01:52:45 PM PDT 24
Peak memory 212968 kb
Host smart-7a83f35f-650d-45de-b3c5-0c5a8585dd1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387046230 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.387046230
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.3674431488
Short name T11
Test name
Test status
Simulation time 536985230 ps
CPU time 13.75 seconds
Started May 25 01:02:17 PM PDT 24
Finished May 25 01:02:31 PM PDT 24
Peak memory 207796 kb
Host smart-2424954e-c829-4f44-8dac-9a2a7e5b619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674431488 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.3674431488
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.2895773566
Short name T68
Test name
Test status
Simulation time 9726731 ps
CPU time 0.74 seconds
Started May 25 01:02:17 PM PDT 24
Finished May 25 01:02:19 PM PDT 24
Peak memory 205492 kb
Host smart-660a6501-d3e3-4a34-b600-8df792d0cdcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895773566 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
2895773566
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.517437771
Short name T131
Test name
Test status
Simulation time 19368261 ps
CPU time 0.8 seconds
Started May 25 01:53:17 PM PDT 24
Finished May 25 01:53:19 PM PDT 24
Peak memory 204232 kb
Host smart-8c3d771b-8220-4781-9513-23abfd452505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517437771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.517437771
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.920491453
Short name T98
Test name
Test status
Simulation time 449796806 ps
CPU time 9.95 seconds
Started May 25 01:02:29 PM PDT 24
Finished May 25 01:02:39 PM PDT 24
Peak memory 208480 kb
Host smart-fe3b377a-6700-4204-8e39-920bf3146846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920491453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.920491453
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.3037621184
Short name T59
Test name
Test status
Simulation time 327639689 ps
CPU time 3.56 seconds
Started May 25 01:52:45 PM PDT 24
Finished May 25 01:52:49 PM PDT 24
Peak memory 212720 kb
Host smart-e9a6c16a-ad1c-4dc5-bd2e-a9549d47c4f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037621184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.3037621184
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1983604235
Short name T52
Test name
Test status
Simulation time 126524211 ps
CPU time 4.45 seconds
Started May 25 01:53:15 PM PDT 24
Finished May 25 01:53:21 PM PDT 24
Peak memory 212580 kb
Host smart-f70d2170-55ea-4f81-b3e2-fe6feda674f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983604235 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.1983604235
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.1235125834
Short name T46
Test name
Test status
Simulation time 924716646 ps
CPU time 7.42 seconds
Started May 25 01:53:20 PM PDT 24
Finished May 25 01:53:29 PM PDT 24
Peak memory 213988 kb
Host smart-e24d1f7f-c13c-4050-b83f-abd991530b92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235125834 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.1235125834
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.4247243426
Short name T7
Test name
Test status
Simulation time 813778034 ps
CPU time 12.87 seconds
Started May 25 01:02:06 PM PDT 24
Finished May 25 01:02:19 PM PDT 24
Peak memory 233800 kb
Host smart-0b4727e8-5452-4689-844b-5224348aa23b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247243426 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.4247243426
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.3829291417
Short name T181
Test name
Test status
Simulation time 791693699 ps
CPU time 1.99 seconds
Started May 25 01:52:39 PM PDT 24
Finished May 25 01:52:42 PM PDT 24
Peak memory 212932 kb
Host smart-fc5549fb-4367-4094-b567-c9d207e7bc60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829291417 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.3829291417
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.4112777483
Short name T276
Test name
Test status
Simulation time 279027589 ps
CPU time 3.62 seconds
Started May 25 01:53:12 PM PDT 24
Finished May 25 01:53:17 PM PDT 24
Peak memory 214772 kb
Host smart-3c74ace1-ccb6-4e6b-bbac-780c8a5ca585
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112777483 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
4112777483
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.4042045286
Short name T63
Test name
Test status
Simulation time 312376642 ps
CPU time 3.65 seconds
Started May 25 01:53:13 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 212736 kb
Host smart-c0ff59f0-810b-45ae-9d47-cff70850eea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042045286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.4042045286
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.1114703295
Short name T99
Test name
Test status
Simulation time 1047634437 ps
CPU time 14.12 seconds
Started May 25 01:02:18 PM PDT 24
Finished May 25 01:02:32 PM PDT 24
Peak memory 206280 kb
Host smart-345118fa-129e-425f-9cb6-f0c29eaf5c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114703295 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.1114703295
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.3524852038
Short name T9
Test name
Test status
Simulation time 23714214408 ps
CPU time 52.23 seconds
Started May 25 01:02:29 PM PDT 24
Finished May 25 01:03:21 PM PDT 24
Peak memory 207896 kb
Host smart-f2c8ee7b-c6f1-4118-9ffd-b29670520c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524852038 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.3524852038
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.1616193495
Short name T51
Test name
Test status
Simulation time 463119152 ps
CPU time 5.63 seconds
Started May 25 01:52:39 PM PDT 24
Finished May 25 01:52:45 PM PDT 24
Peak memory 214340 kb
Host smart-698b34ab-6b99-4e06-965b-8244e50257e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616193495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.1616193495
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.4050337898
Short name T61
Test name
Test status
Simulation time 94111981 ps
CPU time 2.15 seconds
Started May 25 01:53:14 PM PDT 24
Finished May 25 01:53:17 PM PDT 24
Peak memory 204524 kb
Host smart-aa20c590-b4a6-4a8b-a150-36c000e14348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050337898 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.4050337898
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.2952467459
Short name T56
Test name
Test status
Simulation time 910411948 ps
CPU time 8.16 seconds
Started May 25 01:53:14 PM PDT 24
Finished May 25 01:53:23 PM PDT 24
Peak memory 212772 kb
Host smart-594b1afe-540c-4847-afec-a3f7cc3b6f19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952467459 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.2952467459
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.825790613
Short name T60
Test name
Test status
Simulation time 327348388 ps
CPU time 4.26 seconds
Started May 25 01:53:09 PM PDT 24
Finished May 25 01:53:14 PM PDT 24
Peak memory 212776 kb
Host smart-9de95cda-bc3d-44e0-88ec-184ffe2389dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825790613 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe
_tl_intg_err.825790613
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3180743826
Short name T270
Test name
Test status
Simulation time 21531275 ps
CPU time 1.11 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:13 PM PDT 24
Peak memory 204232 kb
Host smart-298144bd-f02d-4094-add7-4f21be31fe26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180743826 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.3180743826
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.4159410261
Short name T130
Test name
Test status
Simulation time 32159647 ps
CPU time 0.71 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:12 PM PDT 24
Peak memory 204336 kb
Host smart-b9278faa-3100-4e9c-b689-a8db766b6aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159410261 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
4159410261
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.2259598958
Short name T80
Test name
Test status
Simulation time 681856609 ps
CPU time 19.95 seconds
Started May 25 01:01:57 PM PDT 24
Finished May 25 01:02:18 PM PDT 24
Peak memory 208204 kb
Host smart-d2b27b96-27bb-4d8b-b8aa-2b68eb023119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259598958 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.2259598958
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.2260888888
Short name T118
Test name
Test status
Simulation time 6313325670 ps
CPU time 28.13 seconds
Started May 25 01:02:07 PM PDT 24
Finished May 25 01:02:36 PM PDT 24
Peak memory 207796 kb
Host smart-22322e5b-d6c6-4d19-a7bf-fb4933a8f380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260888888 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.2260888888
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.895580771
Short name T122
Test name
Test status
Simulation time 578158181 ps
CPU time 9.32 seconds
Started May 25 01:02:16 PM PDT 24
Finished May 25 01:02:26 PM PDT 24
Peak memory 208268 kb
Host smart-f300b241-66c1-4601-ac71-ef559aa96e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895580771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.895580771
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.854481678
Short name T112
Test name
Test status
Simulation time 559716223 ps
CPU time 18.3 seconds
Started May 25 01:02:16 PM PDT 24
Finished May 25 01:02:34 PM PDT 24
Peak memory 207844 kb
Host smart-d71ccc92-2f13-459b-aef1-1823fb3b8599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854481678 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.854481678
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.2373901741
Short name T115
Test name
Test status
Simulation time 2050014441 ps
CPU time 20.08 seconds
Started May 25 01:02:07 PM PDT 24
Finished May 25 01:02:28 PM PDT 24
Peak memory 207504 kb
Host smart-fee02313-3950-4e0e-9891-a22757532aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373901741 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.2373901741
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.1978127824
Short name T73
Test name
Test status
Simulation time 543520678 ps
CPU time 9.07 seconds
Started May 25 01:02:16 PM PDT 24
Finished May 25 01:02:26 PM PDT 24
Peak memory 206332 kb
Host smart-1478ee41-783b-4c5a-a75b-4c7d687e879d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978127824 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.1978127824
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.3080172661
Short name T116
Test name
Test status
Simulation time 25121453488 ps
CPU time 66.79 seconds
Started May 25 01:02:18 PM PDT 24
Finished May 25 01:03:25 PM PDT 24
Peak memory 207860 kb
Host smart-e6a94e49-d612-4e8c-be91-9c2b69549428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080172661 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3080172661
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.4100161921
Short name T125
Test name
Test status
Simulation time 1667414747 ps
CPU time 15.74 seconds
Started May 25 01:02:18 PM PDT 24
Finished May 25 01:02:34 PM PDT 24
Peak memory 207736 kb
Host smart-962bd3eb-d6ed-46bb-9c88-ba6cb86c5b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100161921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.4100161921
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.1635879349
Short name T8
Test name
Test status
Simulation time 475382870 ps
CPU time 15.07 seconds
Started May 25 01:02:28 PM PDT 24
Finished May 25 01:02:43 PM PDT 24
Peak memory 207932 kb
Host smart-25cf3807-1678-4b8f-bd12-bce44307bfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635879349 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.1635879349
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.2359970132
Short name T113
Test name
Test status
Simulation time 21449066781 ps
CPU time 137.65 seconds
Started May 25 01:02:28 PM PDT 24
Finished May 25 01:04:46 PM PDT 24
Peak memory 208496 kb
Host smart-24beef83-c503-4fca-a5ff-2e7cf8f6854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359970132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.2359970132
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.3656228829
Short name T117
Test name
Test status
Simulation time 490734809 ps
CPU time 17.27 seconds
Started May 25 01:02:29 PM PDT 24
Finished May 25 01:02:46 PM PDT 24
Peak memory 207448 kb
Host smart-e069421b-ecd2-4e51-94f3-253aed86195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656228829 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.3656228829
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.2927705332
Short name T111
Test name
Test status
Simulation time 559496929 ps
CPU time 18.79 seconds
Started May 25 01:02:13 PM PDT 24
Finished May 25 01:02:32 PM PDT 24
Peak memory 208488 kb
Host smart-f471b497-7d9e-4b58-ad3b-cb82d4354782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927705332 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.2927705332
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.3241723145
Short name T76
Test name
Test status
Simulation time 4830964000 ps
CPU time 34.64 seconds
Started May 25 01:02:08 PM PDT 24
Finished May 25 01:02:43 PM PDT 24
Peak memory 208556 kb
Host smart-8f45ae7b-4d99-4b5a-9f6c-5908fd7177c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241723145 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.3241723145
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.1849523674
Short name T71
Test name
Test status
Simulation time 454011662 ps
CPU time 3.41 seconds
Started May 25 01:52:49 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 204436 kb
Host smart-2f30d327-691e-46ab-ae05-5835dc4338b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849523674 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.1849523674
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1472155203
Short name T72
Test name
Test status
Simulation time 451799338 ps
CPU time 10.18 seconds
Started May 25 01:52:46 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 204528 kb
Host smart-b0c9dea7-fb9e-4edc-92ec-92a565ccc1c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472155203 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.1472155203
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.19593844
Short name T236
Test name
Test status
Simulation time 53222730 ps
CPU time 1.08 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 204508 kb
Host smart-66b923aa-d149-4abb-ae4e-b2a1f01a72f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19593844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_
hw_reset.19593844
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.3159529844
Short name T224
Test name
Test status
Simulation time 19713888 ps
CPU time 0.96 seconds
Started May 25 01:52:45 PM PDT 24
Finished May 25 01:52:46 PM PDT 24
Peak memory 204440 kb
Host smart-2dbd3289-fdb2-482f-b1c4-58997a779000
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159529844 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.3159529844
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.2828132472
Short name T214
Test name
Test status
Simulation time 51378913 ps
CPU time 0.97 seconds
Started May 25 01:52:50 PM PDT 24
Finished May 25 01:52:51 PM PDT 24
Peak memory 204472 kb
Host smart-81ec6d85-acd6-4f5a-b2ea-4a76e8c6d3eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828132472 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.2
828132472
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.3336592471
Short name T44
Test name
Test status
Simulation time 17351733 ps
CPU time 0.76 seconds
Started May 25 01:52:47 PM PDT 24
Finished May 25 01:52:49 PM PDT 24
Peak memory 204408 kb
Host smart-a606685d-9ede-49d4-902d-26d61e1247df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336592471 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.3
336592471
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.3023963798
Short name T275
Test name
Test status
Simulation time 77637555 ps
CPU time 1.88 seconds
Started May 25 01:52:54 PM PDT 24
Finished May 25 01:52:56 PM PDT 24
Peak memory 204584 kb
Host smart-e4927f9c-98ca-4182-8e8a-2bd7608ee53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023963798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.3023963798
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.681612604
Short name T296
Test name
Test status
Simulation time 80282995 ps
CPU time 2.53 seconds
Started May 25 01:52:39 PM PDT 24
Finished May 25 01:52:42 PM PDT 24
Peak memory 212768 kb
Host smart-54c6957f-a890-4893-9ab0-4c7b03567900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681612604 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.681612604
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.47009479
Short name T274
Test name
Test status
Simulation time 1190797197 ps
CPU time 10.29 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:53:02 PM PDT 24
Peak memory 204564 kb
Host smart-5dfecf41-3d88-4619-8361-e46e10a4b866
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47009479 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_
aliasing.47009479
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.673799428
Short name T272
Test name
Test status
Simulation time 878088441 ps
CPU time 6.44 seconds
Started May 25 01:52:47 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 204656 kb
Host smart-da14ecc9-a199-4f8c-ab7b-0238fcf545d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673799428 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_bit_bash.673799428
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.3253111619
Short name T177
Test name
Test status
Simulation time 11876412 ps
CPU time 0.94 seconds
Started May 25 01:52:46 PM PDT 24
Finished May 25 01:52:47 PM PDT 24
Peak memory 204536 kb
Host smart-4bcd65d0-5018-419e-92e6-b668f8da6c7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253111619 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.3253111619
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.2135353092
Short name T18
Test name
Test status
Simulation time 26297974 ps
CPU time 1.22 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:55 PM PDT 24
Peak memory 212776 kb
Host smart-6cbdaa1e-2876-43e2-b458-aff049ff2d66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135353092 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.2135353092
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.453789546
Short name T284
Test name
Test status
Simulation time 43457929 ps
CPU time 0.93 seconds
Started May 25 01:52:47 PM PDT 24
Finished May 25 01:52:48 PM PDT 24
Peak memory 204356 kb
Host smart-aab362f5-8c31-407c-a71e-8a832c3b02cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453789546 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.453789546
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.2171756458
Short name T241
Test name
Test status
Simulation time 12041290 ps
CPU time 0.75 seconds
Started May 25 01:52:47 PM PDT 24
Finished May 25 01:52:48 PM PDT 24
Peak memory 204340 kb
Host smart-dcb87439-6921-41b6-8881-251e619ea209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171756458 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.2
171756458
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.3602082313
Short name T94
Test name
Test status
Simulation time 191388402 ps
CPU time 2.01 seconds
Started May 25 01:52:45 PM PDT 24
Finished May 25 01:52:47 PM PDT 24
Peak memory 212712 kb
Host smart-a8c784b0-9cc8-4e96-8e2b-53b9c1d029ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602082313 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.3602082313
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.3101011004
Short name T231
Test name
Test status
Simulation time 67141914 ps
CPU time 1.32 seconds
Started May 25 01:52:49 PM PDT 24
Finished May 25 01:52:51 PM PDT 24
Peak memory 213060 kb
Host smart-6972acd1-bcb0-4d62-8b4f-80b83685f46a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101011004 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.3101011004
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2527061721
Short name T242
Test name
Test status
Simulation time 788933613 ps
CPU time 6.15 seconds
Started May 25 01:52:49 PM PDT 24
Finished May 25 01:52:56 PM PDT 24
Peak memory 213008 kb
Host smart-9bbc18f6-7b03-4fe3-b1b5-c7cb095cd2a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527061721 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2527061721
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.4282683998
Short name T41
Test name
Test status
Simulation time 65040110 ps
CPU time 2.47 seconds
Started May 25 01:52:50 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 214892 kb
Host smart-5d36b813-7235-4806-97d7-f4613d424e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282683998 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.4
282683998
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.614610870
Short name T34
Test name
Test status
Simulation time 96280349 ps
CPU time 2.25 seconds
Started May 25 01:52:48 PM PDT 24
Finished May 25 01:52:51 PM PDT 24
Peak memory 212860 kb
Host smart-f7441554-d138-49bb-b83e-aecda96a9db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614610870 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_
tl_intg_err.614610870
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.198134737
Short name T195
Test name
Test status
Simulation time 136297406 ps
CPU time 0.92 seconds
Started May 25 01:53:13 PM PDT 24
Finished May 25 01:53:15 PM PDT 24
Peak memory 204444 kb
Host smart-c1f6e187-b621-4608-b1da-e5a81e3f1aa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198134737 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.198134737
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.1025497233
Short name T101
Test name
Test status
Simulation time 88555846 ps
CPU time 0.85 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:14 PM PDT 24
Peak memory 204328 kb
Host smart-7ee052f3-72a1-4295-a987-25e5222d980e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025497233 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
1025497233
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.1958947316
Short name T45
Test name
Test status
Simulation time 52122893 ps
CPU time 0.77 seconds
Started May 25 01:53:07 PM PDT 24
Finished May 25 01:53:08 PM PDT 24
Peak memory 204320 kb
Host smart-ed24ed26-eb0c-484b-92f4-9f82597cf847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958947316 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
1958947316
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.3739751189
Short name T268
Test name
Test status
Simulation time 333952056 ps
CPU time 2.08 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:14 PM PDT 24
Peak memory 204612 kb
Host smart-50d474d5-84de-4763-8c75-201f128f5855
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739751189 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.3739751189
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.1838359269
Short name T250
Test name
Test status
Simulation time 1177387410 ps
CPU time 2.45 seconds
Started May 25 01:52:50 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 212860 kb
Host smart-a3832b6f-eb7d-4bff-b4d8-cf32d0f2c49b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838359269 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.1838359269
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1820747067
Short name T271
Test name
Test status
Simulation time 400536418 ps
CPU time 3.24 seconds
Started May 25 01:53:14 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 213044 kb
Host smart-04784a6b-6ba0-43e9-a66d-023ab2ab0cdf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820747067 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1820747067
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.2016595003
Short name T50
Test name
Test status
Simulation time 319988760 ps
CPU time 4.99 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 213676 kb
Host smart-7a0460d6-3a36-46ef-af01-16baae17184c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016595003 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.2016595003
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.1474563954
Short name T108
Test name
Test status
Simulation time 105462189 ps
CPU time 1.14 seconds
Started May 25 01:53:08 PM PDT 24
Finished May 25 01:53:09 PM PDT 24
Peak memory 204376 kb
Host smart-e0dcbc20-3175-49af-83f6-5ba4dd689b53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474563954 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
1474563954
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1489801021
Short name T238
Test name
Test status
Simulation time 11684661 ps
CPU time 0.72 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:13 PM PDT 24
Peak memory 204164 kb
Host smart-48173327-f963-474d-9083-9c238b49e14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489801021 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
1489801021
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.1048277050
Short name T219
Test name
Test status
Simulation time 234126748 ps
CPU time 1.82 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:15 PM PDT 24
Peak memory 204424 kb
Host smart-65deacce-f29b-4146-892d-d94cdad6a29b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048277050 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.1048277050
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1222436292
Short name T299
Test name
Test status
Simulation time 325160431 ps
CPU time 2.31 seconds
Started May 25 01:53:14 PM PDT 24
Finished May 25 01:53:17 PM PDT 24
Peak memory 212868 kb
Host smart-04bb6064-bcbb-40b3-862d-84486ad2e1ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222436292 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.1222436292
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.2315816712
Short name T212
Test name
Test status
Simulation time 197118154 ps
CPU time 5.01 seconds
Started May 25 01:53:09 PM PDT 24
Finished May 25 01:53:14 PM PDT 24
Peak memory 212992 kb
Host smart-54e10bb7-718b-4d7f-afca-28d099e2f3fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315816712 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.2315816712
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1381570529
Short name T230
Test name
Test status
Simulation time 391594739 ps
CPU time 3.37 seconds
Started May 25 01:53:09 PM PDT 24
Finished May 25 01:53:13 PM PDT 24
Peak memory 212796 kb
Host smart-791e76a1-fed5-4d73-85f7-24da1b7e6c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381570529 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
1381570529
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.641829287
Short name T53
Test name
Test status
Simulation time 3661760472 ps
CPU time 7.89 seconds
Started May 25 01:53:06 PM PDT 24
Finished May 25 01:53:15 PM PDT 24
Peak memory 215304 kb
Host smart-a1f0c1ef-c25d-4204-9a43-d2ac7587e8a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641829287 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe
_tl_intg_err.641829287
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3727682887
Short name T223
Test name
Test status
Simulation time 61369624 ps
CPU time 1.34 seconds
Started May 25 01:53:09 PM PDT 24
Finished May 25 01:53:11 PM PDT 24
Peak memory 212708 kb
Host smart-a4759909-1fc6-49d6-9340-ce303ed62537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727682887 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.3727682887
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.1304992714
Short name T86
Test name
Test status
Simulation time 115407324 ps
CPU time 0.91 seconds
Started May 25 01:53:09 PM PDT 24
Finished May 25 01:53:11 PM PDT 24
Peak memory 204444 kb
Host smart-f7cd03e0-2a30-47f6-aca9-c45d1ab5c20e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304992714 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
1304992714
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.2071593602
Short name T178
Test name
Test status
Simulation time 9611363 ps
CPU time 0.82 seconds
Started May 25 01:53:14 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 204392 kb
Host smart-c13464b4-762c-4238-b46d-bbb4ef36681f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071593602 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
2071593602
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.2260782335
Short name T226
Test name
Test status
Simulation time 48366590 ps
CPU time 2.1 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:19 PM PDT 24
Peak memory 204544 kb
Host smart-c7e903a2-68ac-4bbe-bbf1-9b091e213903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260782335 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.2260782335
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.1207085096
Short name T246
Test name
Test status
Simulation time 180221843 ps
CPU time 2.9 seconds
Started May 25 01:53:12 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 213096 kb
Host smart-3a78a05a-2883-477a-8b84-7016c1851157
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207085096 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.1207085096
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3414116536
Short name T203
Test name
Test status
Simulation time 119169501 ps
CPU time 5.97 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:23 PM PDT 24
Peak memory 213048 kb
Host smart-369441bd-f87f-4169-bcc7-9a9398914799
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414116536 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3414116536
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3574101054
Short name T55
Test name
Test status
Simulation time 85319609 ps
CPU time 3.07 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 216076 kb
Host smart-aba24f47-8e91-4eb4-abde-458945457964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574101054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
3574101054
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.215441432
Short name T200
Test name
Test status
Simulation time 111164885 ps
CPU time 1.54 seconds
Started May 25 01:53:13 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 214996 kb
Host smart-a9e98e59-3186-4b79-945f-ee72ea464da9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215441432 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.215441432
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1742632938
Short name T292
Test name
Test status
Simulation time 12918594 ps
CPU time 0.89 seconds
Started May 25 01:53:14 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 204396 kb
Host smart-ea7cd1c6-1db5-4171-8721-dccb7df901e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742632938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
1742632938
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.2749613882
Short name T240
Test name
Test status
Simulation time 100688209 ps
CPU time 1.75 seconds
Started May 25 01:53:13 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 204452 kb
Host smart-d8e63387-6955-4e78-9b9d-9e5f44a6ba71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749613882 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.2749613882
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.2751400718
Short name T192
Test name
Test status
Simulation time 96120332 ps
CPU time 2.03 seconds
Started May 25 01:53:07 PM PDT 24
Finished May 25 01:53:10 PM PDT 24
Peak memory 213112 kb
Host smart-697ccce6-32d6-46ab-8fd0-1952e7f2887e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751400718 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.2751400718
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1100739188
Short name T262
Test name
Test status
Simulation time 142387388 ps
CPU time 4.09 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 213000 kb
Host smart-5205edba-22bf-48f2-bba6-69cbf2ec39fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100739188 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1100739188
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1280426968
Short name T280
Test name
Test status
Simulation time 142451914 ps
CPU time 2.59 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:14 PM PDT 24
Peak memory 220960 kb
Host smart-bc5878eb-a74d-4823-a804-16d95a37c92c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280426968 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
1280426968
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.2577430995
Short name T104
Test name
Test status
Simulation time 59065548 ps
CPU time 1 seconds
Started May 25 01:53:09 PM PDT 24
Finished May 25 01:53:10 PM PDT 24
Peak memory 204524 kb
Host smart-8f1d8309-f5af-4e90-a105-37a9f9512ae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577430995 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.2577430995
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.1952033545
Short name T298
Test name
Test status
Simulation time 180012635 ps
CPU time 0.99 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:13 PM PDT 24
Peak memory 204388 kb
Host smart-f8cda836-280b-4bb9-b2f2-4fa0024c0a4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952033545 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
1952033545
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2782428991
Short name T184
Test name
Test status
Simulation time 11804880 ps
CPU time 0.75 seconds
Started May 25 01:53:13 PM PDT 24
Finished May 25 01:53:15 PM PDT 24
Peak memory 204248 kb
Host smart-f5a817e3-8d7a-4d3f-802c-7829c7297a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782428991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
2782428991
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.785937480
Short name T265
Test name
Test status
Simulation time 230002357 ps
CPU time 1.63 seconds
Started May 25 01:53:09 PM PDT 24
Finished May 25 01:53:11 PM PDT 24
Peak memory 204440 kb
Host smart-1e66c111-1e2e-491b-8951-480c433fe7e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785937480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_dpe_same_csr_outstanding.785937480
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.2353212373
Short name T179
Test name
Test status
Simulation time 94831195 ps
CPU time 1.86 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:12 PM PDT 24
Peak memory 213036 kb
Host smart-617a53d6-6de8-4a4e-89af-9b0f01d98a84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353212373 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.2353212373
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3935130241
Short name T105
Test name
Test status
Simulation time 1107595679 ps
CPU time 6.09 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 212956 kb
Host smart-279ee5f3-9d10-43c6-b7c2-26363c6fd381
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935130241 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3935130241
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.774598829
Short name T32
Test name
Test status
Simulation time 276807244 ps
CPU time 1.72 seconds
Started May 25 01:53:12 PM PDT 24
Finished May 25 01:53:15 PM PDT 24
Peak memory 214076 kb
Host smart-075ddbca-d624-49d9-ab95-e7a0e94cd938
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774598829 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.774598829
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.2723131744
Short name T234
Test name
Test status
Simulation time 16900874 ps
CPU time 1.59 seconds
Started May 25 01:53:08 PM PDT 24
Finished May 25 01:53:10 PM PDT 24
Peak memory 212724 kb
Host smart-7a0521e8-de8a-41cc-a0a5-e2b4a46a24f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723131744 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.2723131744
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.3623637601
Short name T279
Test name
Test status
Simulation time 25968641 ps
CPU time 0.88 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:12 PM PDT 24
Peak memory 204464 kb
Host smart-e711854c-7858-4173-8762-53220ec4e5e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623637601 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
3623637601
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.3995032536
Short name T258
Test name
Test status
Simulation time 14834072 ps
CPU time 0.81 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:12 PM PDT 24
Peak memory 204444 kb
Host smart-39e3cb56-20ed-4ab2-a6a5-ac256d5bc4f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995032536 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
3995032536
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.3302672722
Short name T291
Test name
Test status
Simulation time 64587094 ps
CPU time 1.19 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:13 PM PDT 24
Peak memory 204452 kb
Host smart-e4596c1b-e6a7-409e-ba34-0a88fa457dc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302672722 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.3302672722
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.4153049570
Short name T259
Test name
Test status
Simulation time 90813696 ps
CPU time 2.43 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:15 PM PDT 24
Peak memory 213004 kb
Host smart-71f43f09-edb6-4ffc-87e9-f0e415a17944
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153049570 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.4153049570
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3168236216
Short name T307
Test name
Test status
Simulation time 841635443 ps
CPU time 7.62 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:20 PM PDT 24
Peak memory 213008 kb
Host smart-a513556e-0e42-4639-9c5f-de1710771bf2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168236216 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3168236216
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.2823809076
Short name T289
Test name
Test status
Simulation time 649127316 ps
CPU time 2.42 seconds
Started May 25 01:53:12 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 212828 kb
Host smart-cbb91981-eeb7-4e48-9bb9-178f01e8e926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823809076 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
2823809076
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.3985222599
Short name T58
Test name
Test status
Simulation time 126276971 ps
CPU time 4.53 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:17 PM PDT 24
Peak memory 204472 kb
Host smart-4d8e85c7-4fd3-48a8-8ce5-5ecb7638d796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985222599 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.3985222599
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.787988330
Short name T54
Test name
Test status
Simulation time 97583661 ps
CPU time 1.16 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:14 PM PDT 24
Peak memory 220760 kb
Host smart-d70db71b-b1f7-409c-83e8-4a68030b89db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787988330 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.787988330
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.907790352
Short name T285
Test name
Test status
Simulation time 44223166 ps
CPU time 0.85 seconds
Started May 25 01:53:13 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 204324 kb
Host smart-68344761-f55a-46e1-ab02-b9cfe6ab6f33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907790352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.907790352
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.578986474
Short name T132
Test name
Test status
Simulation time 137692135 ps
CPU time 0.72 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:12 PM PDT 24
Peak memory 204336 kb
Host smart-3d052be8-7bee-4379-b00f-e93f3dd463c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578986474 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.578986474
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2519004435
Short name T267
Test name
Test status
Simulation time 90862911 ps
CPU time 1.29 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:14 PM PDT 24
Peak memory 204528 kb
Host smart-a9f8b33c-34aa-4095-aa68-5d073065053e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519004435 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.2519004435
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.3836612779
Short name T66
Test name
Test status
Simulation time 73767274 ps
CPU time 2.14 seconds
Started May 25 01:53:06 PM PDT 24
Finished May 25 01:53:09 PM PDT 24
Peak memory 213020 kb
Host smart-9f6705c5-8809-48c1-865d-ac7658c42b25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836612779 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.3836612779
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2053795869
Short name T269
Test name
Test status
Simulation time 190191365 ps
CPU time 2.4 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:14 PM PDT 24
Peak memory 213016 kb
Host smart-58ba2c3b-9f59-420f-b09b-649cafea79b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053795869 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2053795869
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.1603938979
Short name T244
Test name
Test status
Simulation time 363489405 ps
CPU time 3.86 seconds
Started May 25 01:53:13 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 212248 kb
Host smart-4f6ea108-02e9-4ea6-8c14-344e661ee143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603938979 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
1603938979
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2942602649
Short name T261
Test name
Test status
Simulation time 22497322 ps
CPU time 0.94 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:12 PM PDT 24
Peak memory 204432 kb
Host smart-23e7d1eb-a454-4ef8-bb17-783ebe5947ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942602649 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.2942602649
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.2818992492
Short name T204
Test name
Test status
Simulation time 42468407 ps
CPU time 0.94 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:13 PM PDT 24
Peak memory 204368 kb
Host smart-81b249de-d93c-40b9-84c0-8af94d7c9c7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818992492 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
2818992492
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.3326090440
Short name T286
Test name
Test status
Simulation time 47376533 ps
CPU time 0.9 seconds
Started May 25 01:53:11 PM PDT 24
Finished May 25 01:53:13 PM PDT 24
Peak memory 204336 kb
Host smart-a9b2987a-a20b-4e64-91db-a98d0fa158fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326090440 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
3326090440
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.1441046671
Short name T36
Test name
Test status
Simulation time 27878486 ps
CPU time 1.82 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:19 PM PDT 24
Peak memory 204604 kb
Host smart-1f8f5a25-2ab2-49bc-a34a-8ec02cb9537d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441046671 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.1441046671
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.1221164550
Short name T229
Test name
Test status
Simulation time 164505700 ps
CPU time 2.68 seconds
Started May 25 01:53:07 PM PDT 24
Finished May 25 01:53:11 PM PDT 24
Peak memory 212968 kb
Host smart-13bc171a-5bba-4a7d-b7a5-85fcfc9fccd6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221164550 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.1221164550
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3386995464
Short name T91
Test name
Test status
Simulation time 71872844 ps
CPU time 2.5 seconds
Started May 25 01:53:09 PM PDT 24
Finished May 25 01:53:12 PM PDT 24
Peak memory 212980 kb
Host smart-2e1450f2-6b84-4e09-99cb-d097d2749c08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386995464 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3386995464
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.3252351555
Short name T42
Test name
Test status
Simulation time 2753320838 ps
CPU time 3.87 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:15 PM PDT 24
Peak memory 212900 kb
Host smart-399a2ca9-4f94-40f6-9980-09b419fe241a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252351555 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
3252351555
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.1312371405
Short name T48
Test name
Test status
Simulation time 192764530 ps
CPU time 4.05 seconds
Started May 25 01:53:13 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 213256 kb
Host smart-5ac8df4f-b5c7-4627-9f06-418004791364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312371405 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.1312371405
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2186489332
Short name T210
Test name
Test status
Simulation time 30022131 ps
CPU time 1.7 seconds
Started May 25 01:53:17 PM PDT 24
Finished May 25 01:53:21 PM PDT 24
Peak memory 212740 kb
Host smart-12faea6c-c8a6-4cc9-8bb5-002125a001c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186489332 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.2186489332
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2790692045
Short name T288
Test name
Test status
Simulation time 92465330 ps
CPU time 1.04 seconds
Started May 25 01:53:14 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 204384 kb
Host smart-1f6171bc-2130-47d6-a4dd-4ace685666ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790692045 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
2790692045
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.252509313
Short name T193
Test name
Test status
Simulation time 115128358 ps
CPU time 0.73 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 204304 kb
Host smart-cce0bc2d-22ab-41f4-a4a6-8fd140d43248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252509313 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.252509313
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1723637115
Short name T243
Test name
Test status
Simulation time 49803024 ps
CPU time 2.03 seconds
Started May 25 01:53:15 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 204444 kb
Host smart-e901bfc1-1f84-4941-83f7-8bad6a3406d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723637115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.1723637115
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.3034884384
Short name T209
Test name
Test status
Simulation time 68256157 ps
CPU time 1.68 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:12 PM PDT 24
Peak memory 212964 kb
Host smart-8b6bd4cb-10e5-49cb-b467-6d32086937af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034884384 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.3034884384
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.4037615284
Short name T255
Test name
Test status
Simulation time 470194121 ps
CPU time 2.63 seconds
Started May 25 01:53:10 PM PDT 24
Finished May 25 01:53:14 PM PDT 24
Peak memory 212988 kb
Host smart-6d722eb7-f850-49cc-be54-94455a5545a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037615284 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.4037615284
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1880343056
Short name T260
Test name
Test status
Simulation time 102891095 ps
CPU time 1.69 seconds
Started May 25 01:53:15 PM PDT 24
Finished May 25 01:53:17 PM PDT 24
Peak memory 214816 kb
Host smart-9d9c766b-9023-490c-8e79-c60528807236
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880343056 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
1880343056
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.1803628418
Short name T135
Test name
Test status
Simulation time 243110655 ps
CPU time 1.39 seconds
Started May 25 01:53:19 PM PDT 24
Finished May 25 01:53:22 PM PDT 24
Peak memory 212652 kb
Host smart-b908dc13-6d8e-4f57-acf4-150b6aa2a984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803628418 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.1803628418
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.3217736328
Short name T87
Test name
Test status
Simulation time 189258844 ps
CPU time 1.45 seconds
Started May 25 01:53:17 PM PDT 24
Finished May 25 01:53:20 PM PDT 24
Peak memory 204524 kb
Host smart-0947fe54-496d-409b-866c-157baafc75e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217736328 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
3217736328
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.723856323
Short name T228
Test name
Test status
Simulation time 38780263 ps
CPU time 0.7 seconds
Started May 25 01:53:20 PM PDT 24
Finished May 25 01:53:22 PM PDT 24
Peak memory 204292 kb
Host smart-668ba16e-1d8a-4b71-a47e-4d4a3451d54a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723856323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.723856323
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.3922615268
Short name T208
Test name
Test status
Simulation time 30716331 ps
CPU time 1.13 seconds
Started May 25 01:53:18 PM PDT 24
Finished May 25 01:53:21 PM PDT 24
Peak memory 204544 kb
Host smart-3e6386f4-93ec-474e-8d7b-a8d0deac0f97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922615268 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.3922615268
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2329381316
Short name T222
Test name
Test status
Simulation time 587100023 ps
CPU time 2.2 seconds
Started May 25 01:53:21 PM PDT 24
Finished May 25 01:53:25 PM PDT 24
Peak memory 212984 kb
Host smart-b04b97f1-9632-49d4-b1bb-2b0e6fdf4c6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329381316 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2329381316
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1016205385
Short name T93
Test name
Test status
Simulation time 223069732 ps
CPU time 3.34 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:21 PM PDT 24
Peak memory 213036 kb
Host smart-b8ec8138-9734-4724-9f5a-2b90150be3b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016205385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1016205385
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.3784994733
Short name T295
Test name
Test status
Simulation time 1252341590 ps
CPU time 3.24 seconds
Started May 25 01:53:18 PM PDT 24
Finished May 25 01:53:23 PM PDT 24
Peak memory 212852 kb
Host smart-ca2917a6-e4f6-4b43-aa9a-f6b156be6135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784994733 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
3784994733
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.364820415
Short name T182
Test name
Test status
Simulation time 125212646 ps
CPU time 3.12 seconds
Started May 25 01:52:45 PM PDT 24
Finished May 25 01:52:49 PM PDT 24
Peak memory 204476 kb
Host smart-18415043-289d-4f4c-b23a-d63bc39cf651
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364820415 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_aliasing.364820415
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.170017285
Short name T37
Test name
Test status
Simulation time 596690059 ps
CPU time 17.02 seconds
Started May 25 01:52:49 PM PDT 24
Finished May 25 01:53:07 PM PDT 24
Peak memory 204504 kb
Host smart-bd2571a9-a457-4021-b92f-15bf4398ab93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170017285 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_bit_bash.170017285
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2351627484
Short name T207
Test name
Test status
Simulation time 41489508 ps
CPU time 1.17 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 204568 kb
Host smart-cbb3dc95-de0f-4396-8cb9-401406038ce1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351627484 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.2351627484
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.3902170337
Short name T232
Test name
Test status
Simulation time 140733629 ps
CPU time 1.04 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 204440 kb
Host smart-7064e8c8-4bca-4e95-8be9-913b00636110
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902170337 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.3902170337
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.1849113530
Short name T221
Test name
Test status
Simulation time 62152956 ps
CPU time 1.06 seconds
Started May 25 01:52:52 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 204404 kb
Host smart-0c4c0a4a-b8b6-4f78-9b48-2cddd9dad2e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849113530 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.1
849113530
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.3755172596
Short name T257
Test name
Test status
Simulation time 47974118 ps
CPU time 0.87 seconds
Started May 25 01:52:50 PM PDT 24
Finished May 25 01:52:52 PM PDT 24
Peak memory 204320 kb
Host smart-9c82f434-0559-42e8-a615-851a62175186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755172596 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.3
755172596
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.779477216
Short name T107
Test name
Test status
Simulation time 177887054 ps
CPU time 1.44 seconds
Started May 25 01:52:44 PM PDT 24
Finished May 25 01:52:46 PM PDT 24
Peak memory 204524 kb
Host smart-b8d19b6b-721c-4a99-b6e0-ecd6a1424e63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779477216 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.ke
ymgr_dpe_same_csr_outstanding.779477216
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.3651819555
Short name T237
Test name
Test status
Simulation time 278579163 ps
CPU time 2.32 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:56 PM PDT 24
Peak memory 212984 kb
Host smart-6483d19c-c09f-43aa-936b-d326aa087864
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651819555 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.3651819555
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.701793850
Short name T217
Test name
Test status
Simulation time 66570781 ps
CPU time 3.28 seconds
Started May 25 01:52:46 PM PDT 24
Finished May 25 01:52:50 PM PDT 24
Peak memory 212984 kb
Host smart-1434fc26-7076-4b54-a917-51599cfbeb74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701793850 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.701793850
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.3683404492
Short name T19
Test name
Test status
Simulation time 539478756 ps
CPU time 3.24 seconds
Started May 25 01:52:46 PM PDT 24
Finished May 25 01:52:50 PM PDT 24
Peak memory 215504 kb
Host smart-db45fa94-3729-4188-a4ac-0aeae151b4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683404492 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.3
683404492
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.3477566872
Short name T213
Test name
Test status
Simulation time 11215397 ps
CPU time 0.9 seconds
Started May 25 01:53:17 PM PDT 24
Finished May 25 01:53:19 PM PDT 24
Peak memory 204444 kb
Host smart-e37ee041-5ba2-4402-8c6e-3204a1f114b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477566872 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
3477566872
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.483209048
Short name T256
Test name
Test status
Simulation time 21707029 ps
CPU time 0.78 seconds
Started May 25 01:53:17 PM PDT 24
Finished May 25 01:53:19 PM PDT 24
Peak memory 204340 kb
Host smart-f5f7b86a-ca4b-4219-a649-02fd880e566c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483209048 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.483209048
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.2165529970
Short name T235
Test name
Test status
Simulation time 11141039 ps
CPU time 0.79 seconds
Started May 25 01:53:18 PM PDT 24
Finished May 25 01:53:21 PM PDT 24
Peak memory 204312 kb
Host smart-86bf3400-4922-4fa2-af14-9ad57a15ba42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165529970 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
2165529970
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.188694623
Short name T202
Test name
Test status
Simulation time 25434271 ps
CPU time 0.72 seconds
Started May 25 01:53:15 PM PDT 24
Finished May 25 01:53:17 PM PDT 24
Peak memory 204368 kb
Host smart-64e688ba-1f3a-4576-b25e-4e7c53e948e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188694623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.188694623
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.1125177994
Short name T187
Test name
Test status
Simulation time 30716432 ps
CPU time 0.71 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 204320 kb
Host smart-ded818a2-37af-4f6b-9e20-f66759aee26f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125177994 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
1125177994
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.3388443704
Short name T185
Test name
Test status
Simulation time 9965768 ps
CPU time 0.82 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:19 PM PDT 24
Peak memory 204376 kb
Host smart-89c1a832-cfc2-478d-87f6-afad1f4996f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388443704 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
3388443704
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.2052003599
Short name T273
Test name
Test status
Simulation time 11390032 ps
CPU time 0.82 seconds
Started May 25 01:53:19 PM PDT 24
Finished May 25 01:53:21 PM PDT 24
Peak memory 204376 kb
Host smart-dbeab094-e82e-4f6e-bd9c-e4e70161a74a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052003599 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
2052003599
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.770086876
Short name T251
Test name
Test status
Simulation time 22089439 ps
CPU time 0.86 seconds
Started May 25 01:53:18 PM PDT 24
Finished May 25 01:53:20 PM PDT 24
Peak memory 204364 kb
Host smart-9952bf54-d70c-4650-942c-21507093f86c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770086876 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.770086876
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.2646844944
Short name T287
Test name
Test status
Simulation time 8756607 ps
CPU time 0.82 seconds
Started May 25 01:53:20 PM PDT 24
Finished May 25 01:53:22 PM PDT 24
Peak memory 204376 kb
Host smart-43b4fa8a-77f5-401e-b208-02b4978df27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646844944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
2646844944
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.778753265
Short name T190
Test name
Test status
Simulation time 168340351 ps
CPU time 2.62 seconds
Started May 25 01:52:47 PM PDT 24
Finished May 25 01:52:51 PM PDT 24
Peak memory 204496 kb
Host smart-b5e7fb81-a2ab-46d8-ab26-252d95ca5752
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778753265 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_aliasing.778753265
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.111287718
Short name T176
Test name
Test status
Simulation time 175528962 ps
CPU time 7.56 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:53:01 PM PDT 24
Peak memory 204576 kb
Host smart-a5dd8dfb-5113-4aaa-be01-16e1364aba45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111287718 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_bit_bash.111287718
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.2433148058
Short name T175
Test name
Test status
Simulation time 53729795 ps
CPU time 0.93 seconds
Started May 25 01:52:49 PM PDT 24
Finished May 25 01:52:51 PM PDT 24
Peak memory 204488 kb
Host smart-dba6f6ca-922f-4abc-bac4-f93412969b23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433148058 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.2433148058
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.1528901243
Short name T297
Test name
Test status
Simulation time 26241754 ps
CPU time 1.69 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 220920 kb
Host smart-8975026a-f043-4588-baf6-f2077def2d12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528901243 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.1528901243
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.4167050115
Short name T278
Test name
Test status
Simulation time 33385778 ps
CPU time 0.94 seconds
Started May 25 01:52:54 PM PDT 24
Finished May 25 01:52:55 PM PDT 24
Peak memory 204480 kb
Host smart-3ede1053-10c9-4eeb-9875-7b34da7057bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167050115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.4
167050115
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.1521711454
Short name T293
Test name
Test status
Simulation time 14873708 ps
CPU time 0.91 seconds
Started May 25 01:52:47 PM PDT 24
Finished May 25 01:52:48 PM PDT 24
Peak memory 204408 kb
Host smart-146ab9f7-63d0-4e51-842f-e88d6e5585a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521711454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.1
521711454
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2858934085
Short name T281
Test name
Test status
Simulation time 47161628 ps
CPU time 1.93 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 204396 kb
Host smart-5c36ed2b-5fa6-47af-8bbf-4aab1f007daf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858934085 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.2858934085
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.1711215001
Short name T49
Test name
Test status
Simulation time 65271969 ps
CPU time 2.23 seconds
Started May 25 01:52:46 PM PDT 24
Finished May 25 01:52:49 PM PDT 24
Peak memory 213056 kb
Host smart-de961ca5-a67d-4d6b-a6f0-cd86e141fc0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711215001 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.1711215001
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3598734190
Short name T220
Test name
Test status
Simulation time 125693502 ps
CPU time 4.23 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:53:01 PM PDT 24
Peak memory 213056 kb
Host smart-586886b0-07a4-4bdd-8b9b-1501f6c4c96f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598734190 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3598734190
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.320714050
Short name T300
Test name
Test status
Simulation time 795084784 ps
CPU time 3.8 seconds
Started May 25 01:52:49 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 221012 kb
Host smart-f48cbf64-b9db-4d32-829b-4b34343c9916
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320714050 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.320714050
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.3807195043
Short name T47
Test name
Test status
Simulation time 289757631 ps
CPU time 4.02 seconds
Started May 25 01:52:52 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 212760 kb
Host smart-f69e929e-e234-4ba4-a6ec-e4246fb0ab26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807195043 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.3807195043
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.4182125290
Short name T252
Test name
Test status
Simulation time 16974994 ps
CPU time 0.7 seconds
Started May 25 01:53:19 PM PDT 24
Finished May 25 01:53:22 PM PDT 24
Peak memory 204328 kb
Host smart-4031e8a2-2456-45e5-acd5-5598dc8b68ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182125290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
4182125290
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.891877451
Short name T186
Test name
Test status
Simulation time 144516457 ps
CPU time 0.74 seconds
Started May 25 01:53:19 PM PDT 24
Finished May 25 01:53:22 PM PDT 24
Peak memory 204356 kb
Host smart-b2c82027-0a85-4bfc-9340-0986de291dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891877451 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.891877451
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.1961521302
Short name T306
Test name
Test status
Simulation time 20906253 ps
CPU time 0.85 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 204272 kb
Host smart-5d682cab-b2ee-40fb-b6db-79e191a8a15e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961521302 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
1961521302
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.301171463
Short name T88
Test name
Test status
Simulation time 10257708 ps
CPU time 0.71 seconds
Started May 25 01:53:20 PM PDT 24
Finished May 25 01:53:23 PM PDT 24
Peak memory 204284 kb
Host smart-7d5a3438-d040-456c-976d-74b84aaf9961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301171463 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.301171463
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.2912633895
Short name T225
Test name
Test status
Simulation time 10630823 ps
CPU time 0.73 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 204288 kb
Host smart-23d24da2-c679-4c6a-ae48-5df7d162a418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912633895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
2912633895
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.2937099766
Short name T197
Test name
Test status
Simulation time 7519761 ps
CPU time 0.71 seconds
Started May 25 01:53:18 PM PDT 24
Finished May 25 01:53:21 PM PDT 24
Peak memory 204376 kb
Host smart-04f688b5-c146-4028-bf1e-e95da27d30fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937099766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
2937099766
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.2562989138
Short name T249
Test name
Test status
Simulation time 15055515 ps
CPU time 0.88 seconds
Started May 25 01:53:15 PM PDT 24
Finished May 25 01:53:16 PM PDT 24
Peak memory 204356 kb
Host smart-2648f6c4-a12a-42d6-8e4c-a0d1b8eb99c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562989138 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
2562989138
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.2676393089
Short name T290
Test name
Test status
Simulation time 15310258 ps
CPU time 0.68 seconds
Started May 25 01:53:19 PM PDT 24
Finished May 25 01:53:22 PM PDT 24
Peak memory 204356 kb
Host smart-08aa8ee0-b08f-414b-81ca-df49dc42d97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676393089 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
2676393089
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.190454020
Short name T201
Test name
Test status
Simulation time 31538962 ps
CPU time 0.81 seconds
Started May 25 01:53:17 PM PDT 24
Finished May 25 01:53:19 PM PDT 24
Peak memory 204344 kb
Host smart-62507488-697b-4251-9aff-deeb1036258f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190454020 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.190454020
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2327784798
Short name T43
Test name
Test status
Simulation time 22318112 ps
CPU time 0.68 seconds
Started May 25 01:53:20 PM PDT 24
Finished May 25 01:53:22 PM PDT 24
Peak memory 204344 kb
Host smart-18d5cb21-d456-4da2-9a84-2be3392fa374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327784798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
2327784798
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2642569246
Short name T277
Test name
Test status
Simulation time 43848411 ps
CPU time 3.17 seconds
Started May 25 01:52:45 PM PDT 24
Finished May 25 01:52:48 PM PDT 24
Peak memory 204492 kb
Host smart-8ed9ec89-029b-4c1b-b6d9-f7ba532bbc44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642569246 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.2642569246
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.128471599
Short name T266
Test name
Test status
Simulation time 3438343899 ps
CPU time 12.95 seconds
Started May 25 01:52:48 PM PDT 24
Finished May 25 01:53:02 PM PDT 24
Peak memory 204560 kb
Host smart-659c9456-c991-413f-93fc-3abff66ed051
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128471599 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_bit_bash.128471599
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.201371146
Short name T247
Test name
Test status
Simulation time 85586218 ps
CPU time 1.23 seconds
Started May 25 01:52:46 PM PDT 24
Finished May 25 01:52:48 PM PDT 24
Peak memory 204420 kb
Host smart-703ed4fa-5359-4572-aedc-7b43a9a07ad3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201371146 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_hw_reset.201371146
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.3820879348
Short name T303
Test name
Test status
Simulation time 55440249 ps
CPU time 1.25 seconds
Started May 25 01:52:47 PM PDT 24
Finished May 25 01:52:49 PM PDT 24
Peak memory 204372 kb
Host smart-f685f16f-ae99-4d1f-b4ea-178f8d179ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820879348 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.3820879348
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.4136112143
Short name T301
Test name
Test status
Simulation time 12032146 ps
CPU time 0.86 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 204336 kb
Host smart-f48b84f9-dec0-43b1-88d5-1af9fd5453c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136112143 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.4
136112143
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1143248180
Short name T211
Test name
Test status
Simulation time 51675485 ps
CPU time 0.8 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:55 PM PDT 24
Peak memory 204336 kb
Host smart-55ec7349-d1f1-4f90-b5cb-29df26122517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143248180 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.1
143248180
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.2034449748
Short name T95
Test name
Test status
Simulation time 32439356 ps
CPU time 1.2 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:55 PM PDT 24
Peak memory 204628 kb
Host smart-94e28648-93bd-424d-834b-13db4de368e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034449748 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.2034449748
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.556624233
Short name T180
Test name
Test status
Simulation time 148484486 ps
CPU time 1.69 seconds
Started May 25 01:52:46 PM PDT 24
Finished May 25 01:52:49 PM PDT 24
Peak memory 213120 kb
Host smart-dacb5ad5-bd51-482f-b659-6bc398f5d370
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556624233 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymg
r_dpe_shadow_reg_errors.556624233
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1087592957
Short name T245
Test name
Test status
Simulation time 211735951 ps
CPU time 5.81 seconds
Started May 25 01:52:49 PM PDT 24
Finished May 25 01:52:55 PM PDT 24
Peak memory 213044 kb
Host smart-af1d9892-47cb-487f-ac0b-7d6b9dcb4e5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087592957 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1087592957
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.2392406701
Short name T40
Test name
Test status
Simulation time 233098000 ps
CPU time 2.51 seconds
Started May 25 01:52:47 PM PDT 24
Finished May 25 01:52:50 PM PDT 24
Peak memory 212740 kb
Host smart-6e8e5a46-e682-4b06-9864-1777a4ccc722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392406701 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.2
392406701
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.888478681
Short name T62
Test name
Test status
Simulation time 115932557 ps
CPU time 4.29 seconds
Started May 25 01:52:46 PM PDT 24
Finished May 25 01:52:51 PM PDT 24
Peak memory 213692 kb
Host smart-4df7165f-4353-49b3-99c5-1b4c9709c3e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888478681 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_
tl_intg_err.888478681
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3458413604
Short name T302
Test name
Test status
Simulation time 29581962 ps
CPU time 0.68 seconds
Started May 25 01:53:18 PM PDT 24
Finished May 25 01:53:20 PM PDT 24
Peak memory 204368 kb
Host smart-1be400b2-9b94-43d9-b1c2-12197407b3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458413604 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
3458413604
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.1824754694
Short name T216
Test name
Test status
Simulation time 17925359 ps
CPU time 0.9 seconds
Started May 25 01:53:18 PM PDT 24
Finished May 25 01:53:21 PM PDT 24
Peak memory 204300 kb
Host smart-6bc4f11d-8476-4aba-be2b-86fab422cb8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824754694 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
1824754694
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.312903730
Short name T70
Test name
Test status
Simulation time 11153906 ps
CPU time 0.73 seconds
Started May 25 01:53:19 PM PDT 24
Finished May 25 01:53:22 PM PDT 24
Peak memory 204356 kb
Host smart-3e085ed9-0df2-4ed0-9e0e-e2001b528f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312903730 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.312903730
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.4242333303
Short name T282
Test name
Test status
Simulation time 14711201 ps
CPU time 0.95 seconds
Started May 25 01:53:15 PM PDT 24
Finished May 25 01:53:18 PM PDT 24
Peak memory 204304 kb
Host smart-87e7bf97-35c2-45dc-89b8-933c53db0d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242333303 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
4242333303
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.8011435
Short name T263
Test name
Test status
Simulation time 39650044 ps
CPU time 0.67 seconds
Started May 25 01:53:17 PM PDT 24
Finished May 25 01:53:20 PM PDT 24
Peak memory 204364 kb
Host smart-d6f1c0d2-f678-426e-8f30-c0702e11aa23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8011435 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.8011435
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.2333786830
Short name T205
Test name
Test status
Simulation time 34064365 ps
CPU time 0.74 seconds
Started May 25 01:53:15 PM PDT 24
Finished May 25 01:53:17 PM PDT 24
Peak memory 204376 kb
Host smart-ebaac9a8-77b9-434f-9242-1722622e35e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333786830 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
2333786830
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.596575921
Short name T239
Test name
Test status
Simulation time 52057596 ps
CPU time 0.76 seconds
Started May 25 01:53:16 PM PDT 24
Finished May 25 01:53:19 PM PDT 24
Peak memory 204328 kb
Host smart-4fb72038-c67e-4566-94ba-cdc13fec1c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596575921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.596575921
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.2117021583
Short name T127
Test name
Test status
Simulation time 19011523 ps
CPU time 0.73 seconds
Started May 25 01:53:18 PM PDT 24
Finished May 25 01:53:20 PM PDT 24
Peak memory 204356 kb
Host smart-6650d8b8-45a0-4667-bf7f-a4c19a240bfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117021583 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
2117021583
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.489747889
Short name T206
Test name
Test status
Simulation time 7377322 ps
CPU time 0.73 seconds
Started May 25 01:53:18 PM PDT 24
Finished May 25 01:53:20 PM PDT 24
Peak memory 204324 kb
Host smart-4abb0dec-bc48-4959-a5c0-499d022fb8cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489747889 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.489747889
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.1345572320
Short name T92
Test name
Test status
Simulation time 12794443 ps
CPU time 0.88 seconds
Started May 25 01:53:15 PM PDT 24
Finished May 25 01:53:17 PM PDT 24
Peak memory 204364 kb
Host smart-5642528a-a26f-46df-8fc5-4af04d32ed4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345572320 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
1345572320
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.2433509075
Short name T304
Test name
Test status
Simulation time 56097725 ps
CPU time 1.55 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 212800 kb
Host smart-a54f43d4-c8d9-4083-9054-b2d15f45c255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433509075 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.2433509075
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.4022222110
Short name T198
Test name
Test status
Simulation time 18976380 ps
CPU time 0.9 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 204400 kb
Host smart-1c2fc964-5165-41e1-8284-1b65a046ed7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022222110 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.4
022222110
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.1738086147
Short name T254
Test name
Test status
Simulation time 19899334 ps
CPU time 0.75 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 204264 kb
Host smart-0c03cc6c-df8e-40ea-87b8-145850787a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738086147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.1
738086147
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.3324695188
Short name T102
Test name
Test status
Simulation time 91489447 ps
CPU time 2.4 seconds
Started May 25 01:52:52 PM PDT 24
Finished May 25 01:52:55 PM PDT 24
Peak memory 204388 kb
Host smart-274e3e81-3168-489c-9544-9e2de5825781
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324695188 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.3324695188
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.317662842
Short name T191
Test name
Test status
Simulation time 145629465 ps
CPU time 1.26 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 213112 kb
Host smart-8c806b06-cc67-4576-88c2-1e447c7f89bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317662842 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymg
r_dpe_shadow_reg_errors.317662842
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.743048135
Short name T67
Test name
Test status
Simulation time 334897296 ps
CPU time 3.45 seconds
Started May 25 01:52:49 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 218612 kb
Host smart-b4026944-d90c-404f-8b80-4430b21b7518
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743048135 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.743048135
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.600255877
Short name T57
Test name
Test status
Simulation time 224183380 ps
CPU time 3.97 seconds
Started May 25 01:52:49 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 212768 kb
Host smart-86ff46af-40a1-45b2-955e-ff6a51a35912
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600255877 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.600255877
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.1634878153
Short name T218
Test name
Test status
Simulation time 95390073 ps
CPU time 2.47 seconds
Started May 25 01:52:50 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 204664 kb
Host smart-afd8c8b4-254f-4b71-8c2e-108bb31c373f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634878153 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.1634878153
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.2117639129
Short name T233
Test name
Test status
Simulation time 46243982 ps
CPU time 1.67 seconds
Started May 25 01:52:52 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 204628 kb
Host smart-b2e74020-941f-4b93-99e1-039d05dacb63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117639129 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.2117639129
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.1917258638
Short name T96
Test name
Test status
Simulation time 85992020 ps
CPU time 1.07 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:52:58 PM PDT 24
Peak memory 204404 kb
Host smart-c00fc58d-118d-48c7-bc4e-3d2522d0233c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917258638 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.1
917258638
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1693899391
Short name T196
Test name
Test status
Simulation time 47061882 ps
CPU time 0.69 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 204248 kb
Host smart-a1d6d730-14e3-4baa-8fd8-e1152ae392df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693899391 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.1
693899391
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.4139519975
Short name T103
Test name
Test status
Simulation time 200471402 ps
CPU time 1.51 seconds
Started May 25 01:52:50 PM PDT 24
Finished May 25 01:52:52 PM PDT 24
Peak memory 204616 kb
Host smart-cc45c5f7-99c2-4364-b76a-bf7f5b282369
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139519975 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.4139519975
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.1252781103
Short name T188
Test name
Test status
Simulation time 162714769 ps
CPU time 1.84 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:52:58 PM PDT 24
Peak memory 212908 kb
Host smart-bb871d32-c452-4bb8-8589-d61a9927d1c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252781103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.1252781103
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2240406425
Short name T199
Test name
Test status
Simulation time 1266331411 ps
CPU time 3.69 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 213056 kb
Host smart-962a6bd8-7265-4286-ba56-85c1cea428fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240406425 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2240406425
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.4007684840
Short name T33
Test name
Test status
Simulation time 26487815 ps
CPU time 1.95 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:52:53 PM PDT 24
Peak memory 212784 kb
Host smart-cc9e06d7-7b0c-4063-8105-4b44352aa667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007684840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.4
007684840
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.2178948315
Short name T35
Test name
Test status
Simulation time 109966892 ps
CPU time 2.62 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:52:58 PM PDT 24
Peak memory 213748 kb
Host smart-3393dae4-3e3c-4962-a95a-bc020578595b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178948315 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.2178948315
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.1503004122
Short name T65
Test name
Test status
Simulation time 151423862 ps
CPU time 1.39 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:52:58 PM PDT 24
Peak memory 212752 kb
Host smart-5b3e1ce8-4d9a-4ee8-95a6-407c0706cf43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503004122 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.1503004122
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.580129721
Short name T69
Test name
Test status
Simulation time 16396802 ps
CPU time 0.89 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:55 PM PDT 24
Peak memory 204428 kb
Host smart-778f995f-b844-4eec-af86-f22254482bdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580129721 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.580129721
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.2803200764
Short name T129
Test name
Test status
Simulation time 69088806 ps
CPU time 0.75 seconds
Started May 25 01:52:52 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 204272 kb
Host smart-13b580a4-62ae-4574-9959-ea0f901ea9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803200764 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.2
803200764
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.2485979465
Short name T89
Test name
Test status
Simulation time 52834910 ps
CPU time 2.01 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 204492 kb
Host smart-7fbaa803-456e-4616-833d-2cbeab8eb8e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485979465 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.2485979465
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.2581117421
Short name T64
Test name
Test status
Simulation time 86305334 ps
CPU time 1.75 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:56 PM PDT 24
Peak memory 212984 kb
Host smart-1b965d9c-9329-49d5-a800-86ad257fd3a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581117421 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.2581117421
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.540645477
Short name T309
Test name
Test status
Simulation time 486487526 ps
CPU time 4.74 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:53:01 PM PDT 24
Peak memory 213176 kb
Host smart-c27ac880-93ca-4696-8eda-fa61bcaad360
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540645477 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.540645477
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.1843528820
Short name T305
Test name
Test status
Simulation time 327361967 ps
CPU time 4.6 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:58 PM PDT 24
Peak memory 212652 kb
Host smart-39e23941-acca-411c-9fd7-4dfe003bde44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843528820 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.1843528820
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.3721262832
Short name T106
Test name
Test status
Simulation time 64986811 ps
CPU time 1.15 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:52:58 PM PDT 24
Peak memory 212660 kb
Host smart-11939b7a-4cf3-4407-bea8-363999f19d55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721262832 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.3721262832
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.2140193270
Short name T109
Test name
Test status
Simulation time 144640772 ps
CPU time 1.12 seconds
Started May 25 01:52:47 PM PDT 24
Finished May 25 01:52:49 PM PDT 24
Peak memory 204536 kb
Host smart-371c455f-078a-47f1-8fba-2a7b3c45079a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140193270 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.2
140193270
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.3939552231
Short name T128
Test name
Test status
Simulation time 9529022 ps
CPU time 0.79 seconds
Started May 25 01:52:54 PM PDT 24
Finished May 25 01:52:56 PM PDT 24
Peak memory 204320 kb
Host smart-c15f3bb0-a2ad-48bd-b560-b1eff4be3252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939552231 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.3
939552231
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.1997560524
Short name T308
Test name
Test status
Simulation time 376418643 ps
CPU time 2.3 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:52:58 PM PDT 24
Peak memory 204544 kb
Host smart-288695de-a5c7-4b59-a707-473f2ebdeec8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997560524 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.1997560524
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.1684127858
Short name T194
Test name
Test status
Simulation time 56276335 ps
CPU time 2.09 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:52:58 PM PDT 24
Peak memory 212932 kb
Host smart-3b35a2c3-5141-49d5-8e77-12496406783c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684127858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.1684127858
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.321400214
Short name T189
Test name
Test status
Simulation time 146396127 ps
CPU time 4.35 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:53:01 PM PDT 24
Peak memory 212988 kb
Host smart-a88d08b7-b248-4964-8222-95768cfe632a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321400214 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.321400214
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.2598102451
Short name T227
Test name
Test status
Simulation time 334548160 ps
CPU time 2.26 seconds
Started May 25 01:52:53 PM PDT 24
Finished May 25 01:52:56 PM PDT 24
Peak memory 214960 kb
Host smart-0c503811-385f-487c-a19f-0867cfc990eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598102451 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.2
598102451
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.2211303305
Short name T253
Test name
Test status
Simulation time 21605913 ps
CPU time 1.05 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 204364 kb
Host smart-cf8b099f-8184-48d9-8f32-1b89d0f433e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211303305 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.2211303305
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.4072898747
Short name T248
Test name
Test status
Simulation time 69394217 ps
CPU time 0.97 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 204396 kb
Host smart-e166085c-7652-43e2-b1ca-6d592300747e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072898747 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.4
072898747
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.984900398
Short name T90
Test name
Test status
Simulation time 58595310 ps
CPU time 0.84 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:52:56 PM PDT 24
Peak memory 204288 kb
Host smart-c21c793d-336e-477f-8ce5-29108de9401d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984900398 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.984900398
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.200612198
Short name T294
Test name
Test status
Simulation time 150962818 ps
CPU time 1.36 seconds
Started May 25 01:52:50 PM PDT 24
Finished May 25 01:52:52 PM PDT 24
Peak memory 204424 kb
Host smart-507fb55c-5b88-4c2a-be47-9ef216c91245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200612198 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ke
ymgr_dpe_same_csr_outstanding.200612198
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.1664128067
Short name T183
Test name
Test status
Simulation time 569685660 ps
CPU time 2.13 seconds
Started May 25 01:52:56 PM PDT 24
Finished May 25 01:52:59 PM PDT 24
Peak memory 213052 kb
Host smart-79610707-a29a-44a3-9d7c-d3618d462562
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664128067 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.1664128067
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.609409485
Short name T215
Test name
Test status
Simulation time 231346387 ps
CPU time 6.3 seconds
Started May 25 01:52:55 PM PDT 24
Finished May 25 01:53:02 PM PDT 24
Peak memory 212992 kb
Host smart-4ca6ce03-7973-4861-9400-edbccab0eca3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609409485 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.609409485
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.815512030
Short name T264
Test name
Test status
Simulation time 150921356 ps
CPU time 2.68 seconds
Started May 25 01:52:54 PM PDT 24
Finished May 25 01:52:57 PM PDT 24
Peak memory 212748 kb
Host smart-30fd19b8-c81b-48eb-8442-1146eaeaa71d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815512030 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.815512030
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.3887816159
Short name T283
Test name
Test status
Simulation time 47568406 ps
CPU time 2.23 seconds
Started May 25 01:52:51 PM PDT 24
Finished May 25 01:52:54 PM PDT 24
Peak memory 213684 kb
Host smart-7da01418-d9e4-4ebb-9624-4ed25e6038bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887816159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.3887816159
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.860270298
Short name T158
Test name
Test status
Simulation time 21058571 ps
CPU time 0.92 seconds
Started May 25 01:02:07 PM PDT 24
Finished May 25 01:02:08 PM PDT 24
Peak memory 205608 kb
Host smart-782436c8-0085-4d61-bc4f-eec33ebf4aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860270298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.860270298
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.3161687535
Short name T21
Test name
Test status
Simulation time 717067337 ps
CPU time 5.2 seconds
Started May 25 01:01:59 PM PDT 24
Finished May 25 01:02:05 PM PDT 24
Peak memory 233048 kb
Host smart-57146b51-5568-444d-b6ba-670f57a7a515
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161687535 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.3161687535
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.2248014693
Short name T81
Test name
Test status
Simulation time 8295931 ps
CPU time 0.68 seconds
Started May 25 01:02:07 PM PDT 24
Finished May 25 01:02:09 PM PDT 24
Peak memory 205428 kb
Host smart-e925590b-71e2-4d8e-9810-760671c6afa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248014693 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.2
248014693
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.4031634263
Short name T142
Test name
Test status
Simulation time 53129464 ps
CPU time 0.82 seconds
Started May 25 01:02:19 PM PDT 24
Finished May 25 01:02:20 PM PDT 24
Peak memory 205556 kb
Host smart-e7e68f39-ceb5-4a3b-a4da-fbc68a205f33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031634263 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
4031634263
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.199497684
Short name T26
Test name
Test status
Simulation time 3391795897 ps
CPU time 31.1 seconds
Started May 25 01:02:16 PM PDT 24
Finished May 25 01:02:48 PM PDT 24
Peak memory 208264 kb
Host smart-df37d348-3141-4ca1-a567-427709ef83dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199497684 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.199497684
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.323973355
Short name T149
Test name
Test status
Simulation time 12920814 ps
CPU time 0.85 seconds
Started May 25 01:02:20 PM PDT 24
Finished May 25 01:02:21 PM PDT 24
Peak memory 205476 kb
Host smart-7e669a89-d4f6-49f3-8d53-498672fb3a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323973355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.323973355
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.1037226991
Short name T13
Test name
Test status
Simulation time 873472895 ps
CPU time 15.71 seconds
Started May 25 01:02:16 PM PDT 24
Finished May 25 01:02:33 PM PDT 24
Peak memory 207576 kb
Host smart-5522fa08-bb3f-4702-b568-424cc159f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037226991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.1037226991
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.1904367159
Short name T15
Test name
Test status
Simulation time 18032804 ps
CPU time 0.69 seconds
Started May 25 01:02:17 PM PDT 24
Finished May 25 01:02:18 PM PDT 24
Peak memory 205436 kb
Host smart-88e6c3b8-11a0-4198-9408-1a2ccf436a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904367159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
1904367159
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.609595298
Short name T151
Test name
Test status
Simulation time 20292604 ps
CPU time 0.85 seconds
Started May 25 01:02:16 PM PDT 24
Finished May 25 01:02:17 PM PDT 24
Peak memory 205540 kb
Host smart-2050e4f1-2d0f-492a-b63d-6d168e54ea2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609595298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.609595298
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.2467684464
Short name T31
Test name
Test status
Simulation time 1522841635 ps
CPU time 13.74 seconds
Started May 25 01:02:16 PM PDT 24
Finished May 25 01:02:31 PM PDT 24
Peak memory 206324 kb
Host smart-768acd15-d505-4981-aebc-0a4e9158c1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467684464 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.2467684464
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.3004858976
Short name T140
Test name
Test status
Simulation time 41283138 ps
CPU time 0.71 seconds
Started May 25 01:02:17 PM PDT 24
Finished May 25 01:02:19 PM PDT 24
Peak memory 205480 kb
Host smart-e482a43f-85b9-407e-959c-a61dc9809f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004858976 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
3004858976
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.1306168785
Short name T136
Test name
Test status
Simulation time 12904531 ps
CPU time 0.74 seconds
Started May 25 01:02:17 PM PDT 24
Finished May 25 01:02:18 PM PDT 24
Peak memory 205548 kb
Host smart-b9c99e67-eed9-4936-84d4-da5857af1ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306168785 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
1306168785
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.1605299319
Short name T110
Test name
Test status
Simulation time 1525269033 ps
CPU time 26.84 seconds
Started May 25 01:02:18 PM PDT 24
Finished May 25 01:02:46 PM PDT 24
Peak memory 208304 kb
Host smart-3e36476d-d4c2-4be4-9fe4-1a368d249f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605299319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.1605299319
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.223624135
Short name T25
Test name
Test status
Simulation time 14111861 ps
CPU time 0.75 seconds
Started May 25 01:02:18 PM PDT 24
Finished May 25 01:02:19 PM PDT 24
Peak memory 205528 kb
Host smart-13c86597-162a-47cf-a333-f05a86ac10b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223624135 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.223624135
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.3518631862
Short name T146
Test name
Test status
Simulation time 23947378 ps
CPU time 0.74 seconds
Started May 25 01:02:18 PM PDT 24
Finished May 25 01:02:20 PM PDT 24
Peak memory 205556 kb
Host smart-1924a218-fc63-4c1a-9b3a-48a30f9724c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518631862 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
3518631862
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.4080143707
Short name T100
Test name
Test status
Simulation time 2352413388 ps
CPU time 21.85 seconds
Started May 25 01:02:18 PM PDT 24
Finished May 25 01:02:40 PM PDT 24
Peak memory 208476 kb
Host smart-c03e384b-7753-45f3-9525-794d31f9fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080143707 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.4080143707
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.1502873735
Short name T168
Test name
Test status
Simulation time 12332065 ps
CPU time 0.71 seconds
Started May 25 01:02:17 PM PDT 24
Finished May 25 01:02:19 PM PDT 24
Peak memory 205528 kb
Host smart-773546d3-953b-49bb-8738-3c3869d699b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502873735 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
1502873735
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.3288922415
Short name T147
Test name
Test status
Simulation time 37754383 ps
CPU time 0.84 seconds
Started May 25 01:02:09 PM PDT 24
Finished May 25 01:02:10 PM PDT 24
Peak memory 205540 kb
Host smart-22291e1b-8ebf-405c-86af-05c3ecd1d6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288922415 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.3
288922415
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.3384432730
Short name T170
Test name
Test status
Simulation time 13918293 ps
CPU time 0.88 seconds
Started May 25 01:02:19 PM PDT 24
Finished May 25 01:02:21 PM PDT 24
Peak memory 205544 kb
Host smart-865a1ea9-7e46-4f54-be25-92cb96d2f284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384432730 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
3384432730
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.1364127459
Short name T145
Test name
Test status
Simulation time 136683527 ps
CPU time 0.84 seconds
Started May 25 01:02:17 PM PDT 24
Finished May 25 01:02:18 PM PDT 24
Peak memory 205556 kb
Host smart-4d67eba6-bc45-4052-951e-7eb6853cf74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364127459 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
1364127459
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.3004669972
Short name T83
Test name
Test status
Simulation time 1769039060 ps
CPU time 27.38 seconds
Started May 25 01:02:18 PM PDT 24
Finished May 25 01:02:46 PM PDT 24
Peak memory 207472 kb
Host smart-e16bb5b4-5b19-46b1-ac1b-ca9f9ed4ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004669972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.3004669972
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3301070215
Short name T74
Test name
Test status
Simulation time 17353078 ps
CPU time 0.79 seconds
Started May 25 01:02:20 PM PDT 24
Finished May 25 01:02:21 PM PDT 24
Peak memory 205476 kb
Host smart-66fc843f-877f-4387-8fc3-7b525d9271e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301070215 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3301070215
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.3371349016
Short name T156
Test name
Test status
Simulation time 1606983358 ps
CPU time 13.51 seconds
Started May 25 01:02:22 PM PDT 24
Finished May 25 01:02:35 PM PDT 24
Peak memory 206352 kb
Host smart-075e3afc-816d-4adf-a650-eb70b722f70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371349016 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.3371349016
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.3362749314
Short name T97
Test name
Test status
Simulation time 16730756 ps
CPU time 0.7 seconds
Started May 25 01:02:22 PM PDT 24
Finished May 25 01:02:23 PM PDT 24
Peak memory 205468 kb
Host smart-51e53f2d-0f3f-4889-9108-bee58af7c9f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362749314 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
3362749314
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.1404332179
Short name T27
Test name
Test status
Simulation time 22063040 ps
CPU time 0.89 seconds
Started May 25 01:02:15 PM PDT 24
Finished May 25 01:02:17 PM PDT 24
Peak memory 205512 kb
Host smart-1aa78246-fded-48be-9161-c638fe5d5798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404332179 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
1404332179
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.4231056302
Short name T12
Test name
Test status
Simulation time 31872348007 ps
CPU time 170.74 seconds
Started May 25 01:02:17 PM PDT 24
Finished May 25 01:05:08 PM PDT 24
Peak memory 208076 kb
Host smart-39bd9cdd-7f04-43bb-926f-19e48f93cef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231056302 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.4231056302
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.3345588471
Short name T134
Test name
Test status
Simulation time 15752512 ps
CPU time 0.71 seconds
Started May 25 01:02:17 PM PDT 24
Finished May 25 01:02:19 PM PDT 24
Peak memory 205480 kb
Host smart-37466a11-c0c3-42ce-a0af-e501711d0c28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345588471 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
3345588471
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.1370350241
Short name T159
Test name
Test status
Simulation time 32597021 ps
CPU time 0.75 seconds
Started May 25 01:02:26 PM PDT 24
Finished May 25 01:02:28 PM PDT 24
Peak memory 205500 kb
Host smart-91f2f645-3284-44d2-ac68-d033b2eccdf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370350241 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
1370350241
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.2467933122
Short name T3
Test name
Test status
Simulation time 3063896481 ps
CPU time 15.75 seconds
Started May 25 01:02:26 PM PDT 24
Finished May 25 01:02:42 PM PDT 24
Peak memory 208512 kb
Host smart-543657fa-7f3d-4af2-9470-554c6fbee6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467933122 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.2467933122
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.2289181808
Short name T150
Test name
Test status
Simulation time 12722588 ps
CPU time 0.87 seconds
Started May 25 01:02:27 PM PDT 24
Finished May 25 01:02:28 PM PDT 24
Peak memory 205448 kb
Host smart-f71e0250-ecb2-4916-8ebe-fd3e27ee3587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289181808 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
2289181808
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.2551219208
Short name T143
Test name
Test status
Simulation time 18729428 ps
CPU time 0.9 seconds
Started May 25 01:02:27 PM PDT 24
Finished May 25 01:02:28 PM PDT 24
Peak memory 205660 kb
Host smart-49b4e284-02c6-4868-9a18-de13d80fca90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551219208 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
2551219208
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.1823263878
Short name T114
Test name
Test status
Simulation time 285657815 ps
CPU time 9.55 seconds
Started May 25 01:02:27 PM PDT 24
Finished May 25 01:02:37 PM PDT 24
Peak memory 208380 kb
Host smart-b5f02f09-069a-4980-b621-a28681e2d647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823263878 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.1823263878
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.1193444398
Short name T148
Test name
Test status
Simulation time 10700243 ps
CPU time 0.73 seconds
Started May 25 01:02:28 PM PDT 24
Finished May 25 01:02:29 PM PDT 24
Peak memory 205496 kb
Host smart-3a9ebaf2-c7ee-4c4f-9963-0a3e596b1ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193444398 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
1193444398
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.2253717004
Short name T169
Test name
Test status
Simulation time 223285096 ps
CPU time 11.91 seconds
Started May 25 01:02:26 PM PDT 24
Finished May 25 01:02:39 PM PDT 24
Peak memory 207688 kb
Host smart-fddb5f19-3164-4b1f-93e2-99b62d13dfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253717004 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.2253717004
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.74767374
Short name T16
Test name
Test status
Simulation time 248163385 ps
CPU time 0.84 seconds
Started May 25 01:02:07 PM PDT 24
Finished May 25 01:02:09 PM PDT 24
Peak memory 205460 kb
Host smart-a4be69a9-3b89-485a-ba6b-6ef69c90c616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74767374 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.74767374
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.2896808807
Short name T5
Test name
Test status
Simulation time 410655517 ps
CPU time 6.35 seconds
Started May 25 01:02:08 PM PDT 24
Finished May 25 01:02:15 PM PDT 24
Peak memory 233016 kb
Host smart-b791c907-4aea-443b-93af-983426e6e539
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896808807 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.2896808807
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.289882803
Short name T84
Test name
Test status
Simulation time 2971473374 ps
CPU time 14.86 seconds
Started May 25 01:02:09 PM PDT 24
Finished May 25 01:02:25 PM PDT 24
Peak memory 208184 kb
Host smart-4c5963fd-beb1-482a-94f6-2aeb8837fbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289882803 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.289882803
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.509238047
Short name T17
Test name
Test status
Simulation time 9354711 ps
CPU time 0.75 seconds
Started May 25 01:02:29 PM PDT 24
Finished May 25 01:02:30 PM PDT 24
Peak memory 205540 kb
Host smart-959b8f7d-6726-4578-a39e-db4fcd482d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509238047 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.509238047
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.3686475001
Short name T163
Test name
Test status
Simulation time 11750399 ps
CPU time 0.85 seconds
Started May 25 01:02:29 PM PDT 24
Finished May 25 01:02:30 PM PDT 24
Peak memory 205452 kb
Host smart-e0310363-c93a-47c2-b0b0-885b3931032c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686475001 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
3686475001
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.1039132379
Short name T167
Test name
Test status
Simulation time 1444788024 ps
CPU time 16.63 seconds
Started May 25 01:02:29 PM PDT 24
Finished May 25 01:02:46 PM PDT 24
Peak memory 207388 kb
Host smart-327ed176-44c5-4f8f-80a6-2ea91c9635df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039132379 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.1039132379
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.3473113241
Short name T24
Test name
Test status
Simulation time 12809768 ps
CPU time 0.89 seconds
Started May 25 01:02:27 PM PDT 24
Finished May 25 01:02:28 PM PDT 24
Peak memory 205492 kb
Host smart-4be6b858-5413-4445-852b-d65117c6d8e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473113241 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
3473113241
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.3630610560
Short name T155
Test name
Test status
Simulation time 11816823 ps
CPU time 0.73 seconds
Started May 25 01:02:27 PM PDT 24
Finished May 25 01:02:28 PM PDT 24
Peak memory 205556 kb
Host smart-6ceba9ff-1934-46ee-aff0-bd6585e18dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630610560 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
3630610560
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.3973985626
Short name T152
Test name
Test status
Simulation time 55168631410 ps
CPU time 70 seconds
Started May 25 01:02:27 PM PDT 24
Finished May 25 01:03:37 PM PDT 24
Peak memory 208268 kb
Host smart-3728df77-9efd-4b2c-b784-13fd4d4cb7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973985626 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.3973985626
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.3293077955
Short name T78
Test name
Test status
Simulation time 21372542 ps
CPU time 0.93 seconds
Started May 25 01:02:26 PM PDT 24
Finished May 25 01:02:28 PM PDT 24
Peak memory 205616 kb
Host smart-bd61b312-9f91-443e-972b-f5a012c2aa1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293077955 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
3293077955
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.3455831186
Short name T153
Test name
Test status
Simulation time 14190518 ps
CPU time 0.76 seconds
Started May 25 01:02:28 PM PDT 24
Finished May 25 01:02:29 PM PDT 24
Peak memory 205468 kb
Host smart-7ae4f4ea-5516-45c6-85e9-fcca0d82ee9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455831186 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
3455831186
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.2041604770
Short name T138
Test name
Test status
Simulation time 2220408019 ps
CPU time 17.93 seconds
Started May 25 01:02:26 PM PDT 24
Finished May 25 01:02:45 PM PDT 24
Peak memory 206464 kb
Host smart-97e3d6ad-1cb3-4da3-b831-33007a933920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041604770 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.2041604770
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.112094924
Short name T28
Test name
Test status
Simulation time 23676333 ps
CPU time 0.85 seconds
Started May 25 01:02:29 PM PDT 24
Finished May 25 01:02:30 PM PDT 24
Peak memory 205540 kb
Host smart-5d281239-0bb2-4c86-92b6-0f8ddbd0937b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112094924 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.112094924
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.885967199
Short name T173
Test name
Test status
Simulation time 31320703 ps
CPU time 0.79 seconds
Started May 25 01:02:28 PM PDT 24
Finished May 25 01:02:29 PM PDT 24
Peak memory 205500 kb
Host smart-f73f349f-e02c-44e4-a438-0b3550af0751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885967199 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.885967199
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.829473648
Short name T126
Test name
Test status
Simulation time 14687390475 ps
CPU time 64.56 seconds
Started May 25 01:02:30 PM PDT 24
Finished May 25 01:03:35 PM PDT 24
Peak memory 208304 kb
Host smart-8c99f06a-38db-4995-a487-da3bea76d81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829473648 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.829473648
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.1631544656
Short name T164
Test name
Test status
Simulation time 17337283 ps
CPU time 0.71 seconds
Started May 25 01:02:36 PM PDT 24
Finished May 25 01:02:37 PM PDT 24
Peak memory 205424 kb
Host smart-c8eac958-336f-4c4a-bffb-1dfd49d6f93e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631544656 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
1631544656
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.1568666797
Short name T123
Test name
Test status
Simulation time 799095426 ps
CPU time 16.11 seconds
Started May 25 01:02:38 PM PDT 24
Finished May 25 01:02:55 PM PDT 24
Peak memory 207976 kb
Host smart-6d05db0e-6965-4deb-a64e-657bb42d9c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568666797 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.1568666797
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.3417944683
Short name T79
Test name
Test status
Simulation time 18811741 ps
CPU time 0.79 seconds
Started May 25 01:02:37 PM PDT 24
Finished May 25 01:02:38 PM PDT 24
Peak memory 205456 kb
Host smart-5c716a56-de97-4674-b3e0-861934c6ec91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417944683 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
3417944683
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.4134258841
Short name T4
Test name
Test status
Simulation time 1349191691 ps
CPU time 9.08 seconds
Started May 25 01:02:37 PM PDT 24
Finished May 25 01:02:47 PM PDT 24
Peak memory 208008 kb
Host smart-2fa121f3-8408-48ec-9575-122371b68e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134258841 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.4134258841
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.1469117490
Short name T161
Test name
Test status
Simulation time 38705584 ps
CPU time 0.84 seconds
Started May 25 01:02:07 PM PDT 24
Finished May 25 01:02:08 PM PDT 24
Peak memory 205456 kb
Host smart-4b3afc73-40d0-44a1-abf8-cdbf66580dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469117490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.1
469117490
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.1899256055
Short name T22
Test name
Test status
Simulation time 986281204 ps
CPU time 24.21 seconds
Started May 25 01:02:06 PM PDT 24
Finished May 25 01:02:30 PM PDT 24
Peak memory 232976 kb
Host smart-2702d34f-7e62-44ea-98fd-b3c344dbf4ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899256055 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.1899256055
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.2856204533
Short name T1
Test name
Test status
Simulation time 12867999 ps
CPU time 0.76 seconds
Started May 25 01:02:37 PM PDT 24
Finished May 25 01:02:38 PM PDT 24
Peak memory 205548 kb
Host smart-35e345ef-2363-4a86-bf0c-a7b1be264a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856204533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
2856204533
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.4203229686
Short name T165
Test name
Test status
Simulation time 527739649 ps
CPU time 14.96 seconds
Started May 25 01:02:39 PM PDT 24
Finished May 25 01:02:55 PM PDT 24
Peak memory 207016 kb
Host smart-7ea822f7-a148-41af-b3b9-f37878aae829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203229686 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.4203229686
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.2568035416
Short name T166
Test name
Test status
Simulation time 40289927 ps
CPU time 0.83 seconds
Started May 25 01:02:36 PM PDT 24
Finished May 25 01:02:37 PM PDT 24
Peak memory 205500 kb
Host smart-774ed593-18ad-4ed2-ac3d-9cb34de7168a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568035416 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
2568035416
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.1441593048
Short name T171
Test name
Test status
Simulation time 904847954 ps
CPU time 17.61 seconds
Started May 25 01:02:37 PM PDT 24
Finished May 25 01:02:55 PM PDT 24
Peak memory 207396 kb
Host smart-10b8195e-66d4-40da-852e-c48fa75b38e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441593048 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.1441593048
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.2625580682
Short name T160
Test name
Test status
Simulation time 57452980 ps
CPU time 0.92 seconds
Started May 25 01:02:38 PM PDT 24
Finished May 25 01:02:40 PM PDT 24
Peak memory 205532 kb
Host smart-76abd6a5-1e28-45a3-9c3b-ce39ab50ec33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625580682 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
2625580682
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.4168959289
Short name T121
Test name
Test status
Simulation time 1453886685 ps
CPU time 23.67 seconds
Started May 25 01:02:36 PM PDT 24
Finished May 25 01:03:00 PM PDT 24
Peak memory 206712 kb
Host smart-b6fccf35-7ce6-4f4e-ba38-9c9d2ab36422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168959289 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.4168959289
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.2354391268
Short name T172
Test name
Test status
Simulation time 24780418 ps
CPU time 0.77 seconds
Started May 25 01:02:37 PM PDT 24
Finished May 25 01:02:38 PM PDT 24
Peak memory 205568 kb
Host smart-9dfe85ec-997a-4912-b129-fa2802637c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354391268 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
2354391268
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.1367485538
Short name T2
Test name
Test status
Simulation time 951156366 ps
CPU time 19.24 seconds
Started May 25 01:02:38 PM PDT 24
Finished May 25 01:02:58 PM PDT 24
Peak memory 207452 kb
Host smart-b1bcc9ed-ac5a-42b8-9245-d65aae7d9fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367485538 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.1367485538
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.452382785
Short name T162
Test name
Test status
Simulation time 10105204 ps
CPU time 0.71 seconds
Started May 25 01:02:40 PM PDT 24
Finished May 25 01:02:41 PM PDT 24
Peak memory 205544 kb
Host smart-475eafb1-e6a4-4f84-8201-7b376cf63a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452382785 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.452382785
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.4046920035
Short name T14
Test name
Test status
Simulation time 143126171 ps
CPU time 8.73 seconds
Started May 25 01:02:37 PM PDT 24
Finished May 25 01:02:47 PM PDT 24
Peak memory 206388 kb
Host smart-94028c76-b4c2-4384-9504-450306a1ee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046920035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.4046920035
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.1037358243
Short name T157
Test name
Test status
Simulation time 27229341 ps
CPU time 0.72 seconds
Started May 25 01:02:36 PM PDT 24
Finished May 25 01:02:37 PM PDT 24
Peak memory 205512 kb
Host smart-fd109b0a-1e2b-4e8e-bd98-a3da37f9e5ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037358243 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
1037358243
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.2757961969
Short name T119
Test name
Test status
Simulation time 8064441013 ps
CPU time 30.79 seconds
Started May 25 01:02:36 PM PDT 24
Finished May 25 01:03:08 PM PDT 24
Peak memory 207884 kb
Host smart-6d040015-d618-41d5-9025-fa5056792e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757961969 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.2757961969
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.1924069942
Short name T139
Test name
Test status
Simulation time 86663730 ps
CPU time 0.68 seconds
Started May 25 01:02:35 PM PDT 24
Finished May 25 01:02:37 PM PDT 24
Peak memory 205476 kb
Host smart-a3702ff2-6742-4789-a31c-4f2da8123fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924069942 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
1924069942
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.3077909421
Short name T30
Test name
Test status
Simulation time 617053493 ps
CPU time 17.69 seconds
Started May 25 01:02:36 PM PDT 24
Finished May 25 01:02:54 PM PDT 24
Peak memory 207464 kb
Host smart-d511b707-3843-4b99-889a-aa7f660272e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077909421 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.3077909421
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.3354874713
Short name T144
Test name
Test status
Simulation time 80909437 ps
CPU time 0.73 seconds
Started May 25 01:02:39 PM PDT 24
Finished May 25 01:02:40 PM PDT 24
Peak memory 205556 kb
Host smart-bf5d1f73-3a32-4b2f-86bf-19da715e022a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354874713 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
3354874713
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3162612562
Short name T85
Test name
Test status
Simulation time 913613276 ps
CPU time 20.2 seconds
Started May 25 01:02:39 PM PDT 24
Finished May 25 01:03:00 PM PDT 24
Peak memory 207868 kb
Host smart-efba396f-e6e2-4e3e-9e62-f66b9d651c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162612562 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3162612562
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.90418504
Short name T29
Test name
Test status
Simulation time 35913462 ps
CPU time 0.72 seconds
Started May 25 01:02:37 PM PDT 24
Finished May 25 01:02:38 PM PDT 24
Peak memory 205488 kb
Host smart-e83a27c9-382c-487d-ac08-bd19fd28c6ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90418504 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.90418504
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.3265830036
Short name T174
Test name
Test status
Simulation time 14610445 ps
CPU time 0.73 seconds
Started May 25 01:02:38 PM PDT 24
Finished May 25 01:02:39 PM PDT 24
Peak memory 205540 kb
Host smart-bf0193bb-af72-4665-8a6c-aa06c7b3d315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265830036 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
3265830036
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.687010177
Short name T120
Test name
Test status
Simulation time 250910362 ps
CPU time 12.71 seconds
Started May 25 01:02:37 PM PDT 24
Finished May 25 01:02:51 PM PDT 24
Peak memory 207464 kb
Host smart-6b174607-2343-4968-8719-d04b8f3b73b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687010177 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.687010177
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.2207659787
Short name T77
Test name
Test status
Simulation time 56548640 ps
CPU time 0.78 seconds
Started May 25 01:02:09 PM PDT 24
Finished May 25 01:02:10 PM PDT 24
Peak memory 205468 kb
Host smart-bfdf422b-0250-4629-aa1b-85a3c59495c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207659787 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.2
207659787
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.3694354799
Short name T124
Test name
Test status
Simulation time 13511111798 ps
CPU time 108.17 seconds
Started May 25 01:02:07 PM PDT 24
Finished May 25 01:03:56 PM PDT 24
Peak memory 208056 kb
Host smart-f84e55b4-59c2-4589-8266-cd527f06ea0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694354799 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.3694354799
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.3874675454
Short name T133
Test name
Test status
Simulation time 26542249 ps
CPU time 0.92 seconds
Started May 25 01:02:07 PM PDT 24
Finished May 25 01:02:09 PM PDT 24
Peak memory 205488 kb
Host smart-f1c05ade-fcdd-40a4-8af0-8250db35731e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874675454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.3
874675454
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.3859340991
Short name T141
Test name
Test status
Simulation time 8496058037 ps
CPU time 25.57 seconds
Started May 25 01:02:08 PM PDT 24
Finished May 25 01:02:35 PM PDT 24
Peak memory 207852 kb
Host smart-b1babc53-75ee-4469-9c14-7cd5948dab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859340991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.3859340991
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.998148008
Short name T154
Test name
Test status
Simulation time 99754908 ps
CPU time 1.09 seconds
Started May 25 01:02:07 PM PDT 24
Finished May 25 01:02:09 PM PDT 24
Peak memory 205696 kb
Host smart-5c60ee16-12b4-4dc0-9cf9-97238e8c6c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998148008 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.998148008
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.3596157296
Short name T23
Test name
Test status
Simulation time 2390395921 ps
CPU time 23.48 seconds
Started May 25 01:02:09 PM PDT 24
Finished May 25 01:02:33 PM PDT 24
Peak memory 206772 kb
Host smart-f7213c66-200b-4021-815b-d53a1953da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596157296 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.3596157296
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.4135528768
Short name T75
Test name
Test status
Simulation time 47885578 ps
CPU time 0.7 seconds
Started May 25 01:02:09 PM PDT 24
Finished May 25 01:02:11 PM PDT 24
Peak memory 205528 kb
Host smart-599973c5-1c2f-46db-8078-854ce2e48421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135528768 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.4
135528768
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.1983477788
Short name T137
Test name
Test status
Simulation time 149160926 ps
CPU time 0.67 seconds
Started May 25 01:02:06 PM PDT 24
Finished May 25 01:02:08 PM PDT 24
Peak memory 205424 kb
Host smart-1d7f2405-87e1-4a73-9f02-d148103b4a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983477788 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.1
983477788
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.3036304808
Short name T82
Test name
Test status
Simulation time 2899518492 ps
CPU time 20.07 seconds
Started May 25 01:02:08 PM PDT 24
Finished May 25 01:02:29 PM PDT 24
Peak memory 208300 kb
Host smart-2428a1b3-1a1d-409a-84f0-c23898184a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036304808 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.3036304808
Directory /workspace/9.keymgr_dpe_smoke/latest
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