Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.23 97.60 90.51 57.40 76.92 94.97 98.34 17.85


Total test records in report: 310
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T256 /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.2783367491 Jun 01 01:31:29 PM PDT 24 Jun 01 01:31:33 PM PDT 24 378052828 ps
T257 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.599519333 Jun 01 01:31:48 PM PDT 24 Jun 01 01:31:50 PM PDT 24 48966454 ps
T258 /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3843086116 Jun 01 01:31:59 PM PDT 24 Jun 01 01:32:01 PM PDT 24 19255820 ps
T259 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.711306801 Jun 01 01:31:33 PM PDT 24 Jun 01 01:31:34 PM PDT 24 46134143 ps
T260 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.2586791390 Jun 01 01:31:21 PM PDT 24 Jun 01 01:31:22 PM PDT 24 15221636 ps
T261 /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.1717062555 Jun 01 01:31:34 PM PDT 24 Jun 01 01:31:36 PM PDT 24 12082121 ps
T262 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2242088089 Jun 01 01:31:49 PM PDT 24 Jun 01 01:31:52 PM PDT 24 130406491 ps
T65 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.2019366386 Jun 01 01:31:25 PM PDT 24 Jun 01 01:31:32 PM PDT 24 1467146360 ps
T263 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.1154804214 Jun 01 01:31:19 PM PDT 24 Jun 01 01:31:24 PM PDT 24 446113889 ps
T264 /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.3048788900 Jun 01 01:31:19 PM PDT 24 Jun 01 01:31:20 PM PDT 24 8669529 ps
T265 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1554406651 Jun 01 01:31:05 PM PDT 24 Jun 01 01:31:06 PM PDT 24 59397972 ps
T266 /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.2586673996 Jun 01 01:31:57 PM PDT 24 Jun 01 01:31:59 PM PDT 24 16131726 ps
T267 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.509436004 Jun 01 01:31:04 PM PDT 24 Jun 01 01:31:07 PM PDT 24 201539999 ps
T268 /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.4173943854 Jun 01 01:31:42 PM PDT 24 Jun 01 01:31:44 PM PDT 24 29566605 ps
T269 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.265489618 Jun 01 01:31:53 PM PDT 24 Jun 01 01:31:58 PM PDT 24 287610394 ps
T67 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.1949240435 Jun 01 01:31:34 PM PDT 24 Jun 01 01:31:38 PM PDT 24 216155173 ps
T270 /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.469530731 Jun 01 01:31:52 PM PDT 24 Jun 01 01:31:54 PM PDT 24 14109450 ps
T271 /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.2959549816 Jun 01 01:31:27 PM PDT 24 Jun 01 01:31:28 PM PDT 24 81926721 ps
T272 /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3850929109 Jun 01 01:31:57 PM PDT 24 Jun 01 01:31:58 PM PDT 24 157680899 ps
T273 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.3142402904 Jun 01 01:31:51 PM PDT 24 Jun 01 01:31:53 PM PDT 24 53533546 ps
T274 /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.188895160 Jun 01 01:31:58 PM PDT 24 Jun 01 01:31:59 PM PDT 24 11332775 ps
T275 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.3038029335 Jun 01 01:31:19 PM PDT 24 Jun 01 01:31:21 PM PDT 24 60077795 ps
T276 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2880648918 Jun 01 01:31:11 PM PDT 24 Jun 01 01:31:13 PM PDT 24 36802633 ps
T277 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.1323456776 Jun 01 01:31:34 PM PDT 24 Jun 01 01:31:36 PM PDT 24 126127048 ps
T278 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1456529705 Jun 01 01:31:51 PM PDT 24 Jun 01 01:31:55 PM PDT 24 126491697 ps
T60 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.3969105545 Jun 01 01:31:51 PM PDT 24 Jun 01 01:31:57 PM PDT 24 291737929 ps
T279 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3944191813 Jun 01 01:31:41 PM PDT 24 Jun 01 01:31:42 PM PDT 24 27455887 ps
T280 /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2340998336 Jun 01 01:31:29 PM PDT 24 Jun 01 01:31:38 PM PDT 24 474871896 ps
T281 /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.1906840582 Jun 01 01:31:12 PM PDT 24 Jun 01 01:31:13 PM PDT 24 33814946 ps
T63 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3425877453 Jun 01 01:31:27 PM PDT 24 Jun 01 01:31:32 PM PDT 24 100639478 ps
T282 /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.3294159247 Jun 01 01:31:59 PM PDT 24 Jun 01 01:32:01 PM PDT 24 43781726 ps
T283 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.2120593126 Jun 01 01:31:34 PM PDT 24 Jun 01 01:31:36 PM PDT 24 51779865 ps
T284 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2899166860 Jun 01 01:31:15 PM PDT 24 Jun 01 01:31:17 PM PDT 24 28892666 ps
T285 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.30659951 Jun 01 01:31:42 PM PDT 24 Jun 01 01:31:44 PM PDT 24 83173790 ps
T68 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.2761847846 Jun 01 01:31:11 PM PDT 24 Jun 01 01:31:13 PM PDT 24 50777332 ps
T286 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.156820430 Jun 01 01:31:27 PM PDT 24 Jun 01 01:31:29 PM PDT 24 37632571 ps
T287 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3049895048 Jun 01 01:31:26 PM PDT 24 Jun 01 01:31:36 PM PDT 24 848807141 ps
T288 /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1408096334 Jun 01 01:31:49 PM PDT 24 Jun 01 01:31:51 PM PDT 24 167318594 ps
T289 /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.3686394267 Jun 01 01:31:57 PM PDT 24 Jun 01 01:32:00 PM PDT 24 53587258 ps
T290 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3909938140 Jun 01 01:31:12 PM PDT 24 Jun 01 01:31:15 PM PDT 24 676297183 ps
T291 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.484716780 Jun 01 01:31:55 PM PDT 24 Jun 01 01:31:57 PM PDT 24 29673976 ps
T292 /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.2138510900 Jun 01 01:31:58 PM PDT 24 Jun 01 01:32:00 PM PDT 24 9437182 ps
T293 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.3458661164 Jun 01 01:31:43 PM PDT 24 Jun 01 01:31:45 PM PDT 24 77967390 ps
T294 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.4047183540 Jun 01 01:31:15 PM PDT 24 Jun 01 01:31:18 PM PDT 24 444520574 ps
T295 /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2327738647 Jun 01 01:31:17 PM PDT 24 Jun 01 01:31:21 PM PDT 24 79858130 ps
T296 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3632137624 Jun 01 01:31:34 PM PDT 24 Jun 01 01:31:39 PM PDT 24 213276022 ps
T297 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.3236424092 Jun 01 01:31:54 PM PDT 24 Jun 01 01:31:56 PM PDT 24 13295283 ps
T298 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.2254299878 Jun 01 01:31:34 PM PDT 24 Jun 01 01:31:40 PM PDT 24 332538214 ps
T299 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.1330204873 Jun 01 01:31:13 PM PDT 24 Jun 01 01:31:16 PM PDT 24 710184384 ps
T300 /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.148051281 Jun 01 01:31:30 PM PDT 24 Jun 01 01:31:33 PM PDT 24 152166589 ps
T301 /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.4164837330 Jun 01 01:31:59 PM PDT 24 Jun 01 01:32:01 PM PDT 24 9965159 ps
T302 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1472189979 Jun 01 01:31:20 PM PDT 24 Jun 01 01:31:22 PM PDT 24 21451843 ps
T303 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.746403115 Jun 01 01:31:13 PM PDT 24 Jun 01 01:31:14 PM PDT 24 14346638 ps
T304 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.2576617999 Jun 01 01:31:41 PM PDT 24 Jun 01 01:31:43 PM PDT 24 107057781 ps
T305 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.830989234 Jun 01 01:31:05 PM PDT 24 Jun 01 01:31:07 PM PDT 24 14672017 ps
T306 /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2513833404 Jun 01 01:31:33 PM PDT 24 Jun 01 01:31:36 PM PDT 24 346721962 ps
T307 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.71094610 Jun 01 01:31:40 PM PDT 24 Jun 01 01:31:45 PM PDT 24 680000539 ps
T308 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.1654963120 Jun 01 01:31:47 PM PDT 24 Jun 01 01:31:50 PM PDT 24 371154887 ps
T309 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.2210193167 Jun 01 01:31:20 PM PDT 24 Jun 01 01:31:22 PM PDT 24 36588732 ps
T310 /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.3469989618 Jun 01 01:31:49 PM PDT 24 Jun 01 01:31:51 PM PDT 24 238306352 ps

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.1924430319
Short name T3
Test name
Test status
Simulation time 549152047 ps
CPU time 17.47 seconds
Started Jun 01 01:31:00 PM PDT 24
Finished Jun 01 01:31:17 PM PDT 24
Peak memory 208272 kb
Host smart-08aa8817-fe2a-4ff2-b279-7715a45b0ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924430319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.1924430319
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.4082674809
Short name T7
Test name
Test status
Simulation time 347613405 ps
CPU time 11.58 seconds
Started Jun 01 01:30:23 PM PDT 24
Finished Jun 01 01:30:35 PM PDT 24
Peak memory 228848 kb
Host smart-bf6f9979-5fcc-4db7-9e5a-d381241f54a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082674809 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.4082674809
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.2498584142
Short name T87
Test name
Test status
Simulation time 54627699 ps
CPU time 1.49 seconds
Started Jun 01 01:31:27 PM PDT 24
Finished Jun 01 01:31:30 PM PDT 24
Peak memory 204348 kb
Host smart-029be3c0-ba9b-4576-be61-04145ec5dc13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498584142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.2498584142
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.2735698272
Short name T48
Test name
Test status
Simulation time 474311564 ps
CPU time 2.84 seconds
Started Jun 01 01:31:05 PM PDT 24
Finished Jun 01 01:31:09 PM PDT 24
Peak memory 216192 kb
Host smart-8f047b37-5860-4664-85d8-2cf1df0a9b64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735698272 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.2
735698272
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.4132940742
Short name T71
Test name
Test status
Simulation time 130524798 ps
CPU time 5.55 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:40 PM PDT 24
Peak memory 213072 kb
Host smart-b55c6ff0-ed8a-4c26-af3e-b327d99da45e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132940742 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.4132940742
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.3534472402
Short name T23
Test name
Test status
Simulation time 6446021893 ps
CPU time 24.12 seconds
Started Jun 01 01:30:36 PM PDT 24
Finished Jun 01 01:31:01 PM PDT 24
Peak memory 207564 kb
Host smart-d2bbc052-c402-4158-90c2-db674eed6ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534472402 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.3534472402
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.2155431016
Short name T2
Test name
Test status
Simulation time 8747787 ps
CPU time 0.72 seconds
Started Jun 01 01:30:26 PM PDT 24
Finished Jun 01 01:30:27 PM PDT 24
Peak memory 205388 kb
Host smart-ffc8f993-8ce1-4d9e-971c-d9ddb2b33895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155431016 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.2
155431016
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.1332658507
Short name T98
Test name
Test status
Simulation time 25264558 ps
CPU time 0.72 seconds
Started Jun 01 01:31:48 PM PDT 24
Finished Jun 01 01:31:49 PM PDT 24
Peak memory 204340 kb
Host smart-834d3372-d4a0-45ef-bb60-6fe980b70f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332658507 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
1332658507
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.1930202777
Short name T64
Test name
Test status
Simulation time 107818059 ps
CPU time 2.77 seconds
Started Jun 01 01:31:48 PM PDT 24
Finished Jun 01 01:31:52 PM PDT 24
Peak memory 212816 kb
Host smart-b24e4eba-e700-4a0f-a427-f1e5c981fc17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930202777 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.1930202777
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.936971818
Short name T9
Test name
Test status
Simulation time 3933682054 ps
CPU time 19.98 seconds
Started Jun 01 01:30:50 PM PDT 24
Finished Jun 01 01:31:10 PM PDT 24
Peak memory 208616 kb
Host smart-5f3af5c9-5c48-4864-a849-829495009808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936971818 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.936971818
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1794886676
Short name T84
Test name
Test status
Simulation time 882497539 ps
CPU time 5.12 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:47 PM PDT 24
Peak memory 212868 kb
Host smart-9dbe3c7e-fdc8-4a82-b443-3151fae42e50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794886676 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1794886676
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.2774832999
Short name T104
Test name
Test status
Simulation time 960348566 ps
CPU time 3.52 seconds
Started Jun 01 01:31:06 PM PDT 24
Finished Jun 01 01:31:10 PM PDT 24
Peak memory 215780 kb
Host smart-999082fe-7515-433f-9ec1-a96c784046ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774832999 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.2
774832999
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.1876607996
Short name T21
Test name
Test status
Simulation time 163900024 ps
CPU time 4.68 seconds
Started Jun 01 01:31:20 PM PDT 24
Finished Jun 01 01:31:25 PM PDT 24
Peak memory 204576 kb
Host smart-41c1ce51-6d09-4b9c-af11-6e80f57d0f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876607996 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.1876607996
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3425877453
Short name T63
Test name
Test status
Simulation time 100639478 ps
CPU time 3.66 seconds
Started Jun 01 01:31:27 PM PDT 24
Finished Jun 01 01:31:32 PM PDT 24
Peak memory 212592 kb
Host smart-e4b07f0f-7d9b-4170-baea-979af5f07a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425877453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.3425877453
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.76204983
Short name T10
Test name
Test status
Simulation time 58010577484 ps
CPU time 69.33 seconds
Started Jun 01 01:30:37 PM PDT 24
Finished Jun 01 01:31:47 PM PDT 24
Peak memory 207892 kb
Host smart-c92459b2-b6f0-47ce-9253-712cbe6b92e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76204983 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.76204983
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.2607795167
Short name T57
Test name
Test status
Simulation time 381946245 ps
CPU time 5.38 seconds
Started Jun 01 01:31:40 PM PDT 24
Finished Jun 01 01:31:46 PM PDT 24
Peak memory 212644 kb
Host smart-190e606f-90a2-4224-be9c-578983db3d67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607795167 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.2607795167
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.1896780128
Short name T56
Test name
Test status
Simulation time 262411817 ps
CPU time 4 seconds
Started Jun 01 01:31:35 PM PDT 24
Finished Jun 01 01:31:40 PM PDT 24
Peak memory 213000 kb
Host smart-ec5ec161-4370-4c30-836b-bece1be760a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896780128 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.1896780128
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.2653647732
Short name T6
Test name
Test status
Simulation time 451371320 ps
CPU time 10.03 seconds
Started Jun 01 01:30:25 PM PDT 24
Finished Jun 01 01:30:35 PM PDT 24
Peak memory 233720 kb
Host smart-c9f7858e-2aef-4045-bf09-7427ffea38d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653647732 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.2653647732
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.2629701037
Short name T33
Test name
Test status
Simulation time 2712061103 ps
CPU time 18.91 seconds
Started Jun 01 01:30:32 PM PDT 24
Finished Jun 01 01:30:52 PM PDT 24
Peak memory 206596 kb
Host smart-739f9f2d-4478-4e74-a520-7af1bcb3d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629701037 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.2629701037
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.3969105545
Short name T60
Test name
Test status
Simulation time 291737929 ps
CPU time 5.08 seconds
Started Jun 01 01:31:51 PM PDT 24
Finished Jun 01 01:31:57 PM PDT 24
Peak memory 213792 kb
Host smart-92a424d0-3525-45cb-bbfb-8f3534b8a130
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969105545 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.3969105545
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.2761847846
Short name T68
Test name
Test status
Simulation time 50777332 ps
CPU time 2.37 seconds
Started Jun 01 01:31:11 PM PDT 24
Finished Jun 01 01:31:13 PM PDT 24
Peak memory 212700 kb
Host smart-77223822-2877-4d00-aed1-ec580534f99d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761847846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.2761847846
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.3947964855
Short name T76
Test name
Test status
Simulation time 126792124 ps
CPU time 2.31 seconds
Started Jun 01 01:31:36 PM PDT 24
Finished Jun 01 01:31:38 PM PDT 24
Peak memory 219212 kb
Host smart-a780d0ef-e82f-4e9b-a9ae-b4a4202c58ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947964855 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.3947964855
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.1399257545
Short name T13
Test name
Test status
Simulation time 2007807641 ps
CPU time 18.28 seconds
Started Jun 01 01:30:25 PM PDT 24
Finished Jun 01 01:30:44 PM PDT 24
Peak memory 207336 kb
Host smart-a9ca642a-d707-4de8-a3be-ac90df49c667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399257545 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.1399257545
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.2571291103
Short name T4
Test name
Test status
Simulation time 885526466 ps
CPU time 15.84 seconds
Started Jun 01 01:30:25 PM PDT 24
Finished Jun 01 01:30:41 PM PDT 24
Peak memory 206420 kb
Host smart-efe2fe82-3ef8-4411-8722-12ecee7d97e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571291103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.2571291103
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.2525036785
Short name T91
Test name
Test status
Simulation time 1293892940 ps
CPU time 20.87 seconds
Started Jun 01 01:30:32 PM PDT 24
Finished Jun 01 01:30:53 PM PDT 24
Peak memory 208116 kb
Host smart-2dda46d4-3bd3-4de3-9690-a691922d4540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525036785 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.2525036785
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.1889441340
Short name T11
Test name
Test status
Simulation time 2856048553 ps
CPU time 16.29 seconds
Started Jun 01 01:30:30 PM PDT 24
Finished Jun 01 01:30:47 PM PDT 24
Peak memory 208292 kb
Host smart-b339207b-5a1a-40cf-8731-cc4b3edbed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889441340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.1889441340
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.4000899216
Short name T95
Test name
Test status
Simulation time 755986717 ps
CPU time 14.1 seconds
Started Jun 01 01:30:38 PM PDT 24
Finished Jun 01 01:30:53 PM PDT 24
Peak memory 208184 kb
Host smart-a20feef4-38e6-451e-ba66-3e3d4630a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000899216 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.4000899216
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.943196694
Short name T113
Test name
Test status
Simulation time 7318207505 ps
CPU time 27.3 seconds
Started Jun 01 01:30:44 PM PDT 24
Finished Jun 01 01:31:11 PM PDT 24
Peak memory 208432 kb
Host smart-89caeede-b83b-433a-b076-9bd0ebe3d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943196694 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.943196694
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.799791827
Short name T114
Test name
Test status
Simulation time 1228232998 ps
CPU time 19.72 seconds
Started Jun 01 01:30:47 PM PDT 24
Finished Jun 01 01:31:07 PM PDT 24
Peak memory 208300 kb
Host smart-3caa3ea3-1e26-434b-b2c8-178e8cc2bfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799791827 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.799791827
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.4187813359
Short name T116
Test name
Test status
Simulation time 2758040158 ps
CPU time 21.49 seconds
Started Jun 01 01:30:47 PM PDT 24
Finished Jun 01 01:31:09 PM PDT 24
Peak memory 208296 kb
Host smart-4eafb2f9-e059-4b0b-91dc-b648616ed20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187813359 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.4187813359
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.3435276323
Short name T36
Test name
Test status
Simulation time 2479586387 ps
CPU time 21.2 seconds
Started Jun 01 01:30:42 PM PDT 24
Finished Jun 01 01:31:04 PM PDT 24
Peak memory 207856 kb
Host smart-e3f6f450-11b1-48a1-8c7b-673923603934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435276323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.3435276323
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.2711357106
Short name T90
Test name
Test status
Simulation time 682990102 ps
CPU time 16.39 seconds
Started Jun 01 01:31:00 PM PDT 24
Finished Jun 01 01:31:16 PM PDT 24
Peak memory 206400 kb
Host smart-19571639-a50e-4a15-a59c-ef08e0299fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711357106 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.2711357106
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.1329161395
Short name T110
Test name
Test status
Simulation time 3692659821 ps
CPU time 18.53 seconds
Started Jun 01 01:30:58 PM PDT 24
Finished Jun 01 01:31:17 PM PDT 24
Peak memory 208264 kb
Host smart-2b87938b-cacd-42e9-b589-f357ba399e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329161395 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.1329161395
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.1277037964
Short name T35
Test name
Test status
Simulation time 4335524108 ps
CPU time 25.15 seconds
Started Jun 01 01:30:23 PM PDT 24
Finished Jun 01 01:30:49 PM PDT 24
Peak memory 206576 kb
Host smart-7d598bea-7093-49fd-9e08-031604e90070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277037964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.1277037964
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.2202382193
Short name T112
Test name
Test status
Simulation time 1252110595 ps
CPU time 19.04 seconds
Started Jun 01 01:30:19 PM PDT 24
Finished Jun 01 01:30:39 PM PDT 24
Peak memory 208028 kb
Host smart-049969f0-5326-4e74-aeca-6bdf5a078983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202382193 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.2202382193
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.3537478717
Short name T202
Test name
Test status
Simulation time 45014224 ps
CPU time 2.65 seconds
Started Jun 01 01:31:05 PM PDT 24
Finished Jun 01 01:31:08 PM PDT 24
Peak memory 204576 kb
Host smart-16a142af-433c-496b-b0e7-dd46218fce4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537478717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.3537478717
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.283993773
Short name T102
Test name
Test status
Simulation time 394953711 ps
CPU time 6.56 seconds
Started Jun 01 01:31:14 PM PDT 24
Finished Jun 01 01:31:21 PM PDT 24
Peak memory 204516 kb
Host smart-f71ca10c-ea96-4908-8e80-26e4c132c3af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283993773 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_bit_bash.283993773
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2936345743
Short name T242
Test name
Test status
Simulation time 16260712 ps
CPU time 0.83 seconds
Started Jun 01 01:31:05 PM PDT 24
Finished Jun 01 01:31:07 PM PDT 24
Peak memory 204424 kb
Host smart-361c4e8c-e685-4885-a81b-90d4d100ef4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936345743 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.2936345743
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.2744067767
Short name T233
Test name
Test status
Simulation time 36441435 ps
CPU time 1.02 seconds
Started Jun 01 01:31:09 PM PDT 24
Finished Jun 01 01:31:10 PM PDT 24
Peak memory 204452 kb
Host smart-1d77c3fe-0a10-4fb0-aa5a-0ea0fd1f979b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744067767 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.2744067767
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.830989234
Short name T305
Test name
Test status
Simulation time 14672017 ps
CPU time 0.89 seconds
Started Jun 01 01:31:05 PM PDT 24
Finished Jun 01 01:31:07 PM PDT 24
Peak memory 204312 kb
Host smart-df89edc7-c179-4125-9faa-ab29a57f963d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830989234 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.830989234
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2089521103
Short name T99
Test name
Test status
Simulation time 13306070 ps
CPU time 0.76 seconds
Started Jun 01 01:31:10 PM PDT 24
Finished Jun 01 01:31:12 PM PDT 24
Peak memory 204164 kb
Host smart-a5b5522f-294c-4843-8107-7d6b92d2bf7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089521103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.2
089521103
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.2528983977
Short name T53
Test name
Test status
Simulation time 37614619 ps
CPU time 1.89 seconds
Started Jun 01 01:31:08 PM PDT 24
Finished Jun 01 01:31:10 PM PDT 24
Peak memory 204488 kb
Host smart-f81c2895-38c6-4298-ba04-b09a0cb1a100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528983977 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.2528983977
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.3564915748
Short name T190
Test name
Test status
Simulation time 59848830 ps
CPU time 2.03 seconds
Started Jun 01 01:31:14 PM PDT 24
Finished Jun 01 01:31:17 PM PDT 24
Peak memory 212968 kb
Host smart-88943c97-ae24-43b7-bb67-8d1e04f1b428
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564915748 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.3564915748
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2146597518
Short name T232
Test name
Test status
Simulation time 465887273 ps
CPU time 5.21 seconds
Started Jun 01 01:31:05 PM PDT 24
Finished Jun 01 01:31:11 PM PDT 24
Peak memory 212924 kb
Host smart-0be45fa0-162e-42a6-b09c-d08a74ffcf85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146597518 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2146597518
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.509436004
Short name T267
Test name
Test status
Simulation time 201539999 ps
CPU time 2.51 seconds
Started Jun 01 01:31:04 PM PDT 24
Finished Jun 01 01:31:07 PM PDT 24
Peak memory 204532 kb
Host smart-3a055e9a-dfc0-4d1a-afff-c80c1ff87608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509436004 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_
tl_intg_err.509436004
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.4009564302
Short name T243
Test name
Test status
Simulation time 119516820 ps
CPU time 4.49 seconds
Started Jun 01 01:31:08 PM PDT 24
Finished Jun 01 01:31:13 PM PDT 24
Peak memory 204364 kb
Host smart-77df271a-2f69-4398-9201-fa70bf7f3e50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009564302 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.4009564302
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.3458079895
Short name T170
Test name
Test status
Simulation time 95501052 ps
CPU time 4.4 seconds
Started Jun 01 01:31:05 PM PDT 24
Finished Jun 01 01:31:10 PM PDT 24
Peak memory 204548 kb
Host smart-b290ece4-274d-40f6-b899-7093d34832af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458079895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.3458079895
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1554406651
Short name T265
Test name
Test status
Simulation time 59397972 ps
CPU time 0.85 seconds
Started Jun 01 01:31:05 PM PDT 24
Finished Jun 01 01:31:06 PM PDT 24
Peak memory 204448 kb
Host smart-75c4da5f-b273-4650-9eb6-6657f0be64b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554406651 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.1554406651
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.3164763334
Short name T171
Test name
Test status
Simulation time 36391599 ps
CPU time 1.61 seconds
Started Jun 01 01:31:11 PM PDT 24
Finished Jun 01 01:31:13 PM PDT 24
Peak memory 212732 kb
Host smart-3963213f-ef34-42e5-a21c-1aad9080abe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164763334 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.3164763334
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.2374519092
Short name T238
Test name
Test status
Simulation time 15284105 ps
CPU time 0.9 seconds
Started Jun 01 01:31:09 PM PDT 24
Finished Jun 01 01:31:11 PM PDT 24
Peak memory 204320 kb
Host smart-588c0205-dc42-4e8a-bd52-4ba70895e066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374519092 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.2
374519092
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.2080651363
Short name T185
Test name
Test status
Simulation time 13327170 ps
CPU time 0.87 seconds
Started Jun 01 01:31:13 PM PDT 24
Finished Jun 01 01:31:15 PM PDT 24
Peak memory 204276 kb
Host smart-902c9146-fe94-4628-bdd2-b51efd7dd101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080651363 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.2
080651363
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.1752404057
Short name T228
Test name
Test status
Simulation time 486814685 ps
CPU time 2.09 seconds
Started Jun 01 01:31:13 PM PDT 24
Finished Jun 01 01:31:15 PM PDT 24
Peak memory 204448 kb
Host smart-72bd3a5d-f8db-4221-b4d3-27e931be001e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752404057 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.1752404057
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.430095455
Short name T213
Test name
Test status
Simulation time 206617306 ps
CPU time 3.5 seconds
Started Jun 01 01:31:11 PM PDT 24
Finished Jun 01 01:31:14 PM PDT 24
Peak memory 212896 kb
Host smart-c86b46f4-f9b1-46ed-b442-beddea12ebb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430095455 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymg
r_dpe_shadow_reg_errors.430095455
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2835166673
Short name T198
Test name
Test status
Simulation time 158173294 ps
CPU time 6.08 seconds
Started Jun 01 01:31:09 PM PDT 24
Finished Jun 01 01:31:15 PM PDT 24
Peak memory 213080 kb
Host smart-6ceb947f-768f-43f6-bf36-f48103d40f0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835166673 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2835166673
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.3754927430
Short name T62
Test name
Test status
Simulation time 429749793 ps
CPU time 2.57 seconds
Started Jun 01 01:31:07 PM PDT 24
Finished Jun 01 01:31:10 PM PDT 24
Peak memory 212760 kb
Host smart-d72df51d-883b-4b57-a8cc-469432b2a961
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754927430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.3754927430
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.2827429310
Short name T226
Test name
Test status
Simulation time 10370192 ps
CPU time 0.87 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:35 PM PDT 24
Peak memory 204428 kb
Host smart-4f79888e-cf43-4052-9c9b-6ef9fd9e0320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827429310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
2827429310
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.1717062555
Short name T261
Test name
Test status
Simulation time 12082121 ps
CPU time 0.72 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:36 PM PDT 24
Peak memory 204300 kb
Host smart-4b24fe11-bb31-47cc-8bcc-adf7536096a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717062555 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
1717062555
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.1882103862
Short name T224
Test name
Test status
Simulation time 19585340 ps
CPU time 1.43 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:36 PM PDT 24
Peak memory 204496 kb
Host smart-c42b0f96-2de5-4fc5-9321-807f7fd51e00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882103862 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.1882103862
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.2120593126
Short name T283
Test name
Test status
Simulation time 51779865 ps
CPU time 1.31 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:36 PM PDT 24
Peak memory 213032 kb
Host smart-debbf3e0-6cf7-4077-b21e-ea44ab33222a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120593126 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.2120593126
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.2858418269
Short name T41
Test name
Test status
Simulation time 66807384 ps
CPU time 2.17 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:37 PM PDT 24
Peak memory 214768 kb
Host smart-64b5bd0a-402b-44b5-a569-56baefbaa6ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858418269 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
2858418269
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.1949240435
Short name T67
Test name
Test status
Simulation time 216155173 ps
CPU time 3.19 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:38 PM PDT 24
Peak memory 213608 kb
Host smart-cb95aa5a-04e9-43f5-8698-7ac67f741f59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949240435 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.1949240435
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3944191813
Short name T279
Test name
Test status
Simulation time 27455887 ps
CPU time 1.21 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:42 PM PDT 24
Peak memory 212624 kb
Host smart-6a8a1735-c396-48aa-af4b-95f3127ce8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944191813 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.3944191813
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.1832479864
Short name T230
Test name
Test status
Simulation time 192628645 ps
CPU time 1.02 seconds
Started Jun 01 01:31:42 PM PDT 24
Finished Jun 01 01:31:44 PM PDT 24
Peak memory 204392 kb
Host smart-ba2be349-0215-4bf3-84a6-42df207672c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832479864 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
1832479864
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.4173943854
Short name T268
Test name
Test status
Simulation time 29566605 ps
CPU time 0.79 seconds
Started Jun 01 01:31:42 PM PDT 24
Finished Jun 01 01:31:44 PM PDT 24
Peak memory 204368 kb
Host smart-8de38478-0e1e-429e-9430-7ba24a39a213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173943854 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
4173943854
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.3055813064
Short name T189
Test name
Test status
Simulation time 38382479 ps
CPU time 1.64 seconds
Started Jun 01 01:31:46 PM PDT 24
Finished Jun 01 01:31:48 PM PDT 24
Peak memory 204376 kb
Host smart-8826b0b4-2b5b-478e-a2f9-e23c453a870d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055813064 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.3055813064
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1919069028
Short name T74
Test name
Test status
Simulation time 324155128 ps
CPU time 2.73 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:44 PM PDT 24
Peak memory 213004 kb
Host smart-9efaeda3-8b31-4e6d-bcb4-571813060379
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919069028 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.1919069028
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.188339946
Short name T206
Test name
Test status
Simulation time 530307029 ps
CPU time 3.41 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:45 PM PDT 24
Peak memory 212824 kb
Host smart-d866ccd5-f3fd-4b86-a365-fbf22c54cdd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188339946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.188339946
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1960924000
Short name T217
Test name
Test status
Simulation time 58781351 ps
CPU time 1.87 seconds
Started Jun 01 01:31:42 PM PDT 24
Finished Jun 01 01:31:45 PM PDT 24
Peak memory 212740 kb
Host smart-6bdcad86-b559-4b56-89db-6c7749ba59a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960924000 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
1960924000
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.71094610
Short name T307
Test name
Test status
Simulation time 680000539 ps
CPU time 4.88 seconds
Started Jun 01 01:31:40 PM PDT 24
Finished Jun 01 01:31:45 PM PDT 24
Peak memory 212676 kb
Host smart-f645017b-0fb2-4b92-9b14-fd86fa66e18a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71094610 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_
tl_intg_err.71094610
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3808694034
Short name T235
Test name
Test status
Simulation time 25696819 ps
CPU time 0.86 seconds
Started Jun 01 01:31:39 PM PDT 24
Finished Jun 01 01:31:40 PM PDT 24
Peak memory 204288 kb
Host smart-ace60921-3626-42cf-a3d1-55057cc50141
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808694034 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.3808694034
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.4089223087
Short name T192
Test name
Test status
Simulation time 72498302 ps
CPU time 1.3 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:43 PM PDT 24
Peak memory 204520 kb
Host smart-8765520c-5f0e-4656-b01f-01913a9714a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089223087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
4089223087
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.2415803688
Short name T240
Test name
Test status
Simulation time 21124847 ps
CPU time 0.79 seconds
Started Jun 01 01:31:46 PM PDT 24
Finished Jun 01 01:31:47 PM PDT 24
Peak memory 204324 kb
Host smart-1929f358-cadf-4045-abc2-4a21c3f956a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415803688 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
2415803688
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.794482824
Short name T227
Test name
Test status
Simulation time 87125413 ps
CPU time 1.97 seconds
Started Jun 01 01:31:42 PM PDT 24
Finished Jun 01 01:31:45 PM PDT 24
Peak memory 204580 kb
Host smart-5c8f83ad-5db4-4e5a-b985-f493297f82a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794482824 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.k
eymgr_dpe_same_csr_outstanding.794482824
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.918890165
Short name T107
Test name
Test status
Simulation time 342632583 ps
CPU time 2.97 seconds
Started Jun 01 01:31:42 PM PDT 24
Finished Jun 01 01:31:45 PM PDT 24
Peak memory 213016 kb
Host smart-8b325bb3-15ce-4844-87ac-3f4395c6d26a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918890165 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keym
gr_dpe_shadow_reg_errors.918890165
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1959259592
Short name T241
Test name
Test status
Simulation time 114041422 ps
CPU time 3.38 seconds
Started Jun 01 01:31:43 PM PDT 24
Finished Jun 01 01:31:47 PM PDT 24
Peak memory 212984 kb
Host smart-ae8682ab-a67b-4721-860c-31f43f56dbcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959259592 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1959259592
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.30659951
Short name T285
Test name
Test status
Simulation time 83173790 ps
CPU time 1.57 seconds
Started Jun 01 01:31:42 PM PDT 24
Finished Jun 01 01:31:44 PM PDT 24
Peak memory 212608 kb
Host smart-e7f516a1-19d7-491f-8c4a-5974e60dea7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30659951 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.30659951
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.3668726781
Short name T20
Test name
Test status
Simulation time 50849855 ps
CPU time 2.75 seconds
Started Jun 01 01:31:43 PM PDT 24
Finished Jun 01 01:31:47 PM PDT 24
Peak memory 212668 kb
Host smart-83a1222b-0fac-43a3-aeb8-478dea00eef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668726781 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.3668726781
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.3458661164
Short name T293
Test name
Test status
Simulation time 77967390 ps
CPU time 1.61 seconds
Started Jun 01 01:31:43 PM PDT 24
Finished Jun 01 01:31:45 PM PDT 24
Peak memory 212732 kb
Host smart-1a4cab8f-57c2-40ca-ab13-fa17c928cef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458661164 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.3458661164
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1569510606
Short name T225
Test name
Test status
Simulation time 54806321 ps
CPU time 0.98 seconds
Started Jun 01 01:31:44 PM PDT 24
Finished Jun 01 01:31:45 PM PDT 24
Peak memory 204492 kb
Host smart-20efd88d-cd03-482d-80fa-244e702fae39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569510606 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
1569510606
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.3136761614
Short name T172
Test name
Test status
Simulation time 19556820 ps
CPU time 0.68 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:43 PM PDT 24
Peak memory 204320 kb
Host smart-f214cbd0-109e-48f2-a512-bc7277168208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136761614 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
3136761614
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.2146524615
Short name T188
Test name
Test status
Simulation time 38342584 ps
CPU time 1.46 seconds
Started Jun 01 01:31:42 PM PDT 24
Finished Jun 01 01:31:44 PM PDT 24
Peak memory 204460 kb
Host smart-a76aac84-3404-4f20-b585-9d624a2b721c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146524615 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.2146524615
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.2576617999
Short name T304
Test name
Test status
Simulation time 107057781 ps
CPU time 2.34 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:43 PM PDT 24
Peak memory 212984 kb
Host smart-f90055cf-885d-4f2e-9cd3-11bad3072385
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576617999 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.2576617999
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.783654272
Short name T255
Test name
Test status
Simulation time 28556455 ps
CPU time 1.54 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:43 PM PDT 24
Peak memory 212644 kb
Host smart-1b0a7b0a-dbdb-4e01-8250-67414a4fd67b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783654272 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.783654272
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.3200630763
Short name T194
Test name
Test status
Simulation time 39750263 ps
CPU time 1.43 seconds
Started Jun 01 01:31:47 PM PDT 24
Finished Jun 01 01:31:49 PM PDT 24
Peak memory 212628 kb
Host smart-59cb4e06-c265-4c3b-9ccf-2025c663b4a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200630763 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.3200630763
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.1648058098
Short name T83
Test name
Test status
Simulation time 11528662 ps
CPU time 1.14 seconds
Started Jun 01 01:31:42 PM PDT 24
Finished Jun 01 01:31:44 PM PDT 24
Peak memory 204484 kb
Host smart-ec4bb5a8-2d21-4c4f-a7ac-6db0b027bb13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648058098 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
1648058098
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2823839354
Short name T201
Test name
Test status
Simulation time 16487296 ps
CPU time 0.78 seconds
Started Jun 01 01:31:43 PM PDT 24
Finished Jun 01 01:31:44 PM PDT 24
Peak memory 204316 kb
Host smart-d75187ef-4880-48c8-9470-1055743f8cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823839354 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
2823839354
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.3046304439
Short name T105
Test name
Test status
Simulation time 166189345 ps
CPU time 2.32 seconds
Started Jun 01 01:31:42 PM PDT 24
Finished Jun 01 01:31:45 PM PDT 24
Peak memory 204568 kb
Host smart-6aae4cf8-928c-4d56-98b3-323d52473da5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046304439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.3046304439
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.644883779
Short name T254
Test name
Test status
Simulation time 56126782 ps
CPU time 1.6 seconds
Started Jun 01 01:31:46 PM PDT 24
Finished Jun 01 01:31:48 PM PDT 24
Peak memory 212936 kb
Host smart-44bdfb9e-d928-4f57-93f9-f103a25b7347
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644883779 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keym
gr_dpe_shadow_reg_errors.644883779
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3514379638
Short name T253
Test name
Test status
Simulation time 87827227 ps
CPU time 2.44 seconds
Started Jun 01 01:31:43 PM PDT 24
Finished Jun 01 01:31:46 PM PDT 24
Peak memory 212968 kb
Host smart-3ec0e1d7-3db8-4234-839e-3c13fde3cfed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514379638 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3514379638
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.468281782
Short name T55
Test name
Test status
Simulation time 145761560 ps
CPU time 4.66 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:46 PM PDT 24
Peak memory 220288 kb
Host smart-19b6a22d-763f-496b-b094-021c7c2f1182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468281782 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.468281782
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.2224610964
Short name T193
Test name
Test status
Simulation time 99502095 ps
CPU time 2.11 seconds
Started Jun 01 01:31:41 PM PDT 24
Finished Jun 01 01:31:44 PM PDT 24
Peak memory 212576 kb
Host smart-630fea0a-aaa7-493f-ba6b-5a061d4cb9da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224610964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.2224610964
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.2982985487
Short name T96
Test name
Test status
Simulation time 47821198 ps
CPU time 1.13 seconds
Started Jun 01 01:31:50 PM PDT 24
Finished Jun 01 01:31:52 PM PDT 24
Peak memory 204576 kb
Host smart-26e61123-17ff-4321-9e25-fba6e9062166
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982985487 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.2982985487
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.4061105286
Short name T239
Test name
Test status
Simulation time 99257683 ps
CPU time 1.19 seconds
Started Jun 01 01:31:48 PM PDT 24
Finished Jun 01 01:31:50 PM PDT 24
Peak memory 204464 kb
Host smart-6dbded16-cd17-41f1-a1d9-d373068f51de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061105286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
4061105286
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.1422104018
Short name T178
Test name
Test status
Simulation time 74964038 ps
CPU time 1.49 seconds
Started Jun 01 01:31:49 PM PDT 24
Finished Jun 01 01:31:51 PM PDT 24
Peak memory 204468 kb
Host smart-a0eccecc-d7bc-402c-b656-106ae81c939f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422104018 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.1422104018
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.1654963120
Short name T308
Test name
Test status
Simulation time 371154887 ps
CPU time 3.17 seconds
Started Jun 01 01:31:47 PM PDT 24
Finished Jun 01 01:31:50 PM PDT 24
Peak memory 213032 kb
Host smart-d7116342-f2a5-4df4-b22a-53ac0830e82d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654963120 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.1654963120
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.265489618
Short name T269
Test name
Test status
Simulation time 287610394 ps
CPU time 4.15 seconds
Started Jun 01 01:31:53 PM PDT 24
Finished Jun 01 01:31:58 PM PDT 24
Peak memory 217912 kb
Host smart-dd89b8ad-f694-4124-954d-0b42abf75ad8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265489618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.265489618
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.287617842
Short name T106
Test name
Test status
Simulation time 179124043 ps
CPU time 3.8 seconds
Started Jun 01 01:31:49 PM PDT 24
Finished Jun 01 01:31:54 PM PDT 24
Peak memory 213980 kb
Host smart-3d6df364-4bd7-4c03-a409-0e660e0dc5c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287617842 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.287617842
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.4258827320
Short name T69
Test name
Test status
Simulation time 333344416 ps
CPU time 4.15 seconds
Started Jun 01 01:31:48 PM PDT 24
Finished Jun 01 01:31:53 PM PDT 24
Peak memory 212736 kb
Host smart-a8193792-b93a-4602-ae4e-0763ad4095c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258827320 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.4258827320
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.708719698
Short name T211
Test name
Test status
Simulation time 25227411 ps
CPU time 0.94 seconds
Started Jun 01 01:31:55 PM PDT 24
Finished Jun 01 01:31:56 PM PDT 24
Peak memory 204396 kb
Host smart-ef0ebb8e-c711-4b89-ab0a-3509960d2c43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708719698 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.708719698
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1408096334
Short name T288
Test name
Test status
Simulation time 167318594 ps
CPU time 1.1 seconds
Started Jun 01 01:31:49 PM PDT 24
Finished Jun 01 01:31:51 PM PDT 24
Peak memory 204352 kb
Host smart-12b07ba3-380c-4911-8298-0a9f8e91cfad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408096334 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
1408096334
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.1088795840
Short name T221
Test name
Test status
Simulation time 18487636 ps
CPU time 0.7 seconds
Started Jun 01 01:31:50 PM PDT 24
Finished Jun 01 01:31:52 PM PDT 24
Peak memory 204328 kb
Host smart-60ef677a-fa97-4c54-9f36-66c6f4f0b6bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088795840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.
1088795840
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.571313558
Short name T191
Test name
Test status
Simulation time 40730198 ps
CPU time 1.75 seconds
Started Jun 01 01:31:48 PM PDT 24
Finished Jun 01 01:31:50 PM PDT 24
Peak memory 204600 kb
Host smart-09b139a8-5990-47f1-b9fc-e415f1cd3310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571313558 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.k
eymgr_dpe_same_csr_outstanding.571313558
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.1264403542
Short name T248
Test name
Test status
Simulation time 236109268 ps
CPU time 2.04 seconds
Started Jun 01 01:31:50 PM PDT 24
Finished Jun 01 01:31:52 PM PDT 24
Peak memory 212944 kb
Host smart-a126c6b7-50a7-40ee-963c-aed8b9730692
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264403542 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.1264403542
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1451445363
Short name T223
Test name
Test status
Simulation time 492935431 ps
CPU time 5.78 seconds
Started Jun 01 01:31:52 PM PDT 24
Finished Jun 01 01:31:58 PM PDT 24
Peak memory 212980 kb
Host smart-092c78eb-e9a7-4028-bab7-b2c54456f5a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451445363 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1451445363
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2618132265
Short name T229
Test name
Test status
Simulation time 113872119 ps
CPU time 3.04 seconds
Started Jun 01 01:31:48 PM PDT 24
Finished Jun 01 01:31:52 PM PDT 24
Peak memory 212740 kb
Host smart-8d158a96-51de-464d-8da7-14e89006cd9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618132265 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
2618132265
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.2997145988
Short name T66
Test name
Test status
Simulation time 214350718 ps
CPU time 2.71 seconds
Started Jun 01 01:31:48 PM PDT 24
Finished Jun 01 01:31:51 PM PDT 24
Peak memory 212632 kb
Host smart-ee2a41bb-931b-4a23-910b-1342b7538e14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997145988 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.2997145988
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.599519333
Short name T257
Test name
Test status
Simulation time 48966454 ps
CPU time 1.47 seconds
Started Jun 01 01:31:48 PM PDT 24
Finished Jun 01 01:31:50 PM PDT 24
Peak memory 212692 kb
Host smart-4c77001a-e92f-4519-b737-14760a040dbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599519333 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.599519333
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.3236424092
Short name T297
Test name
Test status
Simulation time 13295283 ps
CPU time 1.2 seconds
Started Jun 01 01:31:54 PM PDT 24
Finished Jun 01 01:31:56 PM PDT 24
Peak memory 204332 kb
Host smart-b768eefd-c38d-450b-81a9-ebf69dcdc8e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236424092 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
3236424092
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.4128332269
Short name T51
Test name
Test status
Simulation time 12281953 ps
CPU time 0.7 seconds
Started Jun 01 01:31:49 PM PDT 24
Finished Jun 01 01:31:51 PM PDT 24
Peak memory 204212 kb
Host smart-20c5b045-5a45-4efc-9996-bd5ee88c97fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128332269 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
4128332269
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.3469989618
Short name T310
Test name
Test status
Simulation time 238306352 ps
CPU time 1.84 seconds
Started Jun 01 01:31:49 PM PDT 24
Finished Jun 01 01:31:51 PM PDT 24
Peak memory 204508 kb
Host smart-275bb559-8c4c-411b-8c5d-331f3749e975
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469989618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.3469989618
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.1089120314
Short name T247
Test name
Test status
Simulation time 252884985 ps
CPU time 1.73 seconds
Started Jun 01 01:31:51 PM PDT 24
Finished Jun 01 01:31:53 PM PDT 24
Peak memory 212892 kb
Host smart-97427a6c-390c-4ceb-bb77-563fb8e3fd99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089120314 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.1089120314
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3024023026
Short name T73
Test name
Test status
Simulation time 179081988 ps
CPU time 5.9 seconds
Started Jun 01 01:31:51 PM PDT 24
Finished Jun 01 01:31:57 PM PDT 24
Peak memory 212924 kb
Host smart-5a8f2ca1-0590-419c-b81d-f7a871aa964b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024023026 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3024023026
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.288525305
Short name T61
Test name
Test status
Simulation time 541423305 ps
CPU time 4.51 seconds
Started Jun 01 01:31:49 PM PDT 24
Finished Jun 01 01:31:55 PM PDT 24
Peak memory 212676 kb
Host smart-95d35ea2-572b-4f1e-9d2f-8dc59a0e34aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288525305 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.288525305
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.3142402904
Short name T273
Test name
Test status
Simulation time 53533546 ps
CPU time 1.5 seconds
Started Jun 01 01:31:51 PM PDT 24
Finished Jun 01 01:31:53 PM PDT 24
Peak memory 212676 kb
Host smart-a8a5202e-088b-4b3a-89db-72f6a37eaca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142402904 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.3142402904
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.3653885217
Short name T252
Test name
Test status
Simulation time 48743791 ps
CPU time 0.95 seconds
Started Jun 01 01:31:49 PM PDT 24
Finished Jun 01 01:31:51 PM PDT 24
Peak memory 204248 kb
Host smart-19026433-258d-4230-b6c8-cfbeae187ea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653885217 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
3653885217
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.469530731
Short name T270
Test name
Test status
Simulation time 14109450 ps
CPU time 0.91 seconds
Started Jun 01 01:31:52 PM PDT 24
Finished Jun 01 01:31:54 PM PDT 24
Peak memory 204276 kb
Host smart-39dcb647-2166-4a6d-ac65-29c32e213e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469530731 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.469530731
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.484716780
Short name T291
Test name
Test status
Simulation time 29673976 ps
CPU time 1.24 seconds
Started Jun 01 01:31:55 PM PDT 24
Finished Jun 01 01:31:57 PM PDT 24
Peak memory 204544 kb
Host smart-8439959b-68eb-4319-84eb-c68767c5ce81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484716780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.k
eymgr_dpe_same_csr_outstanding.484716780
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.1954219100
Short name T250
Test name
Test status
Simulation time 57649572 ps
CPU time 1.92 seconds
Started Jun 01 01:31:49 PM PDT 24
Finished Jun 01 01:31:52 PM PDT 24
Peak memory 212940 kb
Host smart-efdf3616-303c-4984-a7cf-65762c1c5e14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954219100 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.1954219100
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2953806940
Short name T184
Test name
Test status
Simulation time 389410618 ps
CPU time 4.83 seconds
Started Jun 01 01:31:50 PM PDT 24
Finished Jun 01 01:31:55 PM PDT 24
Peak memory 213028 kb
Host smart-f7b9bfe0-dc50-41a3-9e63-ee4be76e2b29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953806940 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2953806940
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.2926133215
Short name T43
Test name
Test status
Simulation time 431288046 ps
CPU time 4.18 seconds
Started Jun 01 01:31:54 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 212660 kb
Host smart-14608baf-0120-4154-b183-3878b96f0ea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926133215 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
2926133215
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.1617465591
Short name T199
Test name
Test status
Simulation time 23729213 ps
CPU time 1.67 seconds
Started Jun 01 01:31:59 PM PDT 24
Finished Jun 01 01:32:02 PM PDT 24
Peak memory 212680 kb
Host smart-d9758c5c-ff64-480d-a8b4-db28ffa9e13a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617465591 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.1617465591
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.2138597082
Short name T183
Test name
Test status
Simulation time 15667818 ps
CPU time 1.12 seconds
Started Jun 01 01:31:59 PM PDT 24
Finished Jun 01 01:32:00 PM PDT 24
Peak memory 204492 kb
Host smart-e6942e87-b28d-48ff-91d1-43d9dfc23671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138597082 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
2138597082
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.3733318837
Short name T204
Test name
Test status
Simulation time 17259520 ps
CPU time 0.74 seconds
Started Jun 01 01:31:56 PM PDT 24
Finished Jun 01 01:31:57 PM PDT 24
Peak memory 204308 kb
Host smart-9b20c65f-95e9-4f1f-93de-fdb9a6ad8ce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733318837 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
3733318837
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.3686394267
Short name T289
Test name
Test status
Simulation time 53587258 ps
CPU time 1.68 seconds
Started Jun 01 01:31:57 PM PDT 24
Finished Jun 01 01:32:00 PM PDT 24
Peak memory 204520 kb
Host smart-9d646b27-4c4a-4552-b0b4-54335a0007b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686394267 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.3686394267
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2242088089
Short name T262
Test name
Test status
Simulation time 130406491 ps
CPU time 1.37 seconds
Started Jun 01 01:31:49 PM PDT 24
Finished Jun 01 01:31:52 PM PDT 24
Peak memory 212888 kb
Host smart-925eb5f1-dde5-4458-90d0-44505f72793a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242088089 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2242088089
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1456529705
Short name T278
Test name
Test status
Simulation time 126491697 ps
CPU time 3.93 seconds
Started Jun 01 01:31:51 PM PDT 24
Finished Jun 01 01:31:55 PM PDT 24
Peak memory 217924 kb
Host smart-7aad49c5-1ea8-4197-9651-d39ff4a7c585
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456529705 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1456529705
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.1857738503
Short name T222
Test name
Test status
Simulation time 180141940 ps
CPU time 1.81 seconds
Started Jun 01 01:31:52 PM PDT 24
Finished Jun 01 01:31:54 PM PDT 24
Peak memory 212744 kb
Host smart-4b0de55c-6d23-4fc0-9279-12dcc56014d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857738503 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
1857738503
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.4174102505
Short name T58
Test name
Test status
Simulation time 191723816 ps
CPU time 2.21 seconds
Started Jun 01 01:31:52 PM PDT 24
Finished Jun 01 01:31:55 PM PDT 24
Peak memory 212884 kb
Host smart-f25286ed-86a5-4e6a-a9f6-b73317573e69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174102505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.4174102505
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.1134964653
Short name T195
Test name
Test status
Simulation time 222672501 ps
CPU time 3.12 seconds
Started Jun 01 01:31:11 PM PDT 24
Finished Jun 01 01:31:15 PM PDT 24
Peak memory 204520 kb
Host smart-85996e90-32f2-48af-9f2b-30e4d16b5378
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134964653 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.1134964653
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.2352402428
Short name T173
Test name
Test status
Simulation time 184098984 ps
CPU time 4.59 seconds
Started Jun 01 01:31:14 PM PDT 24
Finished Jun 01 01:31:19 PM PDT 24
Peak memory 204584 kb
Host smart-08dab6b4-7c21-4dca-988c-e4ed0b9a53be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352402428 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.2352402428
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2899166860
Short name T284
Test name
Test status
Simulation time 28892666 ps
CPU time 1.12 seconds
Started Jun 01 01:31:15 PM PDT 24
Finished Jun 01 01:31:17 PM PDT 24
Peak memory 204428 kb
Host smart-68f8ea8f-7e11-411d-a721-1952460ecd72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899166860 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.2899166860
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.379966720
Short name T209
Test name
Test status
Simulation time 160608646 ps
CPU time 1.15 seconds
Started Jun 01 01:31:20 PM PDT 24
Finished Jun 01 01:31:22 PM PDT 24
Peak memory 204376 kb
Host smart-0ec0066b-09fe-449c-8e17-f158f17b106c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379966720 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.379966720
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2880648918
Short name T276
Test name
Test status
Simulation time 36802633 ps
CPU time 0.86 seconds
Started Jun 01 01:31:11 PM PDT 24
Finished Jun 01 01:31:13 PM PDT 24
Peak memory 204356 kb
Host smart-dc2a700b-334e-4154-921f-56f41f24323b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880648918 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.2
880648918
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.1906840582
Short name T281
Test name
Test status
Simulation time 33814946 ps
CPU time 0.82 seconds
Started Jun 01 01:31:12 PM PDT 24
Finished Jun 01 01:31:13 PM PDT 24
Peak memory 204364 kb
Host smart-2c895e4e-dee5-45f9-af46-82fd1a9afa8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906840582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.1
906840582
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.1467355588
Short name T44
Test name
Test status
Simulation time 53605714 ps
CPU time 1.85 seconds
Started Jun 01 01:31:11 PM PDT 24
Finished Jun 01 01:31:14 PM PDT 24
Peak memory 204432 kb
Host smart-a11de716-a2af-4be7-9db6-5728df5f7453
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467355588 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.1467355588
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.3132270137
Short name T249
Test name
Test status
Simulation time 63884491 ps
CPU time 2.13 seconds
Started Jun 01 01:31:14 PM PDT 24
Finished Jun 01 01:31:17 PM PDT 24
Peak memory 213200 kb
Host smart-f589b9ce-dd88-4769-bf00-fccfd4900df5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132270137 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.3132270137
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4023200905
Short name T245
Test name
Test status
Simulation time 164049517 ps
CPU time 2.38 seconds
Started Jun 01 01:31:12 PM PDT 24
Finished Jun 01 01:31:14 PM PDT 24
Peak memory 213024 kb
Host smart-00b7f007-5960-4e16-8775-3fc425fc0a35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023200905 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4023200905
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.2821445409
Short name T54
Test name
Test status
Simulation time 294057126 ps
CPU time 4.06 seconds
Started Jun 01 01:31:10 PM PDT 24
Finished Jun 01 01:31:15 PM PDT 24
Peak memory 212748 kb
Host smart-b59c1ada-7389-43be-8ecc-48fc054135f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821445409 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.2
821445409
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.2586673996
Short name T266
Test name
Test status
Simulation time 16131726 ps
CPU time 0.9 seconds
Started Jun 01 01:31:57 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 204348 kb
Host smart-ea64c496-1575-4ba2-9991-66c148d2a415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586673996 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
2586673996
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.1077148860
Short name T50
Test name
Test status
Simulation time 11633549 ps
CPU time 0.87 seconds
Started Jun 01 01:31:58 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 204308 kb
Host smart-ea19baad-c15c-43d9-bc6f-78c94ec195a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077148860 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
1077148860
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.3294159247
Short name T282
Test name
Test status
Simulation time 43781726 ps
CPU time 0.82 seconds
Started Jun 01 01:31:59 PM PDT 24
Finished Jun 01 01:32:01 PM PDT 24
Peak memory 204472 kb
Host smart-b5abc0ab-030e-4ea3-8a80-31644f854cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294159247 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
3294159247
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.725128273
Short name T205
Test name
Test status
Simulation time 11451675 ps
CPU time 0.86 seconds
Started Jun 01 01:31:59 PM PDT 24
Finished Jun 01 01:32:00 PM PDT 24
Peak memory 204240 kb
Host smart-f715bd25-5694-47c4-a6f9-4f0dfbbe2be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725128273 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.725128273
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.3551313656
Short name T180
Test name
Test status
Simulation time 19159894 ps
CPU time 0.8 seconds
Started Jun 01 01:31:56 PM PDT 24
Finished Jun 01 01:31:58 PM PDT 24
Peak memory 204352 kb
Host smart-37306054-c60a-449d-91b5-268eb7d9640e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551313656 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
3551313656
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.3315318674
Short name T246
Test name
Test status
Simulation time 46875078 ps
CPU time 0.74 seconds
Started Jun 01 01:31:57 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 204328 kb
Host smart-5dc5d70e-7b4f-498e-a639-8184daf42602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315318674 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
3315318674
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.4157220416
Short name T179
Test name
Test status
Simulation time 14817152 ps
CPU time 0.74 seconds
Started Jun 01 01:32:00 PM PDT 24
Finished Jun 01 01:32:02 PM PDT 24
Peak memory 204332 kb
Host smart-a78b896f-fae5-4142-9f4b-14519bbcc058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157220416 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
4157220416
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1404302582
Short name T197
Test name
Test status
Simulation time 9202376 ps
CPU time 0.88 seconds
Started Jun 01 01:31:58 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 204360 kb
Host smart-f5f6716f-fa04-4da4-ac72-10d3a46c722e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404302582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
1404302582
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.678999338
Short name T210
Test name
Test status
Simulation time 149220512 ps
CPU time 0.77 seconds
Started Jun 01 01:31:55 PM PDT 24
Finished Jun 01 01:31:56 PM PDT 24
Peak memory 204376 kb
Host smart-4fda5ec4-426a-49d1-bbfb-a86ba3e00da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678999338 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.678999338
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.350063256
Short name T215
Test name
Test status
Simulation time 34319634 ps
CPU time 0.8 seconds
Started Jun 01 01:31:57 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 204316 kb
Host smart-fb92d2c8-45aa-4b9d-837c-bd73eb1bbe73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350063256 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.350063256
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.4047183540
Short name T294
Test name
Test status
Simulation time 444520574 ps
CPU time 2.78 seconds
Started Jun 01 01:31:15 PM PDT 24
Finished Jun 01 01:31:18 PM PDT 24
Peak memory 204448 kb
Host smart-055e50f7-b221-4977-b75e-4c4773626a1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047183540 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.4047183540
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.581079939
Short name T236
Test name
Test status
Simulation time 1768188376 ps
CPU time 11.08 seconds
Started Jun 01 01:31:20 PM PDT 24
Finished Jun 01 01:31:32 PM PDT 24
Peak memory 204516 kb
Host smart-2e4b4539-5aa2-47b8-9e2b-9659f78fb00a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581079939 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_bit_bash.581079939
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.746403115
Short name T303
Test name
Test status
Simulation time 14346638 ps
CPU time 0.86 seconds
Started Jun 01 01:31:13 PM PDT 24
Finished Jun 01 01:31:14 PM PDT 24
Peak memory 204344 kb
Host smart-0d51ded9-02dd-4715-a7c9-f05ee8245fa2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746403115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_hw_reset.746403115
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.3038029335
Short name T275
Test name
Test status
Simulation time 60077795 ps
CPU time 1.12 seconds
Started Jun 01 01:31:19 PM PDT 24
Finished Jun 01 01:31:21 PM PDT 24
Peak memory 204436 kb
Host smart-5a2ef531-650a-489c-853c-ed9aab440267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038029335 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.3038029335
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.2210193167
Short name T309
Test name
Test status
Simulation time 36588732 ps
CPU time 1.23 seconds
Started Jun 01 01:31:20 PM PDT 24
Finished Jun 01 01:31:22 PM PDT 24
Peak memory 204364 kb
Host smart-e5245329-0aa0-48a2-847d-b7f8479ac90a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210193167 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.2
210193167
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.3397625545
Short name T80
Test name
Test status
Simulation time 31672395 ps
CPU time 0.68 seconds
Started Jun 01 01:31:11 PM PDT 24
Finished Jun 01 01:31:12 PM PDT 24
Peak memory 204316 kb
Host smart-f6d3e5f7-5f0f-47b2-b758-f899b2e0e102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397625545 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.3
397625545
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2327738647
Short name T295
Test name
Test status
Simulation time 79858130 ps
CPU time 3.26 seconds
Started Jun 01 01:31:17 PM PDT 24
Finished Jun 01 01:31:21 PM PDT 24
Peak memory 204464 kb
Host smart-db85f395-0b3c-423f-a7fc-8a176db8e79f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327738647 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.2327738647
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3909938140
Short name T290
Test name
Test status
Simulation time 676297183 ps
CPU time 2.18 seconds
Started Jun 01 01:31:12 PM PDT 24
Finished Jun 01 01:31:15 PM PDT 24
Peak memory 213060 kb
Host smart-9978b02e-6a8c-44a6-a8d8-3c9dfadf3cfc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909938140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3909938140
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1634184981
Short name T89
Test name
Test status
Simulation time 374186900 ps
CPU time 4.28 seconds
Started Jun 01 01:31:13 PM PDT 24
Finished Jun 01 01:31:17 PM PDT 24
Peak memory 212940 kb
Host smart-3ae1d468-9110-46e6-9cca-e1cec728ade4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634184981 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1634184981
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.1330204873
Short name T299
Test name
Test status
Simulation time 710184384 ps
CPU time 2.76 seconds
Started Jun 01 01:31:13 PM PDT 24
Finished Jun 01 01:31:16 PM PDT 24
Peak memory 212608 kb
Host smart-05ddf4a9-e177-43d7-8c90-d269f5ccc3a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330204873 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.1
330204873
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.2525314126
Short name T59
Test name
Test status
Simulation time 110002065 ps
CPU time 3.7 seconds
Started Jun 01 01:31:21 PM PDT 24
Finished Jun 01 01:31:26 PM PDT 24
Peak memory 212688 kb
Host smart-e84899f8-079f-49fa-82b7-b781c6917360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525314126 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.2525314126
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.2591560533
Short name T244
Test name
Test status
Simulation time 17464023 ps
CPU time 0.88 seconds
Started Jun 01 01:31:59 PM PDT 24
Finished Jun 01 01:32:01 PM PDT 24
Peak memory 204324 kb
Host smart-8cd72831-1c3e-4f0d-b2e1-0ec710c6a4e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591560533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
2591560533
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.516483387
Short name T218
Test name
Test status
Simulation time 11600555 ps
CPU time 0.81 seconds
Started Jun 01 01:31:57 PM PDT 24
Finished Jun 01 01:31:58 PM PDT 24
Peak memory 204204 kb
Host smart-706445e9-29b3-401a-a637-82628983ab29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516483387 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.516483387
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.4164837330
Short name T301
Test name
Test status
Simulation time 9965159 ps
CPU time 0.75 seconds
Started Jun 01 01:31:59 PM PDT 24
Finished Jun 01 01:32:01 PM PDT 24
Peak memory 204296 kb
Host smart-93c288d6-1179-4799-b520-9626246edc65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164837330 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
4164837330
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.3814945518
Short name T214
Test name
Test status
Simulation time 16149527 ps
CPU time 0.75 seconds
Started Jun 01 01:31:56 PM PDT 24
Finished Jun 01 01:31:58 PM PDT 24
Peak memory 204296 kb
Host smart-6172b923-4c08-4b86-ad65-a01d42ceaca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814945518 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
3814945518
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.2138510900
Short name T292
Test name
Test status
Simulation time 9437182 ps
CPU time 0.83 seconds
Started Jun 01 01:31:58 PM PDT 24
Finished Jun 01 01:32:00 PM PDT 24
Peak memory 204348 kb
Host smart-f8f00fb8-84ac-4106-99cd-d6d949f73401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138510900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
2138510900
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3044933159
Short name T234
Test name
Test status
Simulation time 8809026 ps
CPU time 0.75 seconds
Started Jun 01 01:32:03 PM PDT 24
Finished Jun 01 01:32:04 PM PDT 24
Peak memory 204344 kb
Host smart-3c31dafc-45c1-433b-a739-64809942de0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044933159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
3044933159
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.1855023863
Short name T220
Test name
Test status
Simulation time 32646229 ps
CPU time 0.7 seconds
Started Jun 01 01:31:58 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 204268 kb
Host smart-83269208-2708-4fa9-8027-e4a2c9787745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855023863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
1855023863
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3850929109
Short name T272
Test name
Test status
Simulation time 157680899 ps
CPU time 0.94 seconds
Started Jun 01 01:31:57 PM PDT 24
Finished Jun 01 01:31:58 PM PDT 24
Peak memory 204260 kb
Host smart-b27d1f9a-3364-4bb7-be09-72ea44077e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850929109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
3850929109
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.108489474
Short name T176
Test name
Test status
Simulation time 9873877 ps
CPU time 0.81 seconds
Started Jun 01 01:31:59 PM PDT 24
Finished Jun 01 01:32:00 PM PDT 24
Peak memory 204340 kb
Host smart-1effffe0-1495-4d14-944e-713d5e484504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108489474 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.108489474
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.188895160
Short name T274
Test name
Test status
Simulation time 11332775 ps
CPU time 0.84 seconds
Started Jun 01 01:31:58 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 204292 kb
Host smart-853266b5-9744-48d6-bfc0-4d04077d71e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188895160 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.188895160
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.4200951444
Short name T77
Test name
Test status
Simulation time 1513141610 ps
CPU time 6.04 seconds
Started Jun 01 01:31:27 PM PDT 24
Finished Jun 01 01:31:34 PM PDT 24
Peak memory 204384 kb
Host smart-a365a13f-e2e3-49a8-bd6e-8a0ac740e6e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200951444 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.4200951444
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3049895048
Short name T287
Test name
Test status
Simulation time 848807141 ps
CPU time 9.5 seconds
Started Jun 01 01:31:26 PM PDT 24
Finished Jun 01 01:31:36 PM PDT 24
Peak memory 204504 kb
Host smart-0d09a94e-aaf9-4493-91dc-c683f418b643
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049895048 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.3049895048
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.2586791390
Short name T260
Test name
Test status
Simulation time 15221636 ps
CPU time 1.08 seconds
Started Jun 01 01:31:21 PM PDT 24
Finished Jun 01 01:31:22 PM PDT 24
Peak memory 204488 kb
Host smart-46d1b222-5fc1-4201-bb86-647db985b38a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586791390 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.2586791390
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1472189979
Short name T302
Test name
Test status
Simulation time 21451843 ps
CPU time 1.39 seconds
Started Jun 01 01:31:20 PM PDT 24
Finished Jun 01 01:31:22 PM PDT 24
Peak memory 220900 kb
Host smart-72c1473b-17d3-4d3b-a6b4-159adac4b063
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472189979 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.1472189979
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1360619368
Short name T85
Test name
Test status
Simulation time 14376936 ps
CPU time 0.95 seconds
Started Jun 01 01:31:25 PM PDT 24
Finished Jun 01 01:31:26 PM PDT 24
Peak memory 204508 kb
Host smart-5531ebed-2b46-4f7e-bc57-856e74daffe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360619368 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1
360619368
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.3048788900
Short name T264
Test name
Test status
Simulation time 8669529 ps
CPU time 0.71 seconds
Started Jun 01 01:31:19 PM PDT 24
Finished Jun 01 01:31:20 PM PDT 24
Peak memory 204340 kb
Host smart-1e40c5df-9af6-4f64-af49-2413452d3669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048788900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.3
048788900
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.4024410254
Short name T88
Test name
Test status
Simulation time 150630878 ps
CPU time 1.51 seconds
Started Jun 01 01:31:26 PM PDT 24
Finished Jun 01 01:31:28 PM PDT 24
Peak memory 204540 kb
Host smart-07073704-5e7a-4a8b-8343-6679b8864e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024410254 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.4024410254
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.793742751
Short name T86
Test name
Test status
Simulation time 84924892 ps
CPU time 1.83 seconds
Started Jun 01 01:31:27 PM PDT 24
Finished Jun 01 01:31:30 PM PDT 24
Peak memory 213024 kb
Host smart-8d7cf7af-7c3e-4c91-80ce-71b87033fdab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793742751 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymg
r_dpe_shadow_reg_errors.793742751
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.3171653292
Short name T186
Test name
Test status
Simulation time 879291854 ps
CPU time 7.88 seconds
Started Jun 01 01:31:20 PM PDT 24
Finished Jun 01 01:31:28 PM PDT 24
Peak memory 212928 kb
Host smart-9a2cb8ba-387f-4c14-ac3b-53b65939981c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171653292 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.3171653292
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.1171393817
Short name T103
Test name
Test status
Simulation time 532164931 ps
CPU time 2.75 seconds
Started Jun 01 01:31:19 PM PDT 24
Finished Jun 01 01:31:23 PM PDT 24
Peak memory 216292 kb
Host smart-cdce85b6-4110-4ab7-a54a-e346acae3264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171393817 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.1
171393817
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3843086116
Short name T258
Test name
Test status
Simulation time 19255820 ps
CPU time 0.72 seconds
Started Jun 01 01:31:59 PM PDT 24
Finished Jun 01 01:32:01 PM PDT 24
Peak memory 204368 kb
Host smart-9dfacacc-f552-4af8-9f42-632a32812779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843086116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
3843086116
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.2458884759
Short name T79
Test name
Test status
Simulation time 34667709 ps
CPU time 0.86 seconds
Started Jun 01 01:32:01 PM PDT 24
Finished Jun 01 01:32:03 PM PDT 24
Peak memory 204260 kb
Host smart-03434005-85b0-4ec5-841c-2eda72be5246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458884759 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
2458884759
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.1205234251
Short name T212
Test name
Test status
Simulation time 27700232 ps
CPU time 0.78 seconds
Started Jun 01 01:31:58 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 204312 kb
Host smart-6303b4c3-c319-4207-8fb0-fc05e6bfa70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205234251 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
1205234251
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2104731551
Short name T167
Test name
Test status
Simulation time 12813814 ps
CPU time 0.85 seconds
Started Jun 01 01:31:56 PM PDT 24
Finished Jun 01 01:31:57 PM PDT 24
Peak memory 204336 kb
Host smart-71c71686-170c-4488-ad93-d3b0659c7bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104731551 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
2104731551
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.3242648249
Short name T181
Test name
Test status
Simulation time 24541389 ps
CPU time 0.72 seconds
Started Jun 01 01:31:58 PM PDT 24
Finished Jun 01 01:31:59 PM PDT 24
Peak memory 204292 kb
Host smart-94fad9b4-2fef-4a05-9014-458c27d1816a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242648249 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
3242648249
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.2042515436
Short name T237
Test name
Test status
Simulation time 7397370 ps
CPU time 0.73 seconds
Started Jun 01 01:32:03 PM PDT 24
Finished Jun 01 01:32:04 PM PDT 24
Peak memory 204344 kb
Host smart-7219fdb2-2f88-493c-957a-626f3a8a5de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042515436 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
2042515436
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.441398035
Short name T169
Test name
Test status
Simulation time 10667613 ps
CPU time 0.73 seconds
Started Jun 01 01:32:00 PM PDT 24
Finished Jun 01 01:32:01 PM PDT 24
Peak memory 204308 kb
Host smart-7fc26b81-25c3-4057-b665-f10db9276699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441398035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.441398035
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3213844645
Short name T100
Test name
Test status
Simulation time 55102388 ps
CPU time 0.84 seconds
Started Jun 01 01:32:00 PM PDT 24
Finished Jun 01 01:32:01 PM PDT 24
Peak memory 204332 kb
Host smart-510926f4-4ac1-4f45-a2ab-130ce1d9f874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213844645 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
3213844645
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.1719149597
Short name T97
Test name
Test status
Simulation time 50724625 ps
CPU time 0.76 seconds
Started Jun 01 01:31:57 PM PDT 24
Finished Jun 01 01:31:58 PM PDT 24
Peak memory 204192 kb
Host smart-00a26212-f132-40a0-86d4-924363174128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719149597 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
1719149597
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.295568650
Short name T251
Test name
Test status
Simulation time 47082896 ps
CPU time 0.75 seconds
Started Jun 01 01:32:10 PM PDT 24
Finished Jun 01 01:32:11 PM PDT 24
Peak memory 204336 kb
Host smart-7e14836b-705d-4ef7-821b-cdd67f8d98a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295568650 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.295568650
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.241195323
Short name T177
Test name
Test status
Simulation time 63340629 ps
CPU time 1.45 seconds
Started Jun 01 01:31:27 PM PDT 24
Finished Jun 01 01:31:29 PM PDT 24
Peak memory 212752 kb
Host smart-f3c05f48-9c82-4dbd-aace-36a09fa95847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241195323 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.241195323
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.774162553
Short name T231
Test name
Test status
Simulation time 41500145 ps
CPU time 0.89 seconds
Started Jun 01 01:31:25 PM PDT 24
Finished Jun 01 01:31:27 PM PDT 24
Peak memory 204288 kb
Host smart-29843d4d-459a-4ad9-babe-ba7063f6509d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774162553 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.774162553
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.2612468281
Short name T216
Test name
Test status
Simulation time 35710086 ps
CPU time 0.81 seconds
Started Jun 01 01:31:25 PM PDT 24
Finished Jun 01 01:31:26 PM PDT 24
Peak memory 204172 kb
Host smart-c4b9af8e-8da4-47f6-9903-72bf85f4c165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612468281 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.2
612468281
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.2783367491
Short name T256
Test name
Test status
Simulation time 378052828 ps
CPU time 3.44 seconds
Started Jun 01 01:31:29 PM PDT 24
Finished Jun 01 01:31:33 PM PDT 24
Peak memory 204460 kb
Host smart-2b84ba12-6dce-45cd-b349-02eddae9c9b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783367491 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.2783367491
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1928705427
Short name T70
Test name
Test status
Simulation time 428789545 ps
CPU time 3.13 seconds
Started Jun 01 01:31:19 PM PDT 24
Finished Jun 01 01:31:22 PM PDT 24
Peak memory 213016 kb
Host smart-e87ab943-08b2-4785-9e64-b5420b1c63b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928705427 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.1928705427
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.1154804214
Short name T263
Test name
Test status
Simulation time 446113889 ps
CPU time 4.57 seconds
Started Jun 01 01:31:19 PM PDT 24
Finished Jun 01 01:31:24 PM PDT 24
Peak memory 213040 kb
Host smart-0d8822a7-b0ae-44b3-bdeb-dabe4d6d9013
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154804214 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.1154804214
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.1835561886
Short name T196
Test name
Test status
Simulation time 43958164 ps
CPU time 1.5 seconds
Started Jun 01 01:31:25 PM PDT 24
Finished Jun 01 01:31:28 PM PDT 24
Peak memory 212612 kb
Host smart-9b7145f8-04f5-42ba-877d-7e8dd1347993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835561886 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.1
835561886
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.604935967
Short name T40
Test name
Test status
Simulation time 969621026 ps
CPU time 3.73 seconds
Started Jun 01 01:31:25 PM PDT 24
Finished Jun 01 01:31:29 PM PDT 24
Peak memory 204616 kb
Host smart-ec8ca5f7-5924-467e-8070-ca34642bf93f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604935967 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_
tl_intg_err.604935967
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.2370552596
Short name T22
Test name
Test status
Simulation time 174802226 ps
CPU time 0.98 seconds
Started Jun 01 01:31:27 PM PDT 24
Finished Jun 01 01:31:29 PM PDT 24
Peak memory 204432 kb
Host smart-08cbf722-f0c4-4262-9ae2-e0df3840a468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370552596 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.2370552596
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.156820430
Short name T286
Test name
Test status
Simulation time 37632571 ps
CPU time 1.23 seconds
Started Jun 01 01:31:27 PM PDT 24
Finished Jun 01 01:31:29 PM PDT 24
Peak memory 204476 kb
Host smart-c098ffab-edfe-426c-89cb-4fbead42cab4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156820430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.156820430
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.2323828538
Short name T52
Test name
Test status
Simulation time 10934299 ps
CPU time 0.9 seconds
Started Jun 01 01:31:28 PM PDT 24
Finished Jun 01 01:31:29 PM PDT 24
Peak memory 204332 kb
Host smart-b8409b66-ddad-4d9d-970d-216ef57819bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323828538 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.2
323828538
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.148051281
Short name T300
Test name
Test status
Simulation time 152166589 ps
CPU time 2.64 seconds
Started Jun 01 01:31:30 PM PDT 24
Finished Jun 01 01:31:33 PM PDT 24
Peak memory 204392 kb
Host smart-ab6447ea-fc00-4788-b29b-138c039b5b36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148051281 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ke
ymgr_dpe_same_csr_outstanding.148051281
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.3975343678
Short name T72
Test name
Test status
Simulation time 119264861 ps
CPU time 3.6 seconds
Started Jun 01 01:31:27 PM PDT 24
Finished Jun 01 01:31:31 PM PDT 24
Peak memory 212992 kb
Host smart-f37e8ced-f273-4f71-b224-af075db097a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975343678 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.3975343678
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.1433155089
Short name T174
Test name
Test status
Simulation time 185504071 ps
CPU time 4.24 seconds
Started Jun 01 01:31:30 PM PDT 24
Finished Jun 01 01:31:34 PM PDT 24
Peak memory 213120 kb
Host smart-e7d8775f-81b6-4ecf-87b2-7fae9807a1a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433155089 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.1433155089
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.1013697456
Short name T175
Test name
Test status
Simulation time 46926503 ps
CPU time 1.44 seconds
Started Jun 01 01:31:25 PM PDT 24
Finished Jun 01 01:31:27 PM PDT 24
Peak memory 212692 kb
Host smart-69890fdd-1b6e-419c-b021-018e3ab33b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013697456 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.1
013697456
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.899109981
Short name T101
Test name
Test status
Simulation time 61576358 ps
CPU time 1.3 seconds
Started Jun 01 01:31:28 PM PDT 24
Finished Jun 01 01:31:30 PM PDT 24
Peak memory 212780 kb
Host smart-24a5d04c-a59c-42ab-a7a6-5ba7fb1fd349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899109981 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.899109981
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.2959549816
Short name T271
Test name
Test status
Simulation time 81926721 ps
CPU time 1.07 seconds
Started Jun 01 01:31:27 PM PDT 24
Finished Jun 01 01:31:28 PM PDT 24
Peak memory 204420 kb
Host smart-50c770fe-866a-48ab-8331-3507fc1a0ebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959549816 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.2
959549816
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.3900993599
Short name T200
Test name
Test status
Simulation time 10694366 ps
CPU time 0.73 seconds
Started Jun 01 01:31:26 PM PDT 24
Finished Jun 01 01:31:27 PM PDT 24
Peak memory 204240 kb
Host smart-538394a2-fb25-4356-b2dc-eaa2951fa0a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900993599 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.3
900993599
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.2786286700
Short name T187
Test name
Test status
Simulation time 106811890 ps
CPU time 2.12 seconds
Started Jun 01 01:31:26 PM PDT 24
Finished Jun 01 01:31:28 PM PDT 24
Peak memory 213036 kb
Host smart-bf6c12f4-428a-4985-9c54-6fe3dc99ec0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786286700 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.2786286700
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2340998336
Short name T280
Test name
Test status
Simulation time 474871896 ps
CPU time 9.04 seconds
Started Jun 01 01:31:29 PM PDT 24
Finished Jun 01 01:31:38 PM PDT 24
Peak memory 212952 kb
Host smart-2af08f6b-6ae1-4cef-81ad-8bff2e1bf227
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340998336 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2340998336
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.3653369700
Short name T49
Test name
Test status
Simulation time 323542471 ps
CPU time 3.49 seconds
Started Jun 01 01:31:28 PM PDT 24
Finished Jun 01 01:31:32 PM PDT 24
Peak memory 220292 kb
Host smart-30deed49-a020-4159-8e6e-6d7622d28c00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653369700 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.3
653369700
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.2019366386
Short name T65
Test name
Test status
Simulation time 1467146360 ps
CPU time 5.96 seconds
Started Jun 01 01:31:25 PM PDT 24
Finished Jun 01 01:31:32 PM PDT 24
Peak memory 213872 kb
Host smart-26283dd6-a448-4a31-a71a-cbc8913743b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019366386 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.2019366386
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.3558109735
Short name T120
Test name
Test status
Simulation time 95742136 ps
CPU time 1.98 seconds
Started Jun 01 01:31:36 PM PDT 24
Finished Jun 01 01:31:39 PM PDT 24
Peak memory 212772 kb
Host smart-776c4abb-6df2-4483-90e1-e86db5d909eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558109735 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.3558109735
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.711306801
Short name T259
Test name
Test status
Simulation time 46134143 ps
CPU time 1.02 seconds
Started Jun 01 01:31:33 PM PDT 24
Finished Jun 01 01:31:34 PM PDT 24
Peak memory 204412 kb
Host smart-647da5f0-1073-43c5-844c-f6c87bace27f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711306801 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.711306801
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.4034417616
Short name T203
Test name
Test status
Simulation time 37392913 ps
CPU time 0.81 seconds
Started Jun 01 01:31:37 PM PDT 24
Finished Jun 01 01:31:38 PM PDT 24
Peak memory 204352 kb
Host smart-15f3aed1-7af1-498c-b918-a45468f79a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034417616 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.4
034417616
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.4104881792
Short name T78
Test name
Test status
Simulation time 76132401 ps
CPU time 1.99 seconds
Started Jun 01 01:31:32 PM PDT 24
Finished Jun 01 01:31:34 PM PDT 24
Peak memory 204448 kb
Host smart-f339d5d9-0169-4b5a-8dae-9e152eded581
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104881792 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.4104881792
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.567161531
Short name T182
Test name
Test status
Simulation time 1034364414 ps
CPU time 1.82 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:36 PM PDT 24
Peak memory 213020 kb
Host smart-e345880a-7728-425f-a6a0-50ef60276463
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567161531 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymg
r_dpe_shadow_reg_errors.567161531
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.906543522
Short name T207
Test name
Test status
Simulation time 67994350 ps
CPU time 3.1 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:38 PM PDT 24
Peak memory 212868 kb
Host smart-e7da559d-d511-43fa-91fb-d6d3d730dc9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906543522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.906543522
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3632137624
Short name T296
Test name
Test status
Simulation time 213276022 ps
CPU time 4.24 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:39 PM PDT 24
Peak memory 212732 kb
Host smart-afa297d8-657c-4b8a-b3b5-8ca9bb34092c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632137624 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.3
632137624
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.3484414524
Short name T42
Test name
Test status
Simulation time 31052780 ps
CPU time 1.3 seconds
Started Jun 01 01:31:37 PM PDT 24
Finished Jun 01 01:31:39 PM PDT 24
Peak memory 212632 kb
Host smart-c4b01b73-aaf4-4bc0-b174-6c95633434b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484414524 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.3484414524
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.2985334969
Short name T168
Test name
Test status
Simulation time 19465794 ps
CPU time 0.92 seconds
Started Jun 01 01:31:35 PM PDT 24
Finished Jun 01 01:31:37 PM PDT 24
Peak memory 204420 kb
Host smart-878e1522-f21b-40e0-b6ef-9c37f9a3babd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985334969 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.2
985334969
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.1673604125
Short name T208
Test name
Test status
Simulation time 181922631 ps
CPU time 0.87 seconds
Started Jun 01 01:31:35 PM PDT 24
Finished Jun 01 01:31:36 PM PDT 24
Peak memory 204248 kb
Host smart-25de097c-4a64-47bf-be82-54c467a0226a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673604125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.1
673604125
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2513833404
Short name T306
Test name
Test status
Simulation time 346721962 ps
CPU time 2.66 seconds
Started Jun 01 01:31:33 PM PDT 24
Finished Jun 01 01:31:36 PM PDT 24
Peak memory 204576 kb
Host smart-bfe9fefd-a288-4107-a8e3-f478883ce449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513833404 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.2513833404
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.1323456776
Short name T277
Test name
Test status
Simulation time 126127048 ps
CPU time 1.41 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:36 PM PDT 24
Peak memory 212860 kb
Host smart-e34fae3e-5324-4132-a528-660b5d0942f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323456776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.1323456776
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.1961989287
Short name T219
Test name
Test status
Simulation time 234197690 ps
CPU time 2.77 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:38 PM PDT 24
Peak memory 213004 kb
Host smart-0d08408a-bcd3-46f8-a441-35567b050e19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961989287 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.1961989287
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.2254299878
Short name T298
Test name
Test status
Simulation time 332538214 ps
CPU time 5.52 seconds
Started Jun 01 01:31:34 PM PDT 24
Finished Jun 01 01:31:40 PM PDT 24
Peak memory 215140 kb
Host smart-16e09b68-ed96-4ef6-b6dc-846910166290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254299878 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.2
254299878
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.2544389927
Short name T39
Test name
Test status
Simulation time 89279484 ps
CPU time 2.63 seconds
Started Jun 01 01:31:35 PM PDT 24
Finished Jun 01 01:31:39 PM PDT 24
Peak memory 212904 kb
Host smart-3a38d7f6-0d3f-4a29-8ae0-0e304d516a26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544389927 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.2544389927
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.2857783015
Short name T121
Test name
Test status
Simulation time 22562425 ps
CPU time 0.74 seconds
Started Jun 01 01:30:24 PM PDT 24
Finished Jun 01 01:30:25 PM PDT 24
Peak memory 205508 kb
Host smart-2528c790-fba8-407a-9e02-9ecbf432cffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857783015 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.2
857783015
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.1999226457
Short name T46
Test name
Test status
Simulation time 14004260 ps
CPU time 0.76 seconds
Started Jun 01 01:30:29 PM PDT 24
Finished Jun 01 01:30:30 PM PDT 24
Peak memory 205544 kb
Host smart-075001c0-f28c-40c5-8ac2-051fab9b5f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999226457 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
1999226457
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.3586198601
Short name T93
Test name
Test status
Simulation time 2306018585 ps
CPU time 22.37 seconds
Started Jun 01 01:30:30 PM PDT 24
Finished Jun 01 01:30:53 PM PDT 24
Peak memory 208256 kb
Host smart-c0205572-0984-43ab-b1a6-c8d9101080cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586198601 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.3586198601
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.2946919113
Short name T134
Test name
Test status
Simulation time 9265385 ps
CPU time 0.8 seconds
Started Jun 01 01:30:29 PM PDT 24
Finished Jun 01 01:30:30 PM PDT 24
Peak memory 205468 kb
Host smart-2b67a67f-7c7a-4f2a-bf27-0e8fe0860dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946919113 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
2946919113
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.2415606995
Short name T141
Test name
Test status
Simulation time 4075096081 ps
CPU time 18.31 seconds
Started Jun 01 01:30:29 PM PDT 24
Finished Jun 01 01:30:48 PM PDT 24
Peak memory 208216 kb
Host smart-aad26855-1858-4ba6-847d-94e73f56afae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415606995 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.2415606995
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.952430448
Short name T1
Test name
Test status
Simulation time 20683408 ps
CPU time 0.73 seconds
Started Jun 01 01:30:29 PM PDT 24
Finished Jun 01 01:30:30 PM PDT 24
Peak memory 205508 kb
Host smart-9272f603-aea9-4d79-9ac8-1f8d6c5ea8a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952430448 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.952430448
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.810919775
Short name T45
Test name
Test status
Simulation time 177968562 ps
CPU time 0.88 seconds
Started Jun 01 01:30:30 PM PDT 24
Finished Jun 01 01:30:31 PM PDT 24
Peak memory 205616 kb
Host smart-9b1cd580-67fd-4301-af35-db7c7cc10e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810919775 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.810919775
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.1058384439
Short name T14
Test name
Test status
Simulation time 12699313281 ps
CPU time 90.13 seconds
Started Jun 01 01:30:32 PM PDT 24
Finished Jun 01 01:32:02 PM PDT 24
Peak memory 208620 kb
Host smart-af3da907-aa61-4187-ad03-b09c87f9bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058384439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.1058384439
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.3475718797
Short name T122
Test name
Test status
Simulation time 24382134 ps
CPU time 0.86 seconds
Started Jun 01 01:30:32 PM PDT 24
Finished Jun 01 01:30:33 PM PDT 24
Peak memory 205408 kb
Host smart-799d1274-3106-45f1-87a4-64220fac69d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475718797 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
3475718797
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.1317961669
Short name T157
Test name
Test status
Simulation time 1820698532 ps
CPU time 15.84 seconds
Started Jun 01 01:30:30 PM PDT 24
Finished Jun 01 01:30:46 PM PDT 24
Peak memory 206252 kb
Host smart-026d8525-b8a3-4baa-9a0c-86201d8f5b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317961669 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.1317961669
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.1470793797
Short name T162
Test name
Test status
Simulation time 142916947 ps
CPU time 0.89 seconds
Started Jun 01 01:30:32 PM PDT 24
Finished Jun 01 01:30:33 PM PDT 24
Peak memory 205516 kb
Host smart-b764be69-d85c-4531-92f6-2c162667a429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470793797 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
1470793797
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.3871048301
Short name T158
Test name
Test status
Simulation time 15771975 ps
CPU time 0.74 seconds
Started Jun 01 01:30:36 PM PDT 24
Finished Jun 01 01:30:37 PM PDT 24
Peak memory 205452 kb
Host smart-8b5b4686-bd34-4c8e-adb5-382839327644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871048301 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
3871048301
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.1900918125
Short name T132
Test name
Test status
Simulation time 16251231 ps
CPU time 1 seconds
Started Jun 01 01:30:37 PM PDT 24
Finished Jun 01 01:30:38 PM PDT 24
Peak memory 205716 kb
Host smart-5bf27cd3-739c-4435-aec6-38c67dcc1c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900918125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
1900918125
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.2955653419
Short name T153
Test name
Test status
Simulation time 12865399 ps
CPU time 0.89 seconds
Started Jun 01 01:30:38 PM PDT 24
Finished Jun 01 01:30:39 PM PDT 24
Peak memory 205476 kb
Host smart-c27675a7-0cbb-4f40-8aaf-b34f21590035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955653419 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
2955653419
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.3493889987
Short name T19
Test name
Test status
Simulation time 22515230 ps
CPU time 0.72 seconds
Started Jun 01 01:30:36 PM PDT 24
Finished Jun 01 01:30:37 PM PDT 24
Peak memory 205428 kb
Host smart-0f4238b0-59cf-4c7f-b7e3-fad2bcef8d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493889987 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
3493889987
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.1954383944
Short name T37
Test name
Test status
Simulation time 1530513266 ps
CPU time 19.07 seconds
Started Jun 01 01:30:36 PM PDT 24
Finished Jun 01 01:30:55 PM PDT 24
Peak memory 206508 kb
Host smart-9bb34081-6dcc-4d56-a0d4-3a8451ad90ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954383944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.1954383944
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.1424900846
Short name T140
Test name
Test status
Simulation time 32194892 ps
CPU time 0.82 seconds
Started Jun 01 01:30:24 PM PDT 24
Finished Jun 01 01:30:26 PM PDT 24
Peak memory 205456 kb
Host smart-1d0acef2-28d9-444c-92da-2376adaf338b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424900846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.1
424900846
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.3599340704
Short name T25
Test name
Test status
Simulation time 775055462 ps
CPU time 5.4 seconds
Started Jun 01 01:30:22 PM PDT 24
Finished Jun 01 01:30:28 PM PDT 24
Peak memory 232896 kb
Host smart-457ea2b0-9dae-4751-989c-6ed9bdaa79a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599340704 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.3599340704
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.4251691868
Short name T160
Test name
Test status
Simulation time 7364701034 ps
CPU time 99.89 seconds
Started Jun 01 01:30:23 PM PDT 24
Finished Jun 01 01:32:04 PM PDT 24
Peak memory 207288 kb
Host smart-2d648349-fec4-4304-9587-cdcd1fe2d74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251691868 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.4251691868
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.3431401818
Short name T166
Test name
Test status
Simulation time 12866059 ps
CPU time 0.81 seconds
Started Jun 01 01:30:37 PM PDT 24
Finished Jun 01 01:30:38 PM PDT 24
Peak memory 205476 kb
Host smart-c915b15f-0bfb-4226-bd37-31ca69838e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431401818 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
3431401818
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.162564398
Short name T133
Test name
Test status
Simulation time 30040618 ps
CPU time 0.98 seconds
Started Jun 01 01:30:38 PM PDT 24
Finished Jun 01 01:30:39 PM PDT 24
Peak memory 205648 kb
Host smart-fca1f094-5eb5-434b-9ea4-e7e5db9a2cd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162564398 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.162564398
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.703122582
Short name T109
Test name
Test status
Simulation time 558512509 ps
CPU time 15.37 seconds
Started Jun 01 01:30:36 PM PDT 24
Finished Jun 01 01:30:52 PM PDT 24
Peak memory 208652 kb
Host smart-bf7aef19-7357-4316-a893-cfa9998a5854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703122582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.703122582
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3976645753
Short name T125
Test name
Test status
Simulation time 9478700 ps
CPU time 0.72 seconds
Started Jun 01 01:30:37 PM PDT 24
Finished Jun 01 01:30:38 PM PDT 24
Peak memory 205536 kb
Host smart-4d08beca-6438-4943-a516-e632b45e1f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976645753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3976645753
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.748612754
Short name T159
Test name
Test status
Simulation time 8032249015 ps
CPU time 165.2 seconds
Started Jun 01 01:30:35 PM PDT 24
Finished Jun 01 01:33:21 PM PDT 24
Peak memory 207728 kb
Host smart-4264b6e5-92ac-4451-a085-a6084b3dd451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748612754 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.748612754
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.798839604
Short name T144
Test name
Test status
Simulation time 157050977 ps
CPU time 0.88 seconds
Started Jun 01 01:30:42 PM PDT 24
Finished Jun 01 01:30:43 PM PDT 24
Peak memory 205428 kb
Host smart-cb6374d9-b104-4b2b-ba3a-133ccb8b290c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798839604 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.798839604
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.1550299518
Short name T150
Test name
Test status
Simulation time 985943670 ps
CPU time 18.57 seconds
Started Jun 01 01:30:49 PM PDT 24
Finished Jun 01 01:31:08 PM PDT 24
Peak memory 208276 kb
Host smart-0652f558-0930-498a-9531-8c0c0bc94a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550299518 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.1550299518
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.2475479656
Short name T151
Test name
Test status
Simulation time 10833787 ps
CPU time 0.83 seconds
Started Jun 01 01:30:46 PM PDT 24
Finished Jun 01 01:30:47 PM PDT 24
Peak memory 205388 kb
Host smart-cfa46c95-3d23-4437-96bd-e42e2c01e500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475479656 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
2475479656
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.288407799
Short name T165
Test name
Test status
Simulation time 4655833835 ps
CPU time 35.94 seconds
Started Jun 01 01:30:42 PM PDT 24
Finished Jun 01 01:31:19 PM PDT 24
Peak memory 207616 kb
Host smart-a1371dfb-3238-4b5a-bb1a-59f5cb4eb51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288407799 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.288407799
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.4214039409
Short name T136
Test name
Test status
Simulation time 14559715 ps
CPU time 0.84 seconds
Started Jun 01 01:30:45 PM PDT 24
Finished Jun 01 01:30:47 PM PDT 24
Peak memory 205484 kb
Host smart-dff8c880-dfce-43d2-a6f5-9c59fe09dc96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214039409 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
4214039409
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.3052617164
Short name T152
Test name
Test status
Simulation time 9789449 ps
CPU time 0.82 seconds
Started Jun 01 01:30:41 PM PDT 24
Finished Jun 01 01:30:42 PM PDT 24
Peak memory 205504 kb
Host smart-28459aae-43a5-4af1-af99-b8ed0fcd76b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052617164 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
3052617164
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.657205159
Short name T29
Test name
Test status
Simulation time 2326159542 ps
CPU time 18.88 seconds
Started Jun 01 01:30:41 PM PDT 24
Finished Jun 01 01:31:01 PM PDT 24
Peak memory 206464 kb
Host smart-e3489ae9-f247-429f-b07d-feb2df2db992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657205159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.657205159
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.1558937063
Short name T26
Test name
Test status
Simulation time 81721824 ps
CPU time 0.97 seconds
Started Jun 01 01:30:43 PM PDT 24
Finished Jun 01 01:30:45 PM PDT 24
Peak memory 205592 kb
Host smart-b4e4fcea-8783-4f82-8609-8f0febc91ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558937063 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
1558937063
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.3375525378
Short name T94
Test name
Test status
Simulation time 4345805330 ps
CPU time 23 seconds
Started Jun 01 01:30:42 PM PDT 24
Finished Jun 01 01:31:05 PM PDT 24
Peak memory 206412 kb
Host smart-3c9c9bff-f687-4f50-9b4d-856c1e5bfd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375525378 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.3375525378
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.2540380732
Short name T124
Test name
Test status
Simulation time 25875632 ps
CPU time 0.87 seconds
Started Jun 01 01:30:45 PM PDT 24
Finished Jun 01 01:30:46 PM PDT 24
Peak memory 205436 kb
Host smart-b6d3bd06-462f-476d-8b0f-ad369859a1f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540380732 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
2540380732
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.2060997192
Short name T75
Test name
Test status
Simulation time 60483704 ps
CPU time 0.97 seconds
Started Jun 01 01:30:44 PM PDT 24
Finished Jun 01 01:30:45 PM PDT 24
Peak memory 205644 kb
Host smart-4bd3ea16-2fbe-4487-8ac8-946876248869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060997192 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
2060997192
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.4049938176
Short name T147
Test name
Test status
Simulation time 47042188 ps
CPU time 0.76 seconds
Started Jun 01 01:30:21 PM PDT 24
Finished Jun 01 01:30:22 PM PDT 24
Peak memory 205448 kb
Host smart-0068af39-ed7d-4c06-8d12-c2ae8a821c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049938176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.4
049938176
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.1321804933
Short name T8
Test name
Test status
Simulation time 3054085814 ps
CPU time 12.09 seconds
Started Jun 01 01:30:23 PM PDT 24
Finished Jun 01 01:30:35 PM PDT 24
Peak memory 232412 kb
Host smart-6646e5ce-7aaa-436c-bf3b-3b8d050ea9e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321804933 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.1321804933
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.586775349
Short name T15
Test name
Test status
Simulation time 10001578991 ps
CPU time 148.28 seconds
Started Jun 01 01:30:22 PM PDT 24
Finished Jun 01 01:32:51 PM PDT 24
Peak memory 208520 kb
Host smart-787a0e1a-7ae4-4b8c-8126-a93ded67e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586775349 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.586775349
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.3009327304
Short name T16
Test name
Test status
Simulation time 25526013 ps
CPU time 0.76 seconds
Started Jun 01 01:30:43 PM PDT 24
Finished Jun 01 01:30:44 PM PDT 24
Peak memory 205456 kb
Host smart-8b2e1c99-a7be-4a42-b9ee-53d8c65ed3a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009327304 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
3009327304
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.3344392176
Short name T47
Test name
Test status
Simulation time 1021522848 ps
CPU time 14.34 seconds
Started Jun 01 01:30:43 PM PDT 24
Finished Jun 01 01:30:58 PM PDT 24
Peak memory 208116 kb
Host smart-af7ab55d-a936-4e25-ae75-be26c2e5b75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344392176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.3344392176
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.2168816109
Short name T18
Test name
Test status
Simulation time 12123089 ps
CPU time 0.72 seconds
Started Jun 01 01:30:48 PM PDT 24
Finished Jun 01 01:30:49 PM PDT 24
Peak memory 205428 kb
Host smart-8a132f63-47ae-439a-ae08-144222f75d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168816109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
2168816109
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.51732459
Short name T148
Test name
Test status
Simulation time 11938510 ps
CPU time 0.71 seconds
Started Jun 01 01:30:51 PM PDT 24
Finished Jun 01 01:30:52 PM PDT 24
Peak memory 205440 kb
Host smart-c13204d0-ceee-48a7-a3ea-eaf384c64585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51732459 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.51732459
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.1881144837
Short name T111
Test name
Test status
Simulation time 2173293674 ps
CPU time 19.07 seconds
Started Jun 01 01:30:51 PM PDT 24
Finished Jun 01 01:31:11 PM PDT 24
Peak memory 208440 kb
Host smart-60e623bb-725a-46c4-977b-9ad3c49f4fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881144837 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.1881144837
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.3163932577
Short name T155
Test name
Test status
Simulation time 9943809 ps
CPU time 0.83 seconds
Started Jun 01 01:30:51 PM PDT 24
Finished Jun 01 01:30:53 PM PDT 24
Peak memory 205512 kb
Host smart-82f5bf9d-acb3-4652-b8b4-d08cf98531a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163932577 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
3163932577
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.290402494
Short name T38
Test name
Test status
Simulation time 4662725120 ps
CPU time 36.89 seconds
Started Jun 01 01:30:51 PM PDT 24
Finished Jun 01 01:31:28 PM PDT 24
Peak memory 207876 kb
Host smart-690726bd-752a-4db7-8253-b571d5209bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290402494 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.290402494
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.121451450
Short name T156
Test name
Test status
Simulation time 45408895 ps
CPU time 0.7 seconds
Started Jun 01 01:30:53 PM PDT 24
Finished Jun 01 01:30:54 PM PDT 24
Peak memory 205536 kb
Host smart-0114c51f-b437-483a-97d6-9972558b343e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121451450 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.121451450
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.984553976
Short name T92
Test name
Test status
Simulation time 391465062 ps
CPU time 11.61 seconds
Started Jun 01 01:30:53 PM PDT 24
Finished Jun 01 01:31:05 PM PDT 24
Peak memory 206444 kb
Host smart-076f06be-8348-4350-8fb5-25b1a7498f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984553976 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.984553976
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.3513291314
Short name T164
Test name
Test status
Simulation time 40043127 ps
CPU time 0.72 seconds
Started Jun 01 01:30:50 PM PDT 24
Finished Jun 01 01:30:51 PM PDT 24
Peak memory 205536 kb
Host smart-fd3ec0ab-309f-4e73-8565-85556edbfd18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513291314 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
3513291314
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.866579203
Short name T32
Test name
Test status
Simulation time 29683911 ps
CPU time 0.94 seconds
Started Jun 01 01:30:51 PM PDT 24
Finished Jun 01 01:30:53 PM PDT 24
Peak memory 205664 kb
Host smart-bb04e6d5-65e3-42d0-b427-2c2ec9b46098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866579203 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.866579203
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.110200922
Short name T142
Test name
Test status
Simulation time 1813644525 ps
CPU time 14.95 seconds
Started Jun 01 01:30:50 PM PDT 24
Finished Jun 01 01:31:05 PM PDT 24
Peak memory 208024 kb
Host smart-e0988735-1e85-42f4-9bd3-136d5ea7d41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110200922 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.110200922
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.1477908016
Short name T135
Test name
Test status
Simulation time 14941883 ps
CPU time 0.75 seconds
Started Jun 01 01:30:57 PM PDT 24
Finished Jun 01 01:30:58 PM PDT 24
Peak memory 205516 kb
Host smart-ce1cc869-81ab-4b85-a318-6f2c5c6ae134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477908016 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
1477908016
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.906028722
Short name T82
Test name
Test status
Simulation time 12933982 ps
CPU time 0.72 seconds
Started Jun 01 01:30:59 PM PDT 24
Finished Jun 01 01:31:00 PM PDT 24
Peak memory 205536 kb
Host smart-85ce6434-3768-4f34-98c1-5ed5dfb5e439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906028722 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.906028722
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.428040697
Short name T137
Test name
Test status
Simulation time 6695319619 ps
CPU time 29.98 seconds
Started Jun 01 01:30:58 PM PDT 24
Finished Jun 01 01:31:28 PM PDT 24
Peak memory 208144 kb
Host smart-9dd0daad-6f9b-48c6-9136-348299ade1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428040697 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.428040697
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.3557503139
Short name T27
Test name
Test status
Simulation time 47518348 ps
CPU time 0.74 seconds
Started Jun 01 01:30:57 PM PDT 24
Finished Jun 01 01:30:58 PM PDT 24
Peak memory 205512 kb
Host smart-e12fdaa1-32d9-4047-8239-c20f2efbb8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557503139 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
3557503139
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.648119192
Short name T5
Test name
Test status
Simulation time 1156914136 ps
CPU time 20.09 seconds
Started Jun 01 01:31:00 PM PDT 24
Finished Jun 01 01:31:20 PM PDT 24
Peak memory 206620 kb
Host smart-d4027a10-15f6-4d21-8ce6-3a64eb3b50ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648119192 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.648119192
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.997322769
Short name T143
Test name
Test status
Simulation time 51355266 ps
CPU time 0.75 seconds
Started Jun 01 01:30:23 PM PDT 24
Finished Jun 01 01:30:24 PM PDT 24
Peak memory 205492 kb
Host smart-afc46f46-022a-4719-b2fa-5ceb5d12c6bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997322769 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.997322769
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.2602227913
Short name T24
Test name
Test status
Simulation time 976320763 ps
CPU time 7.32 seconds
Started Jun 01 01:30:26 PM PDT 24
Finished Jun 01 01:30:34 PM PDT 24
Peak memory 232812 kb
Host smart-d29a9ddc-c9bd-4d11-bb9a-b2718c540b80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602227913 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.2602227913
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.76339708
Short name T154
Test name
Test status
Simulation time 1326866114 ps
CPU time 32.16 seconds
Started Jun 01 01:30:28 PM PDT 24
Finished Jun 01 01:31:01 PM PDT 24
Peak memory 207324 kb
Host smart-b70ab616-5abb-4d0b-82b9-85e4d1ba3f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76339708 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.76339708
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.3036954421
Short name T81
Test name
Test status
Simulation time 24778849 ps
CPU time 0.88 seconds
Started Jun 01 01:30:59 PM PDT 24
Finished Jun 01 01:31:00 PM PDT 24
Peak memory 205468 kb
Host smart-77ba3367-6ab3-4a5c-9ecb-0de4c0a05396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036954421 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
3036954421
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.1269966063
Short name T12
Test name
Test status
Simulation time 2485792658 ps
CPU time 19.73 seconds
Started Jun 01 01:30:57 PM PDT 24
Finished Jun 01 01:31:17 PM PDT 24
Peak memory 208116 kb
Host smart-cee162ab-821b-4ec7-89ef-b75d555a6bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269966063 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.1269966063
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.2921708052
Short name T138
Test name
Test status
Simulation time 59536257 ps
CPU time 0.84 seconds
Started Jun 01 01:30:56 PM PDT 24
Finished Jun 01 01:30:58 PM PDT 24
Peak memory 205416 kb
Host smart-3302556f-5748-4a65-ac99-5781837e2619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921708052 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
2921708052
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.221550109
Short name T119
Test name
Test status
Simulation time 1311358971 ps
CPU time 13.49 seconds
Started Jun 01 01:30:57 PM PDT 24
Finished Jun 01 01:31:11 PM PDT 24
Peak memory 208144 kb
Host smart-7bac8d32-d893-4438-956b-be97c27d7427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221550109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.221550109
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.2638063780
Short name T127
Test name
Test status
Simulation time 19999109 ps
CPU time 0.81 seconds
Started Jun 01 01:30:59 PM PDT 24
Finished Jun 01 01:31:00 PM PDT 24
Peak memory 205404 kb
Host smart-5b3608c6-c5ad-411d-8b03-369b3bafc3cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638063780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
2638063780
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.3451504930
Short name T117
Test name
Test status
Simulation time 447333484 ps
CPU time 17.03 seconds
Started Jun 01 01:30:56 PM PDT 24
Finished Jun 01 01:31:13 PM PDT 24
Peak memory 206644 kb
Host smart-bbec4847-e301-4cdf-8143-ac25c39bc596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451504930 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.3451504930
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.2576835546
Short name T31
Test name
Test status
Simulation time 11975061 ps
CPU time 0.75 seconds
Started Jun 01 01:30:58 PM PDT 24
Finished Jun 01 01:30:59 PM PDT 24
Peak memory 205512 kb
Host smart-087235a8-bb08-4e1d-b7f8-54606f9b6db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576835546 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
2576835546
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.3193123695
Short name T130
Test name
Test status
Simulation time 55872371 ps
CPU time 0.75 seconds
Started Jun 01 01:30:58 PM PDT 24
Finished Jun 01 01:30:59 PM PDT 24
Peak memory 205480 kb
Host smart-c2cff03c-4e73-4e80-b17b-ebbce621e708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193123695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
3193123695
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.2026601864
Short name T118
Test name
Test status
Simulation time 1321815743 ps
CPU time 21.25 seconds
Started Jun 01 01:31:01 PM PDT 24
Finished Jun 01 01:31:23 PM PDT 24
Peak memory 207388 kb
Host smart-2f55331b-157e-4d8a-8a8d-562557014f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026601864 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.2026601864
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.3574386099
Short name T123
Test name
Test status
Simulation time 26790827 ps
CPU time 0.74 seconds
Started Jun 01 01:30:58 PM PDT 24
Finished Jun 01 01:30:59 PM PDT 24
Peak memory 205484 kb
Host smart-9c3edf60-33b2-44ec-be2f-518b2c7d5ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574386099 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
3574386099
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.1458347338
Short name T30
Test name
Test status
Simulation time 10922455 ps
CPU time 0.72 seconds
Started Jun 01 01:30:58 PM PDT 24
Finished Jun 01 01:31:00 PM PDT 24
Peak memory 205504 kb
Host smart-eed5b0c3-2c56-4a28-801b-9783b2540597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458347338 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
1458347338
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.3157723079
Short name T115
Test name
Test status
Simulation time 160142725 ps
CPU time 9.78 seconds
Started Jun 01 01:30:58 PM PDT 24
Finished Jun 01 01:31:08 PM PDT 24
Peak memory 207984 kb
Host smart-20903c17-47d6-4774-b81c-aa6cfc9ec38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157723079 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.3157723079
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.1533012218
Short name T128
Test name
Test status
Simulation time 18760661 ps
CPU time 0.78 seconds
Started Jun 01 01:30:57 PM PDT 24
Finished Jun 01 01:30:58 PM PDT 24
Peak memory 205428 kb
Host smart-6be51d55-9539-484c-8672-17282801f9fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533012218 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
1533012218
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.128861140
Short name T161
Test name
Test status
Simulation time 888450563 ps
CPU time 12.81 seconds
Started Jun 01 01:30:59 PM PDT 24
Finished Jun 01 01:31:12 PM PDT 24
Peak memory 206560 kb
Host smart-d4c6de17-8ca4-4f32-a66a-b67990a2833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128861140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.128861140
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.3579983735
Short name T28
Test name
Test status
Simulation time 14026787 ps
CPU time 0.85 seconds
Started Jun 01 01:30:58 PM PDT 24
Finished Jun 01 01:31:00 PM PDT 24
Peak memory 205496 kb
Host smart-cb127677-e341-4eea-9518-4ba93c907710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579983735 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
3579983735
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.182938615
Short name T129
Test name
Test status
Simulation time 42169629453 ps
CPU time 181.89 seconds
Started Jun 01 01:31:01 PM PDT 24
Finished Jun 01 01:34:03 PM PDT 24
Peak memory 208668 kb
Host smart-cd2949b3-c293-4641-8853-1b53abb840d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182938615 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.182938615
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.2424775863
Short name T145
Test name
Test status
Simulation time 77509043 ps
CPU time 0.97 seconds
Started Jun 01 01:31:14 PM PDT 24
Finished Jun 01 01:31:15 PM PDT 24
Peak memory 205580 kb
Host smart-e96da005-659f-4fe9-8ceb-579169e51936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424775863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
2424775863
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.4022401360
Short name T34
Test name
Test status
Simulation time 730688580 ps
CPU time 23.84 seconds
Started Jun 01 01:31:06 PM PDT 24
Finished Jun 01 01:31:30 PM PDT 24
Peak memory 207988 kb
Host smart-3394e728-7f3e-4cd7-ae22-1547f3ee5208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022401360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.4022401360
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.2599004045
Short name T131
Test name
Test status
Simulation time 15088852 ps
CPU time 0.9 seconds
Started Jun 01 01:30:23 PM PDT 24
Finished Jun 01 01:30:24 PM PDT 24
Peak memory 205428 kb
Host smart-2fc512a2-d706-4224-82a0-f3ee5636c5fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599004045 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.2
599004045
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.361937287
Short name T146
Test name
Test status
Simulation time 201089607 ps
CPU time 0.71 seconds
Started Jun 01 01:30:22 PM PDT 24
Finished Jun 01 01:30:23 PM PDT 24
Peak memory 205500 kb
Host smart-3a96cb42-002b-407f-9cfa-86277393e836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361937287 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.361937287
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.3915140005
Short name T139
Test name
Test status
Simulation time 34404536 ps
CPU time 0.78 seconds
Started Jun 01 01:30:24 PM PDT 24
Finished Jun 01 01:30:26 PM PDT 24
Peak memory 205508 kb
Host smart-18b8414f-ebb8-4251-8d0e-2ba52ccd02f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915140005 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.3
915140005
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.761025416
Short name T163
Test name
Test status
Simulation time 7864517228 ps
CPU time 33.7 seconds
Started Jun 01 01:30:28 PM PDT 24
Finished Jun 01 01:31:02 PM PDT 24
Peak memory 208288 kb
Host smart-c1e044e5-eda6-403a-90f9-e77653cd2f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761025416 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.761025416
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.2065742437
Short name T17
Test name
Test status
Simulation time 39430314 ps
CPU time 0.72 seconds
Started Jun 01 01:30:22 PM PDT 24
Finished Jun 01 01:30:23 PM PDT 24
Peak memory 205512 kb
Host smart-b589f43b-b696-4299-9cac-6fe5ad7bed84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065742437 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.2
065742437
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.3904930012
Short name T108
Test name
Test status
Simulation time 3738322787 ps
CPU time 20.12 seconds
Started Jun 01 01:30:26 PM PDT 24
Finished Jun 01 01:30:47 PM PDT 24
Peak memory 207948 kb
Host smart-6e98b933-bfce-450d-b7d7-e8f47bd200a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904930012 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.3904930012
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.2867425776
Short name T149
Test name
Test status
Simulation time 70929016 ps
CPU time 0.71 seconds
Started Jun 01 01:30:24 PM PDT 24
Finished Jun 01 01:30:25 PM PDT 24
Peak memory 205456 kb
Host smart-4489a874-7a0a-4365-9a10-c5cecb2c1c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867425776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.2
867425776
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.1677864762
Short name T126
Test name
Test status
Simulation time 2301025965 ps
CPU time 19.8 seconds
Started Jun 01 01:30:28 PM PDT 24
Finished Jun 01 01:30:48 PM PDT 24
Peak memory 206480 kb
Host smart-d509356c-5663-4be9-b65c-45ef3a1904cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677864762 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.1677864762
Directory /workspace/9.keymgr_dpe_smoke/latest
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