ADC_CTRL Simulation Results

Monday May 15 2023 07:07:46 UTC

GitHub Revision: `3d5660d90`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 705130430

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.590s	5.957ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.490s	1.378ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.010s	551.471us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.502m	39.652ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.330s	1.434ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.000s	531.336us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.010s	551.471us	20	20	100.00
		adc_ctrl_csr_aliasing	3.330s	1.434ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	17.867m	496.579ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.722m	495.323ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.656m	492.946ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.892m	498.330ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.051m	504.409ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.711m	500.992ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.145m	528.728ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	16.900m	499.011ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.800s	5.185ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.571m	44.675ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.823m	137.834ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	28.347m	633.456ms	44	50	88.00
V2	alert_test	adc_ctrl_alert_test	1.830s	517.935us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.870s	525.748us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.990s	345.846us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.990s	345.846us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.490s	1.378ms	5	5	100.00
		adc_ctrl_csr_rw	2.010s	551.471us	20	20	100.00
		adc_ctrl_csr_aliasing	3.330s	1.434ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.880s	2.745ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.490s	1.378ms	5	5	100.00
		adc_ctrl_csr_rw	2.010s	551.471us	20	20	100.00
		adc_ctrl_csr_aliasing	3.330s	1.434ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.880s	2.745ms	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	tl_intg_err	adc_ctrl_sec_cm	19.550s	7.888ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.810s	8.836ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.810s	8.836ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.877m	558.012ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			892	920	96.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	99.01	95.70	100.00	100.00	98.18	98.64	91.47

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 22 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 22 failures.
  - 1.adc_ctrl_stress_all_with_rand_reset.1884697455
    Line 364, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 72302261814 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 72302261814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 5.adc_ctrl_stress_all_with_rand_reset.686272202
    Line 332, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 4957103519 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 4957103519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 20 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 6 failures:

Test adc_ctrl_stress_all has 6 failures.

2.adc_ctrl_stress_all.2212650640
Line 328, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 337254864482 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 337254864482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.adc_ctrl_stress_all.1142289758
Line 346, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 490152332037 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 490152332037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.