ADC_CTRL Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.330s	5.601ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.400s	1.484ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.900s	537.448us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.723m	26.593ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.000s	1.226ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	552.989us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.900s	537.448us	20	20	100.00
		adc_ctrl_csr_aliasing	3.000s	1.226ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.523m	488.538ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.918m	485.315ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.095m	492.476ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.264m	495.765ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.420m	640.290ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.862m	589.701ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.778m	494.503ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	14.252m	350.378ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.730s	5.424ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.855m	46.256ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.418m	143.284ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	31.311m	720.337ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.800s	472.084us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.970s	507.767us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.670s	541.028us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.670s	541.028us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.400s	1.484ms	5	5	100.00
		adc_ctrl_csr_rw	1.900s	537.448us	20	20	100.00
		adc_ctrl_csr_aliasing	3.000s	1.226ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.490s	4.925ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.400s	1.484ms	5	5	100.00
		adc_ctrl_csr_rw	1.900s	537.448us	20	20	100.00
		adc_ctrl_csr_aliasing	3.000s	1.226ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.490s	4.925ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	11.780s	4.447ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.910s	8.466ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.910s	8.466ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.729m	930.096ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.07	96.67	100.00	100.00	98.83	98.33	91.32

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.adc_ctrl_stress_all_with_rand_reset.2315431268234802779841718279548243999557856785846636916279660873502722102540
    Line 425, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 72593689202 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 72593689202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 41.adc_ctrl_filters_both.108431338036066249887682248688581626180046116081380930865390910411519831493153
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `b938dde05c`