ADC_CTRL Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 8.890s 5.789ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.470s 1.245ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.570s 384.116us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 31.610s 18.149ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 3.280s 779.113us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 1.540s 453.794us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.570s 384.116us 20 20 100.00
adc_ctrl_csr_aliasing 3.280s 779.113us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 11.342m 492.566ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 11.387m 492.210ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 11.404m 489.070ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 11.408m 489.543ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 11.423m 497.525ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 11.252m 490.036ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 11.665m 499.419ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 9.662m 490.810ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 7.950s 5.241ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.092m 47.215ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 5.918m 76.236ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 35.462m 1.274s 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.210s 348.920us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.190s 349.902us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.080s 504.061us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.080s 504.061us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.470s 1.245ms 5 5 100.00
adc_ctrl_csr_rw 1.570s 384.116us 20 20 100.00
adc_ctrl_csr_aliasing 3.280s 779.113us 5 5 100.00
adc_ctrl_same_csr_outstanding 8.410s 5.145ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.470s 1.245ms 5 5 100.00
adc_ctrl_csr_rw 1.570s 384.116us 20 20 100.00
adc_ctrl_csr_aliasing 3.280s 779.113us 5 5 100.00
adc_ctrl_same_csr_outstanding 8.410s 5.145ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 11.540s 7.810ms 5 5 100.00
adc_ctrl_tl_intg_err 14.240s 8.325ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 14.240s 8.325ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 3.766m 833.283ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
87.13 98.98 94.63 100.00 97.22 97.79 92.18 29.08

Past Results