ADC_CTRL Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	27.090s	5.949ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	6.480s	1.127ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.120s	351.178us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.999m	53.170ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.420s	1.234ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.950s	545.695us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.120s	351.178us	20	20	100.00
		adc_ctrl_csr_aliasing	6.420s	1.234ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	22.706m	494.569ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	26.759m	495.669ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	25.413m	494.852ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	29.919m	493.644ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	33.636m	614.192ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	30.491m	600.886ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.627m	499.747ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	27.097m	513.759ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	23.710s	5.420ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.950m	44.729ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	18.646m	136.222ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.303h	2.537s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	3.020s	496.802us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.140s	451.317us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.930s	499.982us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.930s	499.982us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	6.480s	1.127ms	5	5	100.00
		adc_ctrl_csr_rw	3.120s	351.178us	20	20	100.00
		adc_ctrl_csr_aliasing	6.420s	1.234ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.690s	4.833ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	6.480s	1.127ms	5	5	100.00
		adc_ctrl_csr_rw	3.120s	351.178us	20	20	100.00
		adc_ctrl_csr_aliasing	6.420s	1.234ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.690s	4.833ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	27.840s	7.310ms	5	5	100.00
		adc_ctrl_tl_intg_err	32.060s	8.203ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	32.060s	8.203ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	1.349m	819.184ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.07	96.67	100.00	100.00	98.82	98.33	90.82

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 20.adc_ctrl_filters_both.86442791355571173548941415073596044698527028787763345194959467625893181468098
      Line 170, in log /workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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