ADC_CTRL Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: `877a77116`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.130s	5.818ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.600s	1.270ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.200s	549.486us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	24.190s	26.188ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.160s	985.296us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.120s	560.262us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.200s	549.486us	20	20	100.00
		adc_ctrl_csr_aliasing	4.160s	985.296us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.043m	498.357ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.233m	486.888ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.495m	494.328ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.692m	502.448ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.106m	492.986ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.962m	500.245ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.780m	496.061ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.222m	497.348ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.240s	5.524ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.679m	45.705ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.520m	129.816ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	26.187m	589.578ms	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	1.810s	488.484us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.750s	477.132us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.270s	453.953us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.270s	453.953us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.600s	1.270ms	5	5	100.00
		adc_ctrl_csr_rw	2.200s	549.486us	20	20	100.00
		adc_ctrl_csr_aliasing	4.160s	985.296us	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.400s	4.610ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.600s	1.270ms	5	5	100.00
		adc_ctrl_csr_rw	2.200s	549.486us	20	20	100.00
		adc_ctrl_csr_aliasing	4.160s	985.296us	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.400s	4.610ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	tl_intg_err	adc_ctrl_sec_cm	19.530s	7.834ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.090s	8.538ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.090s	8.538ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.889m	266.236ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			894	920	97.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.53	99.01	95.70	100.00	100.00	98.18	98.64	91.19

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 22 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 22 failures.
  - 2.adc_ctrl_stress_all_with_rand_reset.4165491533
    Line 393, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 78984562823 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 78984562823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 4.adc_ctrl_stress_all_with_rand_reset.932160385
    Line 320, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 2079134653 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 2079134653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 20 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 4 failures:

Test adc_ctrl_stress_all has 4 failures.

8.adc_ctrl_stress_all.1925687677
Line 363, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 656123032596 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 656123032596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.adc_ctrl_stress_all.2868113255
Line 364, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 662683803700 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 662683803700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.