ADC_CTRL Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.870s	6.049ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.250s	679.186us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.000s	572.560us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.349m	36.561ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.350s	1.022ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.100s	582.709us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.000s	572.560us	20	20	100.00
		adc_ctrl_csr_aliasing	4.350s	1.022ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.736m	491.974ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.755m	491.217ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.204m	501.992ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.794m	498.883ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.210m	656.019ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.917m	611.575ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.334m	593.874ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	14.582m	376.122ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.440s	5.120ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.703m	44.035ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	10.479m	121.711ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.888h	4.262s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.900s	521.574us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.750s	489.795us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.520s	398.197us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.520s	398.197us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.250s	679.186us	5	5	100.00
		adc_ctrl_csr_rw	2.000s	572.560us	20	20	100.00
		adc_ctrl_csr_aliasing	4.350s	1.022ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.950s	5.216ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.250s	679.186us	5	5	100.00
		adc_ctrl_csr_rw	2.000s	572.560us	20	20	100.00
		adc_ctrl_csr_aliasing	4.350s	1.022ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.950s	5.216ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	10.450s	4.208ms	5	5	100.00
		adc_ctrl_tl_intg_err	12.420s	8.517ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	12.420s	8.517ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	21.748m	560.797ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			917	920	99.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.07	96.67	100.00	100.00	98.83	98.33	91.42

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.adc_ctrl_stress_all_with_rand_reset.83328009565841367193077697500691639557535046495797505609469918904584875809896
    Line 375, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63081659162 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 63081659162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 6.adc_ctrl_stress_all_with_rand_reset.7305208754102318774524098065890377375512017428523772265552383042580984979533
    Line 381, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 55295549264 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 55295549264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 40.adc_ctrl_filters_both.82310777519461475943200121242966717791483516125236952796508659304997190851483
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a47820eb4c`