ADC_CTRL Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	29.690s	6.109ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.400s	742.966us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.720s	527.879us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.371m	37.885ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.200s	815.740us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.720s	503.893us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.720s	527.879us	20	20	100.00
		adc_ctrl_csr_aliasing	4.200s	815.740us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	27.653m	486.970ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	27.295m	499.251ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	26.954m	481.345ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	26.887m	491.752ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	28.500m	603.571ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	32.288m	620.409ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	29.378m	558.533ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.108m	545.888ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	25.150s	5.322ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	3.399m	43.959ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	18.534m	142.025ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	39.591m	672.039ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	3.500s	523.071us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.400s	518.354us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.860s	521.794us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.860s	521.794us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.400s	742.966us	5	5	100.00
		adc_ctrl_csr_rw	3.720s	527.879us	20	20	100.00
		adc_ctrl_csr_aliasing	4.200s	815.740us	5	5	100.00
		adc_ctrl_same_csr_outstanding	31.460s	4.909ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.400s	742.966us	5	5	100.00
		adc_ctrl_csr_rw	3.720s	527.879us	20	20	100.00
		adc_ctrl_csr_aliasing	4.200s	815.740us	5	5	100.00
		adc_ctrl_same_csr_outstanding	31.460s	4.909ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	26.550s	8.202ms	5	5	100.00
		adc_ctrl_tl_intg_err	32.400s	8.992ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	32.400s	8.992ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	15.748m	1.354s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.07	96.67	100.00	100.00	98.83	98.33	91.64

Failure Buckets

• Offending '(np_sample_cnt_q == '0)' has 1 failures:

  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.adc_ctrl_stress_all_with_rand_reset.67275124921582583761161482120320030195148035427834107529301943853447681735514
      Line 201, in log /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(np_sample_cnt_q == '0)'
        UVM_ERROR @ 221147390539 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
        UVM_INFO @ 221147390539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test adc_ctrl_filters_both has 1 failures.

    • 8.adc_ctrl_filters_both.62784405654846018354505522512292212830583600818075638939270770228580830427104
      Line 170, in log /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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