Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1207304	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1162476

1

T5

161

T6

7

T7

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2087247	1			T5	34		T6	11		T7	19
values[0x0]	141340	1			T5	61		T6	9		T7	9
values[0x1]	141193	1			T5	84		T6	4		T7	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	971914	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1397866

1

T5

172

T6

12

T7

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10003	1			T1	17		T2	5		T3	4
valid_sources[0x01]	22784	1			T2	3		T3	5		T4	20
valid_sources[0x02]	6998	1			T1	2		T2	3		T3	1
valid_sources[0x03]	6949	1			T1	12		T2	3		T4	19
valid_sources[0x04]	11054	1			T5	4		T1	3		T2	2
valid_sources[0x05]	6921	1			T5	2		T1	14		T2	6
valid_sources[0x06]	10949	1			T1	18		T2	4		T3	2
valid_sources[0x07]	7016	1			T5	1		T1	10		T2	4
valid_sources[0x08]	9109	1			T5	2		T1	3		T2	4
valid_sources[0x09]	9040	1			T1	8		T2	2		T4	23
valid_sources[0x0a]	6966	1			T2	2		T3	2		T4	13
valid_sources[0x0b]	6803	1			T5	1		T1	5		T2	7
valid_sources[0x0c]	10672	1			T1	4		T2	2		T3	4
valid_sources[0x0d]	7822	1			T5	2		T1	14		T3	8
valid_sources[0x0e]	12303	1			T5	3		T1	6		T2	3
valid_sources[0x0f]	19929	1			T1	3		T2	1		T26	1
valid_sources[0x10]	7998	1			T1	4		T2	4		T3	1
valid_sources[0x11]	7129	1			T5	2		T6	2		T1	4
valid_sources[0x12]	15180	1			T7	1		T2	6		T3	2
valid_sources[0x13]	7136	1			T1	1		T2	4		T3	3
valid_sources[0x14]	6668	1			T5	2		T3	2		T4	23
valid_sources[0x15]	6840	1			T5	1		T1	2		T2	3
valid_sources[0x16]	18982	1			T5	1		T2	3		T3	2
valid_sources[0x17]	6546	1			T1	11		T2	3		T3	1
valid_sources[0x18]	16133	1			T5	2		T2	6		T3	3
valid_sources[0x19]	6990	1			T1	6		T2	1		T3	3
valid_sources[0x1a]	9021	1			T5	1		T1	13		T2	5
valid_sources[0x1b]	13522	1			T5	3		T7	2		T1	25
valid_sources[0x1c]	8218	1			T5	1		T1	3		T2	6
valid_sources[0x1d]	6713	1			T5	1		T7	2		T2	2
valid_sources[0x1e]	6937	1			T1	5		T2	4		T3	2
valid_sources[0x1f]	6689	1			T5	1		T2	1		T4	29
valid_sources[0x20]	12614	1			T1	14		T2	8		T3	3
valid_sources[0x21]	15607	1			T1	1		T2	2		T3	4
valid_sources[0x22]	11133	1			T5	3		T1	1		T2	3
valid_sources[0x23]	6857	1			T1	31		T2	6		T3	2
valid_sources[0x24]	6977	1			T1	2		T2	5		T3	7
valid_sources[0x25]	6781	1			T7	1		T1	1		T2	4
valid_sources[0x26]	11427	1			T1	19		T2	5		T3	2
valid_sources[0x27]	6511	1			T5	2		T1	26		T2	1
valid_sources[0x28]	6920	1			T5	1		T2	5		T3	4
valid_sources[0x29]	10006	1			T5	1		T1	47		T2	5
valid_sources[0x2a]	7112	1			T5	2		T7	1		T2	5
valid_sources[0x2b]	7240	1			T5	1		T1	2		T2	4
valid_sources[0x2c]	11430	1			T1	13		T2	5		T3	2
valid_sources[0x2d]	11680	1			T1	10		T2	1		T3	4
valid_sources[0x2e]	13692	1			T1	9		T2	2		T25	5
valid_sources[0x2f]	7607	1			T5	1		T1	20		T2	4
valid_sources[0x30]	7137	1			T1	4		T2	6		T3	2
valid_sources[0x31]	6646	1			T2	2		T3	3		T4	28
valid_sources[0x32]	9937	1			T1	7		T4	28		T11	3
valid_sources[0x33]	7007	1			T1	4		T2	3		T3	2
valid_sources[0x34]	7854	1			T2	5		T3	1		T4	15
valid_sources[0x35]	6982	1			T2	3		T3	2		T4	23
valid_sources[0x36]	7163	1			T7	1		T2	3		T26	1
valid_sources[0x37]	6847	1			T2	4		T4	32		T38	3
valid_sources[0x38]	7001	1			T1	22		T2	3		T3	3
valid_sources[0x39]	9133	1			T6	2		T7	1		T2	3
valid_sources[0x3a]	9813	1			T2	3		T3	3		T4	28
valid_sources[0x3b]	11072	1			T5	2		T2	3		T3	2
valid_sources[0x3c]	7035	1			T5	3		T1	4		T2	2
valid_sources[0x3d]	7190	1			T7	1		T1	7		T2	6
valid_sources[0x3e]	8539	1			T2	3		T3	2		T4	19
valid_sources[0x3f]	11390	1			T5	1		T7	1		T1	6
valid_sources[0x40]	7276	1			T5	1		T1	1		T2	3
valid_sources[0x41]	11484	1			T5	1		T1	3		T2	1
valid_sources[0x42]	8993	1			T5	3		T7	1		T2	2
valid_sources[0x43]	6899	1			T2	4		T4	26		T27	3
valid_sources[0x44]	7081	1			T5	1		T2	2		T3	2
valid_sources[0x45]	11323	1			T2	1		T4	25		T39	2
valid_sources[0x46]	7649	1			T2	2		T26	1		T3	2
valid_sources[0x47]	7051	1			T6	9		T1	15		T2	1
valid_sources[0x48]	6814	1			T5	1		T1	1		T2	2
valid_sources[0x49]	6887	1			T2	2		T3	2		T4	25
valid_sources[0x4a]	6943	1			T1	9		T2	3		T26	1
valid_sources[0x4b]	6922	1			T1	19		T2	3		T4	12
valid_sources[0x4c]	11108	1			T5	2		T2	2		T3	1
valid_sources[0x4d]	6590	1			T5	1		T1	11		T2	6
valid_sources[0x4e]	6732	1			T5	1		T1	15		T2	2
valid_sources[0x4f]	6722	1			T5	2		T1	4		T2	1
valid_sources[0x50]	11220	1			T1	14		T2	2		T3	4
valid_sources[0x51]	8101	1			T2	1		T3	6		T4	18
valid_sources[0x52]	8036	1			T5	1		T1	4		T2	2
valid_sources[0x53]	7721	1			T5	1		T1	11		T2	6
valid_sources[0x54]	7301	1			T1	15		T4	20		T38	1
valid_sources[0x55]	7965	1			T1	1		T2	1		T3	10
valid_sources[0x56]	11144	1			T1	1		T2	6		T3	5
valid_sources[0x57]	8177	1			T2	3		T3	4		T4	20
valid_sources[0x58]	7084	1			T7	1		T1	22		T2	7
valid_sources[0x59]	6778	1			T2	3		T26	1		T3	3
valid_sources[0x5a]	10733	1			T7	3		T1	17		T2	1
valid_sources[0x5b]	14243	1			T2	1		T3	6		T4	36
valid_sources[0x5c]	12048	1			T2	3		T4	23		T38	1
valid_sources[0x5d]	6844	1			T5	1		T3	5		T4	13
valid_sources[0x5e]	6808	1			T2	3		T4	32		T10	20
valid_sources[0x5f]	6960	1			T5	6		T1	43		T2	1
valid_sources[0x60]	7490	1			T1	4		T2	6		T3	2
valid_sources[0x61]	7160	1			T5	1		T1	15		T2	2
valid_sources[0x62]	11712	1			T5	1		T1	8		T2	1
valid_sources[0x63]	11138	1			T5	1		T6	2		T2	3
valid_sources[0x64]	8283	1			T5	1		T1	14		T2	3
valid_sources[0x65]	7950	1			T5	1		T2	3		T3	2
valid_sources[0x66]	11761	1			T1	1		T3	2		T4	32
valid_sources[0x67]	12425	1			T1	6		T2	2		T4	9
valid_sources[0x68]	6700	1			T5	2		T1	1		T2	3
valid_sources[0x69]	15759	1			T5	1		T1	5		T2	3
valid_sources[0x6a]	9492	1			T1	1		T2	7		T3	1
valid_sources[0x6b]	11170	1			T1	2		T2	3		T3	1
valid_sources[0x6c]	6608	1			T5	1		T7	1		T2	1
valid_sources[0x6d]	6907	1			T2	3		T3	2		T4	33
valid_sources[0x6e]	7936	1			T5	1		T7	2		T2	1
valid_sources[0x6f]	6597	1			T5	1		T2	1		T3	6
valid_sources[0x70]	13024	1			T5	1		T7	1		T1	26
valid_sources[0x71]	15606	1			T1	1		T3	3		T4	34
valid_sources[0x72]	18362	1			T5	1		T1	23		T2	2
valid_sources[0x73]	19983	1			T5	2		T2	2		T4	26
valid_sources[0x74]	9513	1			T5	1		T3	2		T4	14
valid_sources[0x75]	15369	1			T5	1		T2	4		T4	13
valid_sources[0x76]	7300	1			T2	3		T4	25		T28	1
valid_sources[0x77]	6899	1			T1	6		T2	3		T3	5
valid_sources[0x78]	7746	1			T2	2		T3	3		T4	28
valid_sources[0x79]	7488	1			T5	1		T1	2		T2	2
valid_sources[0x7a]	6941	1			T5	2		T2	2		T3	1
valid_sources[0x7b]	7049	1			T5	2		T1	27		T2	5
valid_sources[0x7c]	8016	1			T1	23		T2	5		T25	4
valid_sources[0x7d]	11203	1			T5	1		T1	1		T2	4
valid_sources[0x7e]	11668	1			T1	4		T2	1		T3	3
valid_sources[0x7f]	7880	1			T1	6		T2	1		T4	25
valid_sources[0x80]	6832	1			T5	2		T1	2		T2	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1040091

1

T5

34

T6

4

T7

9

values[0x0]

all_enables

biggest_size

71014

1

T5

60

T6

2

T7

3

values[0x1]

all_enables

biggest_size

51371

1

T5

67

T6

1

T1

224