Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28786	1			T1	2		T3	307		T4	7
auto[PWRUP]	112	1			T94	3		T34	1		T121	2
auto[ONEST_0]	70	1			T94	2		T34	3		T36	1
auto[ONEST_021]	17	1			T36	1		T168	1		T199	1
auto[ONEST_1]	82	1			T12	2		T94	1		T121	2
auto[ONEST_DONE]	6	1			T91	1		T200	1		T159	1
auto[LP_0]	122	1			T12	5		T94	2		T121	4
auto[LP_021]	19	1			T94	1		T34	1		T201	1
auto[LP_1]	118	1			T12	1		T94	4		T34	1
auto[LP_EVAL]	52	1			T12	1		T94	1		T36	2
auto[LP_SLP]	413	1			T12	8		T94	6		T34	4
auto[LP_PWRUP]	31	1			T121	1		T37	2		T202	3
auto[NP_0]	138	1			T12	2		T94	2		T91	1
auto[NP_021]	27	1			T34	1		T108	1		T201	1
auto[NP_1]	148	1			T12	2		T94	3		T34	1
auto[NP_EVAL]	42	1			T12	1		T94	1		T121	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T170

1

T203

1

T204

1

min

28284

1

T1

2

T3

307

T4

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28289	1			T1	2		T3	307		T4	7
pow[0x1]	8	1			T121	1		T168	1		T133	1
pow[0x2]	25	1			T94	1		T34	1		T121	1
pow[0x3]	24	1			T108	1		T55	1		T168	1
pow[0x4]	60	1			T12	3		T34	1		T37	2
pow[0x5]	88	1			T94	2		T37	1		T108	1
pow[0x6]	251	1			T12	1		T94	7		T34	7
pow[0x7]	447	1			T12	7		T94	11		T34	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

176

1

T12

1

T94

2

T34

1

min

27887

1

T1

2

T3

307

T4

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27887	1			T1	2		T3	307		T4	7
pow[0x2]	1	1			T205	1		-	-		-	-
pow[0x4]	1	1			T206	1		-	-		-	-
pow[0x5]	3	1			T201	1		T207	1		T206	1
pow[0x6]	2	1			T91	1		T159	1		-	-
pow[0x8]	9	1			T94	1		T208	1		T209	1
pow[0x9]	12	1			T94	1		T210	1		T211	1
pow[0xa]	21	1			T36	1		T37	1		T201	2
pow[0xb]	26	1			T12	1		T91	1		T55	1
pow[0xc]	59	1			T12	1		T94	1		T34	1
pow[0xd]	153	1			T12	1		T94	4		T34	2
pow[0xe]	262	1			T12	1		T94	3		T34	2
pow[0xf]	534	1			T12	10		T94	11		T34	4