Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2115	1			T1	20		T27	1		T35	2
auto[PWRUP]	135	1			T12	1		T94	2		T34	1
auto[ONEST_0]	66	1			T12	2		T94	1		T121	1
auto[ONEST_021]	18	1			T12	1		T121	1		T208	1
auto[ONEST_1]	104	1			T12	1		T121	1		T202	2
auto[ONEST_DONE]	5	1			T200	1		T345	1		T159	2
auto[LP_0]	114	1			T12	1		T36	2		T121	2
auto[LP_021]	24	1			T12	1		T346	1		T170	1
auto[LP_1]	125	1			T17	1		T94	1		T91	1
auto[LP_EVAL]	47	1			T34	1		T201	3		T202	1
auto[LP_SLP]	493	1			T12	12		T94	7		T214	1
auto[LP_PWRUP]	31	1			T94	2		T37	1		T347	2
auto[NP_0]	203	1			T12	3		T17	1		T94	4
auto[NP_021]	48	1			T12	1		T94	3		T34	1
auto[NP_1]	224	1			T12	1		T17	2		T94	2
auto[NP_EVAL]	35	1			T214	1		T34	1		T121	1
auto[NP_DONE]	1	1			T348	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T201

1

T133

1

T349

1

min

1894

1

T1

20

T27

1

T35

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1903	1			T1	20		T27	1		T35	2
pow[0x1]	10	1			T202	1		T279	1		T350	1
pow[0x2]	17	1			T347	1		T351	1		T352	1
pow[0x3]	27	1			T17	1		T121	1		T108	1
pow[0x4]	59	1			T12	3		T94	1		T34	2
pow[0x5]	121	1			T12	4		T94	1		T36	2
pow[0x6]	230	1			T12	2		T94	4		T34	1
pow[0x7]	477	1			T12	4		T94	8		T34	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T12

2

T94

4

T36

1

min

1295

1

T1

20

T27

1

T35

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1301	1			T1	20		T27	1		T35	2
pow[0x1]	17	1			T90	1		T140	2		T298	4
pow[0x2]	23	1			T34	1		T108	1		T168	4
pow[0x3]	42	1			T17	1		T214	1		T90	2
pow[0x4]	75	1			T17	2		T214	2		T91	3
pow[0x6]	3	1			T352	1		T205	1		T353	1
pow[0x7]	3	1			T94	1		T159	1		T289	1
pow[0x8]	3	1			T208	1		T265	1		T335	1
pow[0x9]	4	1			T265	1		T354	1		T159	1
pow[0xa]	14	1			T121	1		T346	1		T170	2
pow[0xb]	33	1			T121	1		T201	1		T170	1
pow[0xc]	67	1			T12	1		T36	2		T121	3
pow[0xd]	118	1			T12	2		T94	2		T121	2
pow[0xe]	258	1			T12	7		T94	3		T34	1
pow[0xf]	546	1			T12	5		T17	1		T94	5