Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T18,T19

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T13,T19,T24
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T19,T24
0	1	Covered	T13,T19,T24
1	0	Covered	T13,T19,T24

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T17
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T19
0	1	Covered	T13,T14,T19
1	0	Covered	T13,T14,T17

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T60
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T60,T34
0	1	Covered	T13,T60,T34
1	0	Covered	T13,T17,T60

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T24
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T24
0	1	Covered	T13,T17,T24
1	0	Covered	T13,T17,T24

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T17
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T19
0	1	Covered	T13,T14,T19
1	0	Covered	T13,T14,T17

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T19
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T19
0	1	Covered	T13,T17,T19
1	0	Covered	T13,T17,T19

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T19
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T19,T24
0	1	Covered	T13,T19,T24
1	0	Covered	T13,T17,T19

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T24
1	0	Covered	T12,T13,T17
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T19
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T19
0	1	Covered	T13,T17,T19
1	0	Covered	T13,T17,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T17
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T24
0	1	Covered	T13,T14,T24
1	0	Covered	T13,T14,T17

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T60
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T60,T34
0	1	Covered	T13,T60,T34
1	0	Covered	T13,T17,T60

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T24
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T24
0	1	Covered	T13,T17,T24
1	0	Covered	T13,T17,T24

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T17
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T19
0	1	Covered	T13,T14,T19
1	0	Covered	T13,T14,T17

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T19
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T19
0	1	Covered	T13,T17,T19
1	0	Covered	T13,T17,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T13,T17,T19
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T19,T24
0	1	Covered	T13,T19,T24
1	0	Covered	T13,T17,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T24
1	0	Covered	T12,T13,T17
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T15,T16,T17
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T12,T15,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T14,T15,T16
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T14,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T13,T15,T16
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T13,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T13,T15,T16
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T13,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T13,T15,T16
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T13,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T16
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T12,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T14,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T13,T14,T15

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T18,T19
0	1	Covered	T12,T13,T14
0	0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T19,T24

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T17,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T17,T60

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T17,T60

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T17,T24

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T17,T24

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T14,T17

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T17,T19

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T17,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T17,T19

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T17,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T13,T14,T15

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	31746883	31455002	0	0
gen_filter_match[0].MatchCheck00_A	31746883	9798697	0	0
gen_filter_match[0].MatchCheck01_A	31746883	2450115	0	0
gen_filter_match[0].MatchCheck10_A	31746883	2094221	0	0
gen_filter_match[0].MatchCheck11_A	31746883	17111969	0	0
gen_filter_match[1].MatchCheck00_A	31746883	10725639	0	0
gen_filter_match[1].MatchCheck01_A	31746883	1233804	0	0
gen_filter_match[1].MatchCheck10_A	31746883	1508381	0	0
gen_filter_match[1].MatchCheck11_A	31746883	17987178	0	0
gen_filter_match[2].MatchCheck00_A	31746883	11764708	0	0
gen_filter_match[2].MatchCheck01_A	31746883	832155	0	0
gen_filter_match[2].MatchCheck10_A	31746883	578631	0	0
gen_filter_match[2].MatchCheck11_A	31746883	18279508	0	0
gen_filter_match[3].MatchCheck00_A	31746883	11145616	0	0
gen_filter_match[3].MatchCheck01_A	31746883	317995	0	0
gen_filter_match[3].MatchCheck10_A	31746883	309986	0	0
gen_filter_match[3].MatchCheck11_A	31746883	19681405	0	0
gen_filter_match[4].MatchCheck00_A	31746883	12214545	0	0
gen_filter_match[4].MatchCheck01_A	31746883	66153	0	0
gen_filter_match[4].MatchCheck10_A	31746883	65589	0	0
gen_filter_match[4].MatchCheck11_A	31746883	19108715	0	0
gen_filter_match[5].MatchCheck00_A	31746883	12487316	0	0
gen_filter_match[5].MatchCheck01_A	31746883	7	0	0
gen_filter_match[5].MatchCheck10_A	31746883	90	0	0
gen_filter_match[5].MatchCheck11_A	31746883	18967589	0	0
gen_filter_match[6].MatchCheck00_A	31746883	12036079	0	0
gen_filter_match[6].MatchCheck01_A	31746883	31984	0	0
gen_filter_match[6].MatchCheck10_A	31746883	83133	0	0
gen_filter_match[6].MatchCheck11_A	31746883	19303806	0	0
gen_filter_match[7].MatchCheck00_A	31746883	11986314	0	0
gen_filter_match[7].MatchCheck01_A	31746883	96855	0	0
gen_filter_match[7].MatchCheck10_A	31746883	264755	0	0
gen_filter_match[7].MatchCheck11_A	31746883	19107078	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	31455002	0	0
T12	22019	19108	0	0
T13	102364	102284	0	0
T14	32114	32015	0	0
T15	32684	32606	0	0
T16	33880	33813	0	0
T17	45697	45012	0	0
T18	1167	1086	0	0
T19	72236	71877	0	0
T20	1018	954	0	0
T21	829	748	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	9798697	0	0
T12	22019	18847	0	0
T13	102364	102284	0	0
T14	32114	4	0	0
T15	32684	4	0	0
T16	33880	3	0	0
T17	45697	8729	0	0
T18	1167	1086	0	0
T19	72236	38809	0	0
T20	1018	954	0	0
T21	829	748	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	2450115	0	0
T14	32114	32011	0	0
T15	32684	0	0	0
T16	33880	0	0	0
T17	45697	34792	0	0
T18	1167	0	0	0
T19	72236	0	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	0	0	0
T23	33124	0	0	0
T95	0	32702	0	0
T96	0	34013	0	0
T97	0	32181	0	0
T98	0	34186	0	0
T99	0	33717	0	0
T100	0	33077	0	0
T101	0	33763	0	0
T102	0	32847	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	2094221	0	0
T17	45697	1401	0	0
T18	1167	0	0	0
T19	72236	1	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	0	0	0
T23	33124	0	0	0
T24	99231	0	0	0
T42	85	0	0	0
T43	90	0	0	0
T103	0	32637	0	0
T104	0	32396	0	0
T105	0	32772	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	12686	0	0
T109	0	32715	0	0
T110	0	31788	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	17111969	0	0
T12	22019	261	0	0
T13	102364	0	0	0
T14	32114	0	0	0
T15	32684	32602	0	0
T16	33880	33810	0	0
T17	45697	90	0	0
T18	1167	0	0	0
T19	72236	33067	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	0	34259	0	0
T23	0	33039	0	0
T24	0	32706	0	0
T59	0	32646	0	0
T94	0	42	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	10725639	0	0
T12	22019	19108	0	0
T13	102364	102284	0	0
T14	32114	4	0	0
T15	32684	4	0	0
T16	33880	3	0	0
T17	45697	43610	0	0
T18	1167	1086	0	0
T19	72236	38809	0	0
T20	1018	954	0	0
T21	829	748	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	1233804	0	0
T36	47905	0	0	0
T90	9367	0	0	0
T91	27251	19305	0	0
T95	99832	0	0	0
T101	0	32935	0	0
T103	32700	0	0	0
T105	0	32262	0	0
T111	65941	32601	0	0
T112	0	31842	0	0
T113	0	32459	0	0
T114	0	32894	0	0
T115	0	33793	0	0
T116	0	65785	0	0
T117	0	33982	0	0
T118	8266	0	0	0
T119	33301	0	0	0
T120	31833	0	0	0
T121	35336	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	1508381	0	0
T19	72236	33068	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	0	0	0
T23	33124	0	0	0
T24	99231	0	0	0
T42	85	0	0	0
T43	90	0	0	0
T59	32716	0	0	0
T92	672	0	0	0
T95	0	33792	0	0
T96	0	31737	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T122	0	33242	0	0
T123	0	33366	0	0
T124	0	32645	0	0
T125	0	32882	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	17987178	0	0
T14	32114	32011	0	0
T15	32684	32602	0	0
T16	33880	33810	0	0
T17	45697	1402	0	0
T18	1167	0	0	0
T19	72236	0	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	34259	0	0
T23	33124	33039	0	0
T24	0	33324	0	0
T59	0	32646	0	0
T60	0	100468	0	0
T126	0	99647	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	11764708	0	0
T12	22019	19108	0	0
T13	102364	68334	0	0
T14	32114	32015	0	0
T15	32684	4	0	0
T16	33880	3	0	0
T17	45697	43929	0	0
T18	1167	1086	0	0
T19	72236	39112	0	0
T20	1018	954	0	0
T21	829	748	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	832155	0	0
T36	47905	5604	0	0
T60	100547	33236	0	0
T96	99942	0	0	0
T98	67341	0	0	0
T99	0	32546	0	0
T104	32455	0	0	0
T105	65101	0	0	0
T121	35336	0	0	0
T127	64668	32546	0	0
T128	0	33238	0	0
T129	0	32874	0	0
T130	0	31880	0	0
T131	0	33152	0	0
T132	0	31881	0	0
T133	0	338	0	0
T134	66376	0	0	0
T135	33143	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	578631	0	0
T19	72236	2	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	0	0	0
T23	33124	0	0	0
T24	99231	0	0	0
T42	85	0	0	0
T43	90	0	0	0
T59	32716	0	0	0
T92	672	0	0	0
T101	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T110	0	33170	0	0
T134	0	32191	0	0
T136	0	32976	0	0
T137	0	32004	0	0
T138	0	1	0	0
T139	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	18279508	0	0
T13	102364	33950	0	0
T14	32114	0	0	0
T15	32684	32602	0	0
T16	33880	33810	0	0
T17	45697	1083	0	0
T18	1167	0	0	0
T19	72236	32763	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	34259	0	0
T23	0	33039	0	0
T24	0	65839	0	0
T59	0	32646	0	0
T60	0	33727	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	11145616	0	0
T12	22019	19108	0	0
T13	102364	68334	0	0
T14	32114	32015	0	0
T15	32684	4	0	0
T16	33880	3	0	0
T17	45697	11303	0	0
T18	1167	1086	0	0
T19	72236	6044	0	0
T20	1018	954	0	0
T21	829	748	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	317995	0	0
T101	99168	1	0	0
T102	36193	0	0	0
T108	52894	0	0	0
T115	69489	0	0	0
T128	33329	0	0	0
T140	0	2249	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	33347	0	0
T144	0	33767	0	0
T145	0	1	0	0
T146	0	12234	0	0
T147	0	1	0	0
T148	0	32269	0	0
T149	97523	0	0	0
T150	33631	0	0	0
T151	8979	0	0	0
T152	97962	0	0	0
T153	1173	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	309986	0	0
T19	72236	4	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	0	0	0
T23	33124	0	0	0
T24	99231	0	0	0
T36	0	2	0	0
T42	85	0	0	0
T43	90	0	0	0
T59	32716	0	0	0
T92	672	0	0	0
T101	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	3	0	0
T112	0	33599	0	0
T154	0	1	0	0
T155	0	6	0	0
T156	0	32488	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	19681405	0	0
T13	102364	33950	0	0
T14	32114	0	0	0
T15	32684	32602	0	0
T16	33880	33810	0	0
T17	45697	33709	0	0
T18	1167	0	0	0
T19	72236	65829	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	34259	0	0
T23	0	33039	0	0
T59	0	32646	0	0
T60	0	33727	0	0
T126	0	99647	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	12214545	0	0
T12	22019	19108	0	0
T13	102364	66362	0	0
T14	32114	4	0	0
T15	32684	4	0	0
T16	33880	3	0	0
T17	45697	8818	0	0
T18	1167	1086	0	0
T19	72236	38809	0	0
T20	1018	954	0	0
T21	829	748	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	66153	0	0
T139	65975	0	0	0
T145	0	1	0	0
T157	98134	1	0	0
T158	0	1	0	0
T159	0	33366	0	0
T160	0	32782	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	7781	0	0	0
T164	1183	0	0	0
T165	66228	0	0	0
T166	1179	0	0	0
T167	689	0	0	0
T168	61951	0	0	0
T169	979	0	0	0
T170	25408	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	65589	0	0
T19	72236	2	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	0	0	0
T23	33124	0	0	0
T24	99231	0	0	0
T36	0	2	0	0
T42	85	0	0	0
T43	90	0	0	0
T59	32716	0	0	0
T92	672	0	0	0
T101	0	1	0	0
T106	0	1	0	0
T107	0	2	0	0
T108	0	3	0	0
T154	0	1	0	0
T155	0	9	0	0
T171	0	1	0	0
T172	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	19108715	0	0
T13	102364	35922	0	0
T14	32114	32011	0	0
T15	32684	32602	0	0
T16	33880	33810	0	0
T17	45697	36194	0	0
T18	1167	0	0	0
T19	72236	33066	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	34259	0	0
T23	0	33039	0	0
T59	0	32646	0	0
T60	0	33505	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	12487316	0	0
T12	22019	19108	0	0
T13	102364	68334	0	0
T14	32114	4	0	0
T15	32684	4	0	0
T16	33880	3	0	0
T17	45697	45012	0	0
T18	1167	1086	0	0
T19	72236	39113	0	0
T20	1018	954	0	0
T21	829	748	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	7	0	0
T101	99168	1	0	0
T102	36193	0	0	0
T108	52894	0	0	0
T115	69489	0	0	0
T128	33329	0	0	0
T145	0	1	0	0
T149	97523	0	0	0
T150	33631	0	0	0
T151	8979	0	0	0
T152	97962	0	0	0
T153	1173	0	0	0
T156	0	1	0	0
T158	0	1	0	0
T162	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	90	0	0
T19	72236	1	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	0	0	0
T23	33124	0	0	0
T24	99231	0	0	0
T42	85	0	0	0
T43	90	0	0	0
T59	32716	0	0	0
T92	672	0	0	0
T97	0	1	0	0
T101	0	1	0	0
T103	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0
T154	0	1	0	0
T171	0	1	0	0
T175	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	18967589	0	0
T13	102364	33950	0	0
T14	32114	32011	0	0
T15	32684	32602	0	0
T16	33880	33810	0	0
T17	45697	0	0	0
T18	1167	0	0	0
T19	72236	32763	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	34259	0	0
T23	0	33039	0	0
T24	0	66030	0	0
T59	0	32646	0	0
T60	0	33505	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	12036079	0	0
T12	22019	19108	0	0
T13	102364	35926	0	0
T14	32114	32015	0	0
T15	32684	4	0	0
T16	33880	3	0	0
T17	45697	43929	0	0
T18	1167	1086	0	0
T19	72236	71877	0	0
T20	1018	954	0	0
T21	829	748	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	31984	0	0
T129	32953	0	0	0
T130	114103	0	0	0
T138	67616	1	0	0
T141	97594	1	0	0
T145	0	1	0	0
T147	0	1	0	0
T162	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T176	99874	31974	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	33067	0	0	0
T180	32926	0	0	0
T181	33165	0	0	0
T182	99566	0	0	0
T183	101	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	83133	0	0
T36	47905	1	0	0
T96	99942	0	0	0
T97	64719	1	0	0
T104	32455	0	0	0
T105	65101	0	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	3	0	0
T112	65504	0	0	0
T121	35336	0	0	0
T134	66376	0	0	0
T135	33143	0	0	0
T154	0	1	0	0
T155	0	4	0	0
T171	0	1	0	0
T172	0	1	0	0
T175	0	1	0	0
T184	98074	0	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	19303806	0	0
T13	102364	66358	0	0
T14	32114	0	0	0
T15	32684	32602	0	0
T16	33880	33810	0	0
T17	45697	1083	0	0
T18	1167	0	0	0
T19	72236	0	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	34259	0	0
T23	0	33039	0	0
T24	0	33133	0	0
T59	0	32646	0	0
T60	0	66741	0	0
T126	0	99647	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	11986314	0	0
T12	22019	19108	0	0
T13	102364	35926	0	0
T14	32114	4	0	0
T15	32684	4	0	0
T16	33880	3	0	0
T17	45697	43929	0	0
T18	1167	1086	0	0
T19	72236	71877	0	0
T20	1018	954	0	0
T21	829	748	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	96855	0	0
T101	99168	1	0	0
T102	36193	0	0	0
T108	52894	0	0	0
T115	69489	0	0	0
T117	0	31647	0	0
T128	33329	0	0	0
T145	0	1	0	0
T149	97523	0	0	0
T150	33631	0	0	0
T151	8979	0	0	0
T152	97962	0	0	0
T153	1173	0	0	0
T156	0	1	0	0
T158	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	32062	0	0
T189	0	33131	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	264755	0	0
T36	47905	1	0	0
T90	9367	0	0	0
T95	99832	0	0	0
T97	0	1	0	0
T101	0	2	0	0
T103	32700	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T111	65941	0	0	0
T113	0	33218	0	0
T115	0	33054	0	0
T118	8266	0	0	0
T119	33301	0	0	0
T120	31833	0	0	0
T121	35336	0	0	0
T134	66376	0	0	0
T171	0	1	0	0
T190	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31746883	19107078	0	0
T13	102364	66358	0	0
T14	32114	32011	0	0
T15	32684	32602	0	0
T16	33880	33810	0	0
T17	45697	1083	0	0
T18	1167	0	0	0
T19	72236	0	0	0
T20	1018	0	0	0
T21	829	0	0	0
T22	34322	34259	0	0
T23	0	33039	0	0
T24	0	33324	0	0
T59	0	32646	0	0
T60	0	66963	0	0