Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	5927	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1682	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1686	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1598	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1600	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1563	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1579	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1729	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1821	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1547	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1575	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1508	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1501	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1658	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1697	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1618	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1739	0	0
adc_en_ctl_rd_A	2147483647	1131	0	0
adc_fsm_rst_rd_A	2147483647	1205	0	0
adc_intr_ctl_rd_A	2147483647	1214	0	0
adc_lp_sample_ctl_rd_A	2147483647	1201	0	0
adc_pd_ctl_rd_A	2147483647	1447	0	0
adc_sample_ctl_rd_A	2147483647	1032	0	0
adc_wakeup_ctl_rd_A	2147483647	1034	0	0
intr_enable_rd_A	2147483647	1596	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5927	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	0	0	0
T4	103150	0	0	0
T5	7271	7	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	143	0	0
T39	0	82	0	0
T41	0	445	0	0
T61	0	1	0	0
T63	0	161	0	0
T65	0	613	0	0
T66	0	422	0	0
T67	0	21	0	0
T191	0	4	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1682	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	61	0	0
T4	103150	0	0	0
T5	7271	6	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	8	0	0
T68	0	85	0	0
T70	0	1	0	0
T74	0	26	0	0
T75	0	5	0	0
T192	0	67	0	0
T193	0	86	0	0
T194	0	3	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1686	0	0
T3	101750	41	0	0
T4	103150	0	0	0
T9	2645	0	0	0
T27	8034	0	0	0
T28	15603	0	0	0
T29	8386	0	0	0
T31	6333	0	0	0
T35	35866	0	0	0
T40	22300	0	0	0
T68	0	87	0	0
T70	0	2	0	0
T74	0	27	0	0
T76	0	17	0	0
T84	4570	0	0	0
T88	0	107	0	0
T192	0	30	0	0
T193	0	90	0	0
T194	0	4	0	0
T195	0	59	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1598	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	32	0	0
T4	103150	0	0	0
T5	7271	7	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	5	0	0
T68	0	86	0	0
T70	0	7	0	0
T74	0	7	0	0
T76	0	14	0	0
T192	0	36	0	0
T193	0	83	0	0
T194	0	7	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1600	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	31	0	0
T4	103150	0	0	0
T5	7271	6	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	2	0	0
T68	0	61	0	0
T70	0	5	0	0
T74	0	46	0	0
T76	0	1	0	0
T192	0	30	0	0
T193	0	108	0	0
T194	0	9	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1563	0	0
T3	101750	44	0	0
T4	103150	0	0	0
T9	2645	0	0	0
T27	8034	0	0	0
T28	15603	0	0	0
T29	8386	0	0	0
T31	6333	0	0	0
T35	35866	0	0	0
T40	22300	0	0	0
T68	0	85	0	0
T70	0	7	0	0
T74	0	26	0	0
T75	0	1	0	0
T84	4570	0	0	0
T88	0	123	0	0
T192	0	24	0	0
T193	0	100	0	0
T194	0	19	0	0
T195	0	61	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	24	0	0
T4	103150	0	0	0
T5	7271	3	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T68	0	135	0	0
T70	0	3	0	0
T74	0	5	0	0
T88	0	87	0	0
T192	0	16	0	0
T193	0	88	0	0
T194	0	7	0	0
T195	0	44	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1729	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	39	0	0
T4	103150	0	0	0
T5	7271	1	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	2	0	0
T68	0	89	0	0
T70	0	2	0	0
T74	0	11	0	0
T76	0	11	0	0
T192	0	41	0	0
T193	0	61	0	0
T194	0	4	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1821	0	0
T3	101750	55	0	0
T4	103150	0	0	0
T9	2645	0	0	0
T27	8034	0	0	0
T28	15603	0	0	0
T29	8386	0	0	0
T31	6333	0	0	0
T35	35866	0	0	0
T38	0	9	0	0
T40	22300	0	0	0
T68	0	67	0	0
T70	0	6	0	0
T74	0	34	0	0
T76	0	16	0	0
T84	4570	0	0	0
T192	0	58	0	0
T193	0	131	0	0
T194	0	2	0	0
T195	0	53	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1547	0	0
T3	101750	16	0	0
T4	103150	0	0	0
T9	2645	0	0	0
T27	8034	0	0	0
T28	15603	0	0	0
T29	8386	0	0	0
T31	6333	0	0	0
T35	35866	0	0	0
T40	22300	0	0	0
T68	0	104	0	0
T70	0	2	0	0
T74	0	4	0	0
T76	0	6	0	0
T84	4570	0	0	0
T88	0	118	0	0
T192	0	43	0	0
T193	0	119	0	0
T195	0	29	0	0
T196	0	76	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1575	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	28	0	0
T4	103150	0	0	0
T5	7271	1	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T68	0	89	0	0
T70	0	4	0	0
T74	0	16	0	0
T88	0	110	0	0
T192	0	20	0	0
T193	0	68	0	0
T194	0	11	0	0
T195	0	80	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1508	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	29	0	0
T4	103150	0	0	0
T5	7271	7	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T68	0	90	0	0
T70	0	6	0	0
T74	0	5	0	0
T88	0	87	0	0
T192	0	15	0	0
T193	0	71	0	0
T194	0	5	0	0
T195	0	37	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1501	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	65	0	0
T4	103150	0	0	0
T5	7271	8	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T68	0	98	0	0
T74	0	13	0	0
T76	0	7	0	0
T88	0	51	0	0
T192	0	42	0	0
T193	0	44	0	0
T194	0	4	0	0
T195	0	29	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1658	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	14	0	0
T4	103150	0	0	0
T5	7271	1	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T68	0	116	0	0
T74	0	5	0	0
T75	0	4	0	0
T88	0	109	0	0
T192	0	18	0	0
T193	0	86	0	0
T194	0	1	0	0
T195	0	32	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1697	0	0
T3	101750	76	0	0
T4	103150	0	0	0
T9	2645	0	0	0
T27	8034	0	0	0
T28	15603	0	0	0
T29	8386	0	0	0
T31	6333	0	0	0
T35	35866	0	0	0
T38	0	12	0	0
T40	22300	0	0	0
T68	0	112	0	0
T70	0	1	0	0
T74	0	16	0	0
T75	0	4	0	0
T76	0	8	0	0
T84	4570	0	0	0
T192	0	42	0	0
T193	0	88	0	0
T194	0	2	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1618	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	45	0	0
T4	103150	0	0	0
T5	7271	2	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	6	0	0
T68	0	89	0	0
T70	0	6	0	0
T74	0	6	0	0
T76	0	14	0	0
T192	0	34	0	0
T193	0	78	0	0
T195	0	74	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1739	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	44	0	0
T4	103150	0	0	0
T5	7271	6	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	5	0	0
T68	0	107	0	0
T70	0	3	0	0
T74	0	12	0	0
T76	0	4	0	0
T192	0	73	0	0
T193	0	107	0	0
T194	0	3	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1131	0	0
T3	101750	31	0	0
T4	103150	0	0	0
T9	2645	0	0	0
T27	8034	0	0	0
T28	15603	0	0	0
T29	8386	0	0	0
T31	6333	0	0	0
T35	35866	0	0	0
T38	0	8	0	0
T40	22300	0	0	0
T68	0	51	0	0
T70	0	7	0	0
T74	0	4	0	0
T76	0	4	0	0
T84	4570	0	0	0
T192	0	42	0	0
T193	0	62	0	0
T194	0	7	0	0
T195	0	33	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1205	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	24	0	0
T4	103150	0	0	0
T5	7271	9	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	4	0	0
T68	0	40	0	0
T70	0	3	0	0
T74	0	7	0	0
T76	0	5	0	0
T192	0	70	0	0
T193	0	44	0	0
T194	0	1	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1214	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	76	0	0
T4	103150	0	0	0
T5	7271	19	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	13	0	0
T68	0	28	0	0
T70	0	2	0	0
T74	0	4	0	0
T75	0	3	0	0
T192	0	35	0	0
T193	0	33	0	0
T194	0	7	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1201	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	67	0	0
T4	103150	0	0	0
T5	7271	5	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T38	0	1	0	0
T68	0	33	0	0
T70	0	4	0	0
T74	0	5	0	0
T76	0	3	0	0
T192	0	66	0	0
T193	0	42	0	0
T195	0	23	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1447	0	0
T3	101750	35	0	0
T4	103150	0	0	0
T9	2645	0	0	0
T27	8034	0	0	0
T28	15603	0	0	0
T29	8386	0	0	0
T31	6333	0	0	0
T35	35866	0	0	0
T38	0	3	0	0
T40	22300	0	0	0
T68	0	63	0	0
T70	0	1	0	0
T74	0	8	0	0
T76	0	8	0	0
T84	4570	0	0	0
T192	0	35	0	0
T193	0	81	0	0
T194	0	2	0	0
T195	0	42	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1032	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	40	0	0
T4	103150	0	0	0
T5	7271	22	0	0
T6	5509	0	0	0
T7	17652	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T68	0	37	0	0
T70	0	1	0	0
T74	0	8	0	0
T76	0	2	0	0
T192	0	38	0	0
T193	0	34	0	0
T194	0	3	0	0
T195	0	28	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1034	0	0
T3	101750	27	0	0
T4	103150	0	0	0
T9	2645	0	0	0
T27	8034	0	0	0
T28	15603	0	0	0
T29	8386	0	0	0
T31	6333	0	0	0
T35	35866	0	0	0
T38	0	1	0	0
T40	22300	0	0	0
T68	0	39	0	0
T70	0	1	0	0
T74	0	8	0	0
T76	0	9	0	0
T84	4570	0	0	0
T192	0	19	0	0
T193	0	31	0	0
T194	0	1	0	0
T195	0	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1596	0	0
T1	896985	0	0	0
T2	59550	0	0	0
T3	101750	30	0	0
T4	103150	0	0	0
T7	17652	11	0	0
T9	2645	0	0	0
T25	33049	0	0	0
T26	12547	0	0	0
T27	8034	0	0	0
T28	15603	0	0	0
T29	0	5	0	0
T40	0	21	0	0
T68	0	43	0	0
T70	0	4	0	0
T84	0	6	0	0
T192	0	44	0	0
T197	0	8	0	0
T198	0	5	0	0