9601d3bbdd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 16.620s | 5.946ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 3.620s | 1.230ms | 5 | 5 | 100.00 |
| V1 | csr_rw | adc_ctrl_csr_rw | 2.170s | 569.482us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 1.179m | 53.004ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 3.470s | 1.002ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 2.280s | 526.988us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 2.170s | 569.482us | 20 | 20 | 100.00 |
| adc_ctrl_csr_aliasing | 3.470s | 1.002ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 104 | 105 | 99.05 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 20.362m | 499.168ms | 50 | 50 | 100.00 |
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 19.681m | 493.654ms | 49 | 50 | 98.00 |
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 19.229m | 495.056ms | 50 | 50 | 100.00 |
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 19.893m | 494.236ms | 49 | 50 | 98.00 |
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 19.604m | 525.550ms | 50 | 50 | 100.00 |
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 20.686m | 497.790ms | 50 | 50 | 100.00 |
| V2 | filters_both | adc_ctrl_filters_both | 19.888m | 499.716ms | 50 | 50 | 100.00 |
| V2 | clock_gating | adc_ctrl_clock_gating | 18.260m | 499.738ms | 50 | 50 | 100.00 |
| V2 | poweron_counter | adc_ctrl_poweron_counter | 13.420s | 5.026ms | 50 | 50 | 100.00 |
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 1.770m | 46.477ms | 50 | 50 | 100.00 |
| V2 | fsm_reset | adc_ctrl_fsm_reset | 11.193m | 135.237ms | 48 | 50 | 96.00 |
| V2 | stress_all | adc_ctrl_stress_all | 42.268m | 676.594ms | 44 | 50 | 88.00 |
| V2 | alert_test | adc_ctrl_alert_test | 1.780s | 509.059us | 50 | 50 | 100.00 |
| V2 | intr_test | adc_ctrl_intr_test | 1.910s | 523.582us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 3.170s | 316.471us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 3.170s | 316.471us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 3.620s | 1.230ms | 5 | 5 | 100.00 |
| adc_ctrl_csr_rw | 2.170s | 569.482us | 20 | 20 | 100.00 | ||
| adc_ctrl_csr_aliasing | 3.470s | 1.002ms | 5 | 5 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 19.320s | 3.888ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 3.620s | 1.230ms | 5 | 5 | 100.00 |
| adc_ctrl_csr_rw | 2.170s | 569.482us | 20 | 20 | 100.00 | ||
| adc_ctrl_csr_aliasing | 3.470s | 1.002ms | 5 | 5 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 19.320s | 3.888ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 730 | 740 | 98.65 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 9.960s | 7.523ms | 5 | 5 | 100.00 |
| adc_ctrl_tl_intg_err | 25.610s | 8.970ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 25.610s | 8.970ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 13.502m | 635.856ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 909 | 920 | 98.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 16 | 16 | 12 | 75.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.53 | 98.98 | 95.70 | 100.00 | 100.00 | 98.18 | 98.64 | 91.24 |
UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 6 failures:
1.adc_ctrl_stress_all.95903151062494605947139241099902908991221184909548456763166132025962808063157
Line 552, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 404456578590 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 404456578590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.adc_ctrl_stress_all.79344356299589113873042571458620818601750659489862908335059158968743913124185
Line 387, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 408654198534 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 408654198534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:
Test adc_ctrl_filters_interrupt_fixed has 1 failures.
0.adc_ctrl_filters_interrupt_fixed.63246054019891055498986056662385680946220988007586413911692859604504896721511
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest/run.log
[make]: simulate
cd /workspace/0.adc_ctrl_filters_interrupt_fixed/latest && /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818350183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.1818350183
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test adc_ctrl_fsm_reset has 2 failures.
0.adc_ctrl_fsm_reset.56682951009319619877413316221665079327194017463688651973241866184159983793278
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest/run.log
[make]: simulate
cd /workspace/0.adc_ctrl_fsm_reset/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828053118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3828053118
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.adc_ctrl_fsm_reset.85461992372636161775614117433975443661723819646814371802738925844278619297885
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest/run.log
[make]: simulate
cd /workspace/3.adc_ctrl_fsm_reset/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539359837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3539359837
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test adc_ctrl_filters_polled_fixed has 1 failures.
1.adc_ctrl_filters_polled_fixed.66848162230056660451849571583275328359687938265570479637233418734918293780805
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest/run.log
[make]: simulate
cd /workspace/1.adc_ctrl_filters_polled_fixed/latest && /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910662469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.3910662469
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test adc_ctrl_smoke has 1 failures.
4.adc_ctrl_smoke.39369103165775896317716489709085718165945611285422384986020248972016117578718
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest/run.log
[make]: simulate
cd /workspace/4.adc_ctrl_smoke/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076408798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2076408798
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:47 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255