Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6868	1			T13	10		T16	20		T37	20
testmodes[AdcCtrlTestmodeNormal]	5348	1			T13	9		T14	2		T15	2
testmodes[AdcCtrlTestmodeLowpower]	5628	1			T12	2		T14	1		T18	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3796	1			T13	5		T16	19		T37	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1669	1			T13	5		T22	15		T87	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1300	1			T22	22		T38	14		T90	18
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1687	1			T13	4		T22	15		T87	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2012	1			T13	4		T15	1		T17	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1300	1			T14	1		T21	1		T22	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1274	1			T22	22		T86	1		T38	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1327	1			T14	1		T22	16		T38	9
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2788	1			T12	1		T18	1		T19	14