| | | | | | | |
tb |
98.58 |
98.98 |
95.70 |
100.00 |
100.00 |
98.18 |
98.64 |
| dut |
98.58 |
98.98 |
95.70 |
100.00 |
100.00 |
98.18 |
98.64 |
| adc_ctrl_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
| u_adc_ctrl_core |
98.70 |
99.67 |
98.31 |
|
100.00 |
95.54 |
100.00 |
| u_adc_ctrl_fsm |
97.92 |
100.00 |
96.84 |
|
100.00 |
92.77 |
100.00 |
| u_adc_ctrl_fsm_sva |
100.00 |
|
|
|
|
|
100.00 |
| u_adc_ctrl_intr |
95.01 |
98.67 |
84.62 |
|
|
96.77 |
100.00 |
| i_adc_ctrl_intr_o |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_match_sync |
87.50 |
100.00 |
50.00 |
|
|
100.00 |
100.00 |
| gen_nrz_hs_protocol.ack_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_nrz_hs_protocol.req_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_oneshot_done_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_reg |
97.77 |
98.90 |
95.13 |
100.00 |
|
98.47 |
96.33 |
| subtree... |
|
|
|
|
|
|
|