Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21896

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3323

1

T12

10

T14

13

T15

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19994

1

T5

1

T28

1

T46

3

auto[1]

5225

1

T12

16

T14

5

T15

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	31	1			T211	7		T212	24		-	-
values[1]	670	1			T14	5		T18	42		T24	1
values[2]	2471	1			T17	10		T21	23		T85	3
values[3]	725	1			T15	11		T22	15		T33	2
values[4]	604	1			T23	1		T34	15		T90	21
values[5]	732	1			T12	10		T15	5		T23	1
values[6]	650	1			T14	15		T95	2		T39	1
values[7]	729	1			T14	13		T82	3		T85	16
values[8]	585	1			T82	15		T96	1		T97	10
values[9]	1067	1			T12	16		T20	9		T21	1
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	802	1			T14	5		T18	20		T24	1
values[1]	2535	1			T15	11		T17	10		T21	23
values[2]	666	1			T34	15		T125	4		T181	3
values[3]	612	1			T15	5		T23	1		T90	21
values[4]	842	1			T12	10		T23	1		T24	1
values[5]	626	1			T14	15		T82	3		T85	16
values[6]	597	1			T14	13		T89	16		T135	16
values[7]	572	1			T21	1		T82	16		T96	1
values[8]	839	1			T12	16		T22	17		T33	39
values[9]	141	1			T20	9		T213	4		T100	18
minimum	16987	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T24	1		T82	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T18	11		T141	6		T89	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T15	1		T17	2		T21	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T98	12		T214	5		T215	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T125	3		T181	3		T116	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T34	15		T216	9		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T218	4		T144	17		T219	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	1		T23	1		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T23	1		T24	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	10		T95	1		T34	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	8		T39	1		T220	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T82	1		T85	6		T86	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T89	16		T135	16		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	8		T124	16		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T21	1		T82	1		T132	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T82	1		T96	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	16		T33	6		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T22	7		T33	15		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T20	1		T213	3		T100	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T118	1		T222	3		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16838	1			T13	19		T16	20		T18	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T111	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	4		T115	13		T214	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T18	9		T141	5		T115	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T15	10		T17	8		T21	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T98	12		T214	5		T215	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T125	1		T116	13		T144	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T216	10		T217	1		T100	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T144	7		T219	7		T224	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	4		T90	10		T115	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T91	11		T93	10		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T34	11		T93	13		T226	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	7		T39	1		T220	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T82	2		T85	10		T86	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T126	2		T227	3		T105	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	5		T124	14		T228	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T92	12		T128	4		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T82	14		T97	9		T112	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T33	1		T124	12		T35	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T22	10		T33	17		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T20	8		T213	1		T100	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T222	5		T223	15		T229	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T28	1		T46	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T211	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T212	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	1		T18	10		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T18	11		T89	5		T135	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T17	2		T21	11		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T98	12		T141	6		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	1		T22	11		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T216	9		T214	5		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T218	4		T144	17		T219	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T23	1		T34	15		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T23	1		T24	1		T35	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	10		T15	1		T34	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	8		T95	1		T220	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T95	1		T39	1		T93	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	1		T135	16		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	8		T82	1		T85	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T132	2		T89	16		T92	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T82	1		T96	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	16		T20	1		T21	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T22	7		T33	15		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T212	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T14	4		T18	12		T115	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T18	9		T104	11		T230	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T17	8		T21	12		T85	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T98	12		T141	5		T115	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	10		T22	4		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T216	10		T214	5		T217	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T144	7		T219	7		T224	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T90	10		T181	2		T231	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T91	11		T232	14		T233	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	4		T34	11		T115	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	7		T220	10		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T93	13		T232	11		T234	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	1		T126	2		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	5		T82	2		T85	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T92	12		T230	1		T235	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T82	14		T97	9		T112	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T20	8		T33	1		T213	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T22	10		T33	17		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	5		T24	1		T82	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T18	10		T141	6		T89	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T15	11		T17	10		T21	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T98	13		T214	7		T215	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T125	2		T181	3		T116	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T34	1		T216	11		T217	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T218	1		T144	8		T219	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	5		T23	1		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T23	1		T24	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	1		T95	1		T34	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	8		T39	2		T220	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T82	3		T85	11		T86	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T89	1		T135	1		T126	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	6		T124	15		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T21	1		T82	1		T132	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T82	15		T96	1		T97	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	1		T33	2		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T22	11		T33	18		T34	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T20	9		T213	3		T100	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T118	1		T222	6		T223	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T111	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T89	2		T214	1		T120	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T18	10		T141	5		T89	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T21	10		T22	10		T131	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T98	11		T214	3		T215	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T125	2		T116	11		T144	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T34	14		T216	8		T100	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T218	3		T144	16		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T90	10		T181	2		T236	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T35	7		T91	12		T93	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	9		T34	9		T93	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	7		T220	11		T183	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T85	5		T86	6		T232	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T89	15		T135	15		T53	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	7		T124	15		T237	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T92	5		T238	2		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T112	4		T233	4		T239	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	15		T33	5		T124	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	6		T33	14		T90	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T213	1		T100	10		T240	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T222	2		T229	3		T241	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T18	9		T135	8		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T211	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T212	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T14	5		T18	13		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T18	10		T89	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T17	10		T21	13		T85	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T98	13		T141	6		T115	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	11		T22	5		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T216	11		T214	7		T217	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T218	1		T144	8		T219	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T23	1		T34	1		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T23	1		T24	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	1		T15	5		T34	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	8		T95	1		T220	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T95	1		T39	1		T93	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	2		T135	1		T126	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	6		T82	3		T85	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T132	2		T89	1		T92	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T82	15		T96	1		T97	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T12	1		T20	9		T21	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T22	11		T33	18		T34	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T211	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T212	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T18	9		T89	2		T135	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T18	10		T89	4		T135	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T21	10		T131	24		T242	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T98	11		T141	5		T91	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T22	10		T116	11		T121	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T216	8		T214	3		T100	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T218	3		T144	16		T219	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T34	14		T90	10		T181	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T35	7		T91	12		T232	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	9		T34	9		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	7		T220	11		T183	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T93	10		T232	4		T145	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T135	15		T116	10		T112	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	7		T85	5		T86	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T89	15		T92	5		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T112	4		T233	4		T239	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	15		T33	5		T213	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T22	6		T33	14		T90	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22101

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3118

1

T12

16

T14

20

T15

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19861

1

T5

1

T28

1

T46

3

auto[1]

5358

1

T14

28

T17

10

T18

42

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T23	1		-	-		-	-
values[0]	61	1			T243	24		T244	18		T245	1
values[1]	616	1			T82	15		T85	3		T96	1
values[2]	673	1			T34	21		T141	11		T213	4
values[3]	750	1			T12	16		T23	1		T24	1
values[4]	634	1			T15	5		T22	17		T24	1
values[5]	595	1			T15	11		T18	22		T82	1
values[6]	655	1			T14	13		T21	24		T22	15
values[7]	503	1			T14	15		T18	20		T85	16
values[8]	713	1			T12	10		T82	1		T33	32
values[9]	3063	1			T14	5		T17	10		T20	9
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	793	1			T82	15		T85	3		T96	1
values[1]	748	1			T34	21		T141	11		T115	10
values[2]	629	1			T12	16		T22	17		T23	1
values[3]	652	1			T15	5		T24	1		T82	1
values[4]	699	1			T14	13		T15	11		T21	1
values[5]	632	1			T18	22		T21	23		T22	15
values[6]	2407	1			T14	15		T17	10		T18	20
values[7]	632	1			T12	10		T82	1		T33	32
values[8]	867	1			T23	1		T132	2		T90	21
values[9]	203	1			T14	5		T20	9		T82	3
minimum	16957	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T85	1		T89	3		T35	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T82	1		T96	1		T97	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T34	10		T91	13		T116	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T141	6		T115	1		T216	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T22	7		T23	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	16		T124	14		T93	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	1		T24	1		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T82	1		T89	16		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	8		T35	10		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	1		T21	1		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T21	11		T85	6		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T18	10		T22	11		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T17	2		T18	11		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	8		T134	1		T100	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	10		T82	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T33	15		T221	1		T181	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T132	2		T90	11		T91	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T23	1		T39	1		T183	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T34	15		T132	1		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T14	1		T20	1		T82	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16821	1			T13	19		T16	20		T19	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T85	2		T35	1		T215	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T82	14		T97	9		T98	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T34	11		T91	11		T116	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T141	5		T115	9		T216	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	10		T33	1		T90	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T124	12		T93	13		T103	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	4		T232	14		T104	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T126	10		T214	5		T217	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	5		T35	9		T246	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	10		T115	13		T92	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T21	12		T85	10		T124	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T18	12		T22	4		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T17	8		T18	9		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	7		T100	17		T122	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T220	10		T116	1		T128	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T33	17		T181	2		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T90	10		T91	3		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T39	1		T183	11		T232	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T247	12		T248	9		T249	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T14	4		T20	8		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T23	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T244	14		T245	1		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T243	10		T251	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T85	1		T89	3		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T82	1		T96	1		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	10		T91	13		T116	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T141	6		T213	3		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T23	1		T24	1		T33	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	16		T93	11		T110	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	1		T22	7		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T89	16		T135	6		T124	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T246	1		T214	4		T232	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	1		T18	10		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	8		T21	11		T124	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T21	1		T22	11		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T18	11		T85	6		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T14	8		T35	8		T238	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	10		T82	1		T220	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T33	15		T120	10		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T17	2		T34	15		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T14	1		T20	1		T82	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T244	4		T252	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T243	14		T251	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T85	2		T35	1		T215	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T82	14		T97	9		T98	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T34	11		T91	11		T116	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T141	5		T213	1		T115	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T33	1		T90	10		T116	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T93	13		T103	8		T107	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	4		T22	10		T253	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T124	12		T126	10		T100	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T246	9		T214	2		T232	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	10		T18	12		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	5		T21	12		T124	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T22	4		T115	13		T126	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T18	9		T85	10		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	7		T100	17		T254	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T220	10		T91	3		T128	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T33	17		T122	1		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1093	1			T17	8		T142	11		T99	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T14	4		T20	8		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3