Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21835

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3384

1

T12

26

T15

11

T18

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19693

1

T5

1

T28

1

T46

3

auto[1]

5526

1

T12

16

T14

28

T17

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	355	1			T18	20		T21	23		T23	1
values[0]	31	1			T107	14		T315	7		T321	10
values[1]	729	1			T14	5		T34	21		T141	11
values[2]	365	1			T15	11		T82	1		T95	1
values[3]	520	1			T24	1		T85	3		T96	1
values[4]	797	1			T213	4		T135	6		T247	13
values[5]	623	1			T12	26		T14	15		T15	5
values[6]	669	1			T20	9		T22	17		T33	2
values[7]	619	1			T23	1		T24	1		T115	10
values[8]	2643	1			T14	13		T17	10		T18	22
values[9]	913	1			T82	3		T34	2		T132	1
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	717	1			T141	11		T132	1		T89	5
values[1]	420	1			T15	11		T82	1		T85	3
values[2]	586	1			T24	1		T247	13		T221	1
values[3]	679	1			T14	15		T132	1		T213	4
values[4]	645	1			T12	10		T15	5		T22	17
values[5]	682	1			T12	16		T20	9		T23	1
values[6]	2559	1			T14	13		T17	10		T18	22
values[7]	637	1			T21	1		T82	4		T97	10
values[8]	1054	1			T18	20		T21	23		T85	16
values[9]	147	1			T23	1		T39	2		T175	1
minimum	17093	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T141	6		T132	1		T90	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T89	5		T135	9		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	15		T86	11		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T15	1		T82	1		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T24	1		T247	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T91	13		T112	5		T232	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	8		T132	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T213	3		T135	6		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	1		T22	7		T82	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	10		T33	21		T98	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T91	5		T116	11		T100	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	16		T20	1		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T14	8		T17	2		T22	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T18	10		T95	1		T93	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T82	1		T221	1		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	1		T82	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T18	11		T85	6		T260	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T21	11		T34	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T39	1		T175	1		T93	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T23	1		T226	10		T322	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16852	1			T13	19		T14	1		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T34	10		T89	3		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T141	5		T90	10		T124	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T92	12		T323	4		T324	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T86	5		T35	1		T264	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T15	10		T85	2		T112	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T247	12		T121	14		T233	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T91	11		T112	8		T232	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	7		T246	9		T103	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T213	1		T115	13		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	4		T22	10		T82	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	18		T98	12		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T91	3		T116	13		T100	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T20	8		T115	13		T100	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T14	5		T17	8		T22	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	12		T93	10		T215	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T128	4		T232	11		T121	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T82	2		T97	9		T126	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T18	9		T85	10		T116	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T21	12		T34	1		T220	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T39	1		T93	13		T235	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T226	2		T270	7		T283	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T34	11		T227	3		T107	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T18	11		T85	6		T93	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T21	11		T23	1		T220	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T321	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T107	1		T315	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T14	1		T141	6		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T34	10		T89	8		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T86	11		T214	4		T120	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T15	1		T82	1		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T24	1		T34	15		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T85	1		T96	1		T91	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T247	1		T246	1		T238	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T213	3		T135	6		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T14	8		T15	1		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	26		T33	21		T98	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T22	7		T33	1		T91	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T20	1		T90	11		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T115	1		T183	10		T93	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T23	1		T24	1		T100	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T14	8		T17	2		T22	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T18	10		T21	1		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T39	1		T260	2		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T82	1		T34	1		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T18	9		T85	10		T93	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T21	12		T220	10		T226	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T107	13		T315	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	4		T141	5		T90	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T34	11		T92	12		T227	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T86	5		T214	2		T280	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T15	10		T232	14		T171	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T35	1		T121	14		T233	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T85	2		T91	11		T112	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T247	12		T246	9		T103	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T213	1		T112	8		T227	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	7		T15	4		T82	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T33	18		T98	12		T35	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T22	10		T33	1		T91	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T20	8		T90	10		T115	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T115	9		T183	11		T93	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T100	17		T107	14		T243	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T14	5		T17	8		T22	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T18	12		T97	9		T93	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T39	1		T104	11		T261	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T82	2		T34	1		T124	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T141	6		T132	1		T90	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T89	1		T135	1		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T34	1		T86	10		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	11		T82	1		T85	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T24	1		T247	13		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T91	12		T112	9		T232	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	8		T132	1		T246	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T213	3		T135	1		T115	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	5		T22	11		T82	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T33	20		T98	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T91	4		T116	14		T100	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T20	9		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T14	6		T17	10		T22	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T18	13		T95	1		T93	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T82	1		T221	1		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T21	1		T82	3		T97	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T18	10		T85	11		T260	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T21	13		T34	2		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T39	2		T175	1		T93	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T23	1		T226	10		T322	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16971	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T34	12		T89	1		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T141	5		T90	10		T135	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T89	4		T135	8		T92	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	14		T86	6		T120	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T112	6		T232	15		T171	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T121	13		T233	12		T244	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T91	12		T112	4		T232	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	7		T238	2		T271	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T213	1		T135	5		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T22	6		T214	3		T119	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	9		T33	19		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T91	4		T116	10		T100	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	15		T100	11		T257	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	906	1			T14	7		T22	10		T131	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T18	9		T93	11		T215	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T232	4		T121	9		T211	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T116	11		T120	9		T101	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T18	10		T85	5		T116	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T21	10		T220	11		T124	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T93	10		T325	5		T326	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T226	2		T322	9		T270	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T163	9		T299	7		T321	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T34	9		T89	2		T255	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T18	10		T85	11		T93	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T21	13		T23	1		T220	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T321	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T107	14		T315	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T14	5		T141	6		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	12		T89	2		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T86	10		T214	5		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T15	11		T82	1		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T24	1		T34	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T85	3		T96	1		T91	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T247	13		T246	10		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T213	3		T135	1		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	8		T15	5		T82	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	2		T33	20		T98	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T22	11		T33	2		T91	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T20	9		T90	11		T115	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T115	10		T183	12		T93	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T23	1		T24	1		T100	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T14	6		T17	10		T22	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T18	13		T21	1		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T39	2		T260	2		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T82	3		T34	2		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T18	10		T85	5		T93	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T21	10		T220	11		T226	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T321	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T141	5		T90	10		T135	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T34	9		T89	6		T92	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T86	6		T214	1		T120	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T135	8		T232	15		T171	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	14		T121	13		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T91	12		T112	6		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T238	2		T271	10		T103	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T213	1		T135	5		T112	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T14	7		T214	3		T119	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	24		T33	19		T98	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	6		T91	4		T116	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T90	10		T257	2		T237	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T183	9		T93	6		T216	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T100	11		T123	6		T243	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T14	7		T22	10		T131	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T18	9		T93	11		T116	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T211	6		T255	1		T54	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T124	15		T181	2		T100	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19