Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21833

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3386

1

T12

26

T15

11

T18

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19636

1

T5

1

T28

1

T46

3

auto[1]

5583

1

T12

16

T14

28

T17

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	64	1			T116	3		T230	14		T322	10
values[0]	97	1			T34	21		T107	14		T327	1
values[1]	654	1			T14	5		T141	11		T132	1
values[2]	385	1			T15	11		T82	1		T86	16
values[3]	508	1			T24	1		T85	3		T95	1
values[4]	802	1			T89	16		T213	4		T135	6
values[5]	623	1			T12	10		T14	15		T15	5
values[6]	645	1			T12	16		T20	9		T22	17
values[7]	626	1			T23	1		T24	1		T115	10
values[8]	2638	1			T14	13		T17	10		T18	22
values[9]	1222	1			T18	20		T21	23		T23	1
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	809	1			T14	5		T34	21		T141	11
values[1]	474	1			T15	11		T82	1		T85	3
values[2]	605	1			T24	1		T213	4		T247	13
values[3]	611	1			T14	15		T132	1		T135	6
values[4]	650	1			T12	10		T15	5		T22	17
values[5]	699	1			T12	16		T20	9		T23	1
values[6]	2643	1			T14	13		T17	10		T18	22
values[7]	566	1			T21	1		T82	3		T97	10
values[8]	1021	1			T18	20		T21	23		T85	16
values[9]	172	1			T23	1		T39	2		T175	1
minimum	16969	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T14	1		T141	6		T90	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T34	10		T89	8		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T34	15		T86	11		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	1		T82	1		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T24	1		T247	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T213	3		T91	13		T232	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	8		T132	1		T135	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T246	1		T277	1		T110	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T15	1		T22	7		T82	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	10		T33	21		T98	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T91	5		T116	11		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	16		T20	1		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T14	8		T17	2		T22	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T18	10		T95	1		T93	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T260	1		T221	1		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T21	1		T82	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T18	11		T85	6		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T21	11		T34	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T39	1		T175	1		T93	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T23	1		T218	4		T322	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T107	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	4		T141	5		T90	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T34	11		T92	12		T227	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T86	5		T233	5		T244	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T15	10		T85	2		T112	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T247	12		T35	1		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T213	1		T91	11		T232	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T14	7		T105	7		T292	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T246	9		T112	8		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	4		T22	10		T82	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	18		T98	12		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T91	3		T116	13		T144	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	8		T115	13		T126	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T14	5		T17	8		T22	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T18	12		T93	10		T215	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T128	4		T232	11		T121	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T82	2		T97	9		T116	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T18	9		T85	10		T116	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T21	12		T34	1		T220	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T39	1		T93	13		T267	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T270	7		T328	1		T283	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T107	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T116	2		T329	1		T330	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T230	8		T322	10		T157	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T331	18		T278	1		T332	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T34	10		T107	1		T327	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	1		T141	6		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T89	8		T39	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T86	11		T214	4		T120	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T15	1		T82	1		T135	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T24	1		T34	15		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T85	1		T95	1		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T135	6		T247	1		T238	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T89	16		T213	3		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T14	8		T15	1		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	10		T33	21		T98	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T22	7		T33	1		T91	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	16		T20	1		T90	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T115	1		T183	10		T93	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T23	1		T24	1		T100	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T14	8		T17	2		T22	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T18	10		T21	1		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T18	11		T85	6		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T21	11		T23	1		T82	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T116	1		T329	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T230	6		T157	2		T333	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T331	17		T332	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T34	11		T107	13		T334	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	4		T141	5		T90	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T92	12		T227	3		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T86	5		T214	2		T280	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T15	10		T232	14		T171	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T35	1		T121	14		T233	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T85	2		T91	11		T112	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T247	12		T103	8		T206	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T213	1		T246	9		T112	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	7		T15	4		T82	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T33	18		T98	12		T35	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T22	10		T33	1		T91	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T20	8		T90	10		T115	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T115	9		T183	11		T93	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T100	17		T107	19		T243	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T14	5		T17	8		T22	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T18	12		T97	9		T93	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T18	9		T85	10		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T21	12		T82	2		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T14	5		T141	6		T90	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T34	12		T89	2		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T34	1		T86	10		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T15	11		T82	1		T85	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T24	1		T247	13		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T213	3		T91	12		T232	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	8		T132	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T246	10		T277	1		T110	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	5		T22	11		T82	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T33	20		T98	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T91	4		T116	14		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	1		T20	9		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T14	6		T17	10		T22	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T18	13		T95	1		T93	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T260	1		T221	1		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T21	1		T82	3		T97	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T18	10		T85	11		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T21	13		T34	2		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T39	2		T175	1		T93	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T23	1		T218	1		T322	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T107	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T141	5		T90	10		T135	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T34	9		T89	6		T135	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T34	14		T86	6		T120	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T112	6		T232	15		T171	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T121	13		T103	7		T231	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T213	1		T91	12		T232	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T14	7		T135	5		T238	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T112	4		T239	7		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T22	6		T214	3		T224	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	9		T33	19		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T91	4		T116	10		T102	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	15		T100	19		T257	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T14	7		T22	10		T131	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T18	9		T93	11		T215	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T232	4		T121	9		T211	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T116	11		T120	12		T101	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T18	10		T85	5		T116	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T21	10		T220	11		T124	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T93	10		T325	5		T294	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T218	3		T322	9		T270	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T116	2		T329	11		T330	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T230	7		T322	1		T157	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T331	18		T278	1		T332	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T34	12		T107	14		T327	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	5		T141	6		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T89	2		T39	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T86	10		T214	5		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T15	11		T82	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T24	1		T34	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T85	3		T95	1		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T135	1		T247	13		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T89	1		T213	3		T246	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	8		T15	5		T82	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	1		T33	20		T98	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T22	11		T33	2		T91	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T20	9		T90	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T115	10		T183	12		T93	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T23	1		T24	1		T100	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T14	6		T17	10		T22	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T18	13		T21	1		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T18	10		T85	11		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T21	13		T23	1		T82	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T116	1		T330	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T230	7		T322	9		T157	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T331	17		T332	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T34	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T141	5		T90	10		T135	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T89	6		T92	5		T255	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T86	6		T214	1		T120	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T135	8		T232	15		T171	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T34	14		T121	13		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T91	12		T112	6		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T135	5		T238	2		T271	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T89	15		T213	1		T112	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T14	7		T214	3		T119	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	9		T33	19		T98	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T22	6		T91	4		T116	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	15		T90	10		T100	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T183	9		T93	6		T216	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T100	11		T123	6		T243	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T14	7		T22	10		T131	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T18	9		T93	11		T116	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T18	10		T85	5		T93	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T21	10		T220	11		T124	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19