Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21851

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3368

1

T14

15

T20

9

T21

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19753

1

T5

1

T28

1

T46

3

auto[1]

5466

1

T12

16

T14

18

T17

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	577	1			T22	3		T38	9		T90	4
values[0]	58	1			T237	24		T251	30		T291	4
values[1]	565	1			T24	1		T33	32		T132	1
values[2]	2551	1			T17	10		T21	24		T82	2
values[3]	710	1			T33	7		T34	21		T132	1
values[4]	562	1			T12	16		T82	15		T90	21
values[5]	652	1			T20	9		T82	3		T33	2
values[6]	628	1			T23	1		T24	1		T89	16
values[7]	573	1			T14	18		T15	11		T18	20
values[8]	563	1			T22	17		T90	21		T135	6
values[9]	1204	1			T12	10		T14	15		T15	5
minimum	16576	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	474	1			T21	23		T24	1		T82	1
values[1]	2669	1			T17	10		T21	1		T82	1
values[2]	594	1			T12	16		T33	7		T34	21
values[3]	639	1			T20	9		T82	15		T90	21
values[4]	563	1			T82	3		T33	2		T98	24
values[5]	637	1			T14	5		T23	1		T24	1
values[6]	562	1			T14	13		T15	11		T18	20
values[7]	619	1			T14	15		T22	32		T95	1
values[8]	1087	1			T12	10		T15	5		T18	22
values[9]	112	1			T39	2		T91	8		T128	5
minimum	17263	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T21	11		T183	10		T94	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T24	1		T82	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T17	2		T82	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T21	1		T85	1		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	16		T33	6		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T34	10		T135	16		T260	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T82	1		T90	11		T35	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	1		T135	9		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T289	1		T257	3		T182	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T82	1		T33	1		T98	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T23	1		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T24	1		T86	11		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	8		T15	1		T18	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T135	6		T181	3		T226	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T22	7		T141	6		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	8		T22	11		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T12	10		T15	1		T18	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T23	1		T175	1		T116	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T91	5		T128	1		T110	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T39	1		T118	1		T335	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16877	1			T13	19		T16	20		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T237	13		T316	12		T320	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T21	12		T183	11		T215	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T214	7		T112	10		T107	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T17	8		T142	11		T99	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T85	2		T97	9		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T33	1		T213	1		T124	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T34	11		T116	1		T217	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T82	14		T90	10		T233	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	8		T247	12		T35	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T206	5		T234	14		T296	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T82	2		T33	1		T98	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	4		T34	1		T100	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T86	5		T107	14		T255	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	5		T15	10		T18	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T226	2		T116	13		T137	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T22	10		T141	5		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	7		T22	4		T90	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	4		T18	12		T126	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T116	13		T112	4		T232	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T91	3		T128	4		T225	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T39	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T237	11		T316	11		T269	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	418	1			T22	3		T38	9		T90	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T116	12		T118	1		T101	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T291	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T237	13		T251	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T33	15		T115	1		T183	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T24	1		T132	1		T89	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T17	2		T21	11		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T21	1		T82	1		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T33	6		T132	1		T213	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	10		T260	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	16		T82	1		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T135	25		T221	1		T35	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	8		T120	10		T257	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T20	1		T82	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T23	1		T89	16		T100	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T24	1		T125	3		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	9		T15	1		T18	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T86	11		T181	3		T116	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T22	7		T260	1		T115	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T90	11		T135	6		T253	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T12	10		T15	1		T18	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T14	8		T22	11		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16440	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T128	4		T112	8		T225	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T116	13		T232	11		T268	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T291	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T237	11		T251	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T33	17		T115	13		T183	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T214	2		T224	11		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T17	8		T21	12		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T85	2		T97	9		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T33	1		T213	1		T124	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T34	11		T126	10		T93	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T82	14		T90	10		T233	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T35	9		T116	1		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T224	14		T254	6		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	8		T82	2		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T100	8		T171	14		T268	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T125	1		T107	14		T255	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	9		T15	10		T18	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T86	5		T116	13		T137	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T22	10		T115	22		T92	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T90	10		T253	16		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T15	4		T18	12		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	7		T22	4		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T21	13		T183	12		T94	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T24	1		T82	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T17	10		T82	1		T142	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T21	1		T85	3		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T33	2		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	12		T135	1		T260	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T82	15		T90	11		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T20	9		T135	1		T247	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T289	1		T257	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T82	3		T33	2		T98	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	5		T23	1		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	1		T86	10		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	6		T15	11		T18	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T135	1		T181	3		T226	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T22	11		T141	6		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	8		T22	5		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T12	1		T15	5		T18	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T23	1		T175	1		T116	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T91	4		T128	5		T110	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T39	2		T118	1		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17060	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T237	12		T316	12		T320	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T21	10		T183	9		T215	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T89	2		T214	4		T112	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T131	24		T242	5		T124	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T34	14		T238	2		T93	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	15		T33	5		T213	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T34	9		T135	15		T116	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T90	10		T35	7		T120	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T135	8		T35	9		T93	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T257	2		T182	10		T306	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T98	11		T125	2		T119	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T89	15		T100	8		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T86	6		T255	2		T274	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	7		T18	10		T85	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T135	5		T226	2		T116	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T22	6		T141	5		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	7		T22	10		T90	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	9		T18	9		T89	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T116	11		T112	4		T101	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T91	4		T225	7		T231	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T335	12		T306	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T33	14		T105	7		T312	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T237	12		T316	11		T320	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	435	1			T22	3		T38	9		T90	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T116	14		T118	1		T101	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T291	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T237	12		T251	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T33	18		T115	14		T183	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T24	1		T132	1		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T17	10		T21	13		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T21	1		T82	1		T85	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T33	2		T132	1		T213	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T34	12		T260	1		T126	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T82	15		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T135	2		T221	1		T35	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T35	1		T120	1		T257	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T20	9		T82	3		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T23	1		T89	1		T100	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T24	1		T125	2		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	11		T15	11		T18	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T86	10		T181	3		T116	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T22	11		T260	1		T115	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T90	11		T135	1		T253	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T12	1		T15	5		T18	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T14	8		T22	5		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16576	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T112	4		T225	7		T231	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T116	11		T101	2		T232	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T237	12		T251	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T33	14		T183	9		T215	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T89	2		T214	1		T119	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T21	10		T131	24		T242	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T34	14		T214	3		T112	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T33	5		T213	1		T124	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	9		T238	2		T93	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	15		T90	10		T233	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T135	23		T35	9		T116	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T35	7		T120	9		T257	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T98	11		T93	11		T119	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T89	15		T100	8		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T125	2		T145	4		T255	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	7		T18	10		T85	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T86	6		T116	10		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T22	6		T92	5		T249	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T90	10		T135	5		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T12	9		T18	9		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T14	7		T22	10		T93	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19