Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22016

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3203

1

T18

42

T20

9

T21

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19848

1

T5

1

T28

1

T46

3

auto[1]

5371

1

T12

26

T14

15

T15

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T121	28		T145	7		T310	8
values[0]	69	1			T164	26		T301	2		T311	3
values[1]	430	1			T15	5		T21	23		T24	1
values[2]	603	1			T18	22		T82	19		T247	13
values[3]	701	1			T14	5		T15	11		T18	20
values[4]	720	1			T12	16		T85	3		T96	1
values[5]	2455	1			T12	10		T14	28		T17	10
values[6]	569	1			T82	1		T95	1		T33	32
values[7]	563	1			T24	1		T34	36		T134	1
values[8]	666	1			T34	2		T89	3		T39	1
values[9]	1444	1			T20	9		T21	1		T22	17
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	631	1			T15	5		T21	23		T24	1
values[1]	654	1			T18	42		T82	4		T141	11
values[2]	654	1			T14	5		T22	15		T96	1
values[3]	2571	1			T15	11		T17	10		T33	2
values[4]	573	1			T12	26		T14	28		T85	3
values[5]	597	1			T23	1		T82	1		T33	32
values[6]	619	1			T24	1		T95	1		T34	23
values[7]	733	1			T39	1		T183	21		T181	3
values[8]	831	1			T20	9		T21	1		T22	17
values[9]	359	1			T98	24		T91	24		T181	6
minimum	16997	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T21	11		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T132	1		T247	1		T35	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T82	1		T221	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T18	21		T82	1		T141	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	1		T22	11		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T96	1		T132	1		T90	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T15	1		T17	2		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T33	1		T135	6		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	26		T14	16		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T97	1		T246	1		T100	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T23	1		T89	5		T94	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T82	1		T33	15		T34	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T24	1		T95	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T34	11		T217	1		T120	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T226	10		T101	3		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	1		T183	10		T181	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T23	1		T86	11		T89	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	1		T21	1		T22	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T98	12		T91	13		T116	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T181	4		T271	11		T233	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16822	1			T13	19		T16	20		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T320	9		T164	13		T336	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	4		T21	12		T82	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T247	12		T126	2		T128	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T115	9		T91	3		T232	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T18	21		T82	2		T141	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	4		T22	4		T125	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T90	10		T214	5		T107	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T15	10		T17	8		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T33	1		T35	1		T116	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	12		T85	2		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T97	9		T246	9		T100	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T116	13		T217	1		T215	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T33	17		T90	10		T220	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	1		T93	6		T232	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T34	12		T105	7		T107	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T226	2		T137	10		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T183	11		T93	10		T253	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T86	5		T115	26		T104	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T20	8		T22	10		T85	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T98	12		T91	11		T116	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T181	2		T233	2		T227	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T164	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T121	14		T145	7		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T310	8		T250	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T301	1		T311	3		T337	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T164	13		T338	11		T337	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	1		T21	11		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T132	1		T35	8		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T82	2		T221	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T18	10		T82	1		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T15	1		T22	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T18	11		T141	6		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	16		T85	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T96	1		T135	16		T260	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T12	10		T14	16		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T33	1		T97	1		T135	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T95	1		T89	5		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T82	1		T33	15		T90	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T24	1		T134	1		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T34	25		T217	1		T225	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T226	10		T111	1		T232	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	1		T89	3		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T23	1		T98	12		T86	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T20	1		T21	1		T22	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T121	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T301	1		T337	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T164	13		T337	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T15	4		T21	12		T213	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T126	2		T128	4		T100	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T82	14		T115	9		T91	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T18	12		T82	2		T247	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	4		T15	10		T22	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T18	9		T141	5		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T85	2		T93	13		T121	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T35	1		T116	13		T100	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T14	12		T17	8		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T33	1		T97	9		T246	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T107	13		T219	7		T231	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T33	17		T90	10		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	1		T93	6		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T34	11		T225	8		T105	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T226	2		T232	9		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T34	1		T253	16		T214	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T98	12		T86	5		T115	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T20	8		T22	10		T85	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T15	5		T21	13		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T132	1		T247	13		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T82	1		T221	1		T115	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T18	23		T82	3		T141	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	5		T22	5		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T96	1		T132	1		T90	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T15	11		T17	10		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	2		T135	1		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	2		T14	14		T85	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T97	10		T246	10		T100	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T23	1		T89	1		T94	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T82	1		T33	18		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T24	1		T95	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T34	14		T217	1		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T226	10		T101	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T39	1		T183	12		T181	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T23	1		T86	10		T89	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T20	9		T21	1		T22	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T98	13		T91	12		T116	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T181	4		T271	1		T233	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16958	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T320	1		T164	14		T336	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T21	10		T213	1		T238	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T35	7		T100	10		T119	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T91	4		T183	9		T232	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	19		T141	5		T218	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T22	10		T125	2		T93	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T90	10		T135	15		T214	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	913	1			T131	24		T242	5		T124	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T135	5		T116	11		T225	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	24		T14	14		T33	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T100	11		T233	4		T171	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T89	4		T116	10		T215	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T33	14		T34	14		T90	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T93	6		T232	9		T53	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	9		T120	9		T105	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T226	2		T101	2		T182	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T183	9		T93	11		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T86	6		T89	15		T171	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T22	6		T85	5		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T98	11		T91	12		T116	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T181	2		T271	10		T233	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T249	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T320	8		T164	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T121	15		T145	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T310	1		T250	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T301	2		T311	1		T337	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T164	14		T338	1		T337	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	5		T21	13		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T132	1		T35	1		T126	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T82	16		T221	1		T115	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T18	13		T82	3		T247	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T14	5		T15	11		T22	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T18	10		T141	6		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T85	3		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T96	1		T135	1		T260	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T12	1		T14	14		T17	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T33	2		T97	10		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T95	1		T89	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T82	1		T33	18		T90	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T24	1		T134	1		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T34	13		T217	1		T225	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T226	10		T111	1		T232	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	2		T89	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T23	1		T98	13		T86	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	481	1			T20	9		T21	1		T22	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T121	13		T145	6		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T310	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T311	2		T337	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T164	12		T338	10		T337	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T21	10		T213	1		T238	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T35	7		T100	10		T119	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T91	4		T183	9		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T18	9		T218	3		T236	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T22	10		T125	2		T100	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T18	10		T141	5		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	15		T93	10		T121	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T135	15		T116	11		T100	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T12	9		T14	14		T33	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T135	5		T171	2		T255	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T89	4		T182	10		T219	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T33	14		T90	10		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T93	6		T116	10		T215	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	23		T225	7		T105	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T226	2		T232	9		T237	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T89	2		T214	1		T120	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T98	11		T86	6		T89	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T22	6		T85	5		T183	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19