Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21942

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3277

1

T18

42

T20

9

T21

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19793

1

T5

1

T28

1

T46

3

auto[1]

5426

1

T12

26

T14

15

T15

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	263	1			T20	9		T89	16		T115	14
values[0]	60	1			T164	26		T301	2		T338	11
values[1]	396	1			T15	5		T21	23		T24	1
values[2]	634	1			T18	42		T82	16		T247	13
values[3]	666	1			T14	5		T22	15		T82	3
values[4]	745	1			T12	16		T15	11		T33	7
values[5]	2451	1			T12	10		T14	28		T17	10
values[6]	607	1			T82	1		T33	32		T90	21
values[7]	553	1			T24	1		T95	1		T34	36
values[8]	686	1			T34	2		T89	3		T39	1
values[9]	1203	1			T21	1		T22	17		T23	1
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	481	1			T15	5		T82	15		T132	1
values[1]	632	1			T18	42		T82	1		T141	11
values[2]	669	1			T14	5		T22	15		T82	3
values[3]	2575	1			T12	16		T15	11		T17	10
values[4]	619	1			T12	10		T14	28		T23	1
values[5]	513	1			T82	1		T33	32		T34	15
values[6]	647	1			T24	1		T95	1		T34	23
values[7]	642	1			T39	1		T183	21		T181	3
values[8]	1106	1			T20	9		T21	1		T22	17
values[9]	192	1			T98	24		T181	6		T116	3
minimum	17143	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	1		T82	1		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T247	1		T126	1		T230	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T82	1		T221	1		T183	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T18	21		T141	6		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	1		T22	11		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T82	1		T96	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T12	16		T15	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T33	1		T135	6		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	10		T14	16		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T23	1		T85	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T94	1		T116	11		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T82	1		T33	15		T34	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T24	1		T95	1		T89	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T34	11		T120	10		T107	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T117	1		T118	1		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T39	1		T183	10		T181	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T23	1		T86	11		T89	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T20	1		T21	1		T22	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T98	12		T116	2		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T181	4		T271	11		T173	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16868	1			T13	19		T16	20		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T35	8		T126	1		T128	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T15	4		T82	14		T213	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T247	12		T126	10		T230	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T268	2		T236	12		T244	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T18	21		T141	5		T115	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	4		T22	4		T125	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T82	2		T90	10		T214	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T15	10		T17	8		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T33	1		T35	1		T116	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	12		T33	1		T124	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T85	2		T97	9		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T116	13		T217	1		T215	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T33	17		T220	10		T105	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	1		T93	6		T232	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	12		T107	19		T258	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T137	10		T237	11		T228	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T183	11		T93	10		T253	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T86	5		T115	26		T91	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T20	8		T22	10		T85	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T98	12		T116	1		T261	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T181	2		T276	9		T339	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T126	2		T128	4		T100	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T89	16		T115	1		T91	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T20	1		T271	11		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T301	1		T337	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T164	13		T338	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	1		T21	11		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T35	8		T126	2		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T82	2		T221	1		T183	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	21		T247	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	1		T22	11		T125	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T82	1		T141	6		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	16		T15	1		T33	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T96	1		T135	16		T260	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T12	10		T14	16		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T23	1		T85	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T94	1		T217	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T82	1		T33	15		T90	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T24	1		T95	1		T89	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	25		T107	1		T108	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T117	1		T118	1		T232	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T34	1		T89	3		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T23	1		T98	12		T86	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T21	1		T22	7		T85	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T115	13		T91	11		T116	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T20	8		T227	3		T267	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T301	1		T337	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T164	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T15	4		T21	12		T213	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T126	12		T128	4		T100	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T82	14		T216	10		T112	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T18	21		T247	12		T115	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	4		T22	4		T125	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T82	2		T141	5		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	10		T33	1		T93	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T35	1		T116	13		T225	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T14	12		T17	8		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T85	2		T33	1		T97	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T217	1		T107	13		T219	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T33	17		T90	10		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	1		T93	6		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T34	11		T107	19		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T232	9		T105	7		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T34	1		T253	16		T214	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T98	12		T86	5		T115	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T22	10		T85	10		T183	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T15	5		T82	15		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T247	13		T126	11		T230	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T82	1		T221	1		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T18	23		T141	6		T115	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	5		T22	5		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T82	3		T96	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T12	1		T15	11		T17	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T33	2		T135	1		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T14	14		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T23	1		T85	3		T97	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T94	1		T116	14		T217	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T82	1		T33	18		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T24	1		T95	1		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	14		T120	1		T107	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T117	1		T118	1		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T39	1		T183	12		T181	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T23	1		T86	10		T89	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T20	9		T21	1		T22	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T98	13		T116	2		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T181	4		T271	1		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17021	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T35	1		T126	3		T128	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T213	1		T238	2		T216	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T230	7		T224	12		T320	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T183	9		T282	2		T237	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T18	19		T141	5		T91	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T22	10		T125	2		T93	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T90	10		T135	15		T214	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T12	15		T131	24		T242	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	5		T116	11		T225	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	9		T14	14		T33	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T90	10		T100	11		T233	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T116	10		T215	1		T120	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	14		T34	14		T220	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T89	4		T93	6		T101	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T34	9		T120	9		T108	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T182	25		T237	12		T228	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T183	9		T93	11		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T86	6		T89	15		T91	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T22	6		T85	5		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T98	11		T116	1		T228	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T181	2		T271	10		T173	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T21	10		T103	7		T325	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T35	7		T100	10		T119	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T89	1		T115	14		T91	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T20	9		T271	1		T227	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T301	2		T337	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T164	14		T338	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T15	5		T21	13		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T35	1		T126	14		T128	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T82	16		T221	1		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T18	23		T247	13		T115	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	5		T22	5		T125	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T82	3		T141	6		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	1		T15	11		T33	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T96	1		T135	1		T260	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T12	1		T14	14		T17	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T23	1		T85	3		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T94	1		T217	2		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T82	1		T33	18		T90	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T24	1		T95	1		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T34	13		T107	20		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T117	1		T118	1		T232	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	2		T89	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T23	1		T98	13		T86	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	416	1			T21	1		T22	11		T85	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T89	15		T91	12		T116	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T271	10		T123	14		T173	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T337	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T164	12		T338	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T21	10		T213	1		T238	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T35	7		T100	10		T119	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T183	9		T216	8		T112	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T18	19		T91	4		T218	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	10		T125	2		T100	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T141	5		T90	10		T214	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	15		T33	5		T93	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T135	15		T116	11		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T12	9		T14	14		T131	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T135	5		T100	11		T171	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T182	10		T219	11		T340	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	14		T90	10		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T89	4		T93	6		T116	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T34	23		T108	9		T284	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T232	9		T105	7		T237	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T89	2		T214	1		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T98	11		T86	6		T102	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T22	6		T85	5		T183	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19