Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21897

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3322

1

T12

10

T14

13

T15

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19972

1

T5

1

T28

1

T46

3

auto[1]

5247

1

T12

16

T14

5

T15

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	208	1			T35	19		T100	18		T118	1
values[0]	38	1			T211	7		T340	5		T241	9
values[1]	715	1			T14	5		T18	42		T24	1
values[2]	2374	1			T17	10		T21	23		T85	3
values[3]	788	1			T15	11		T22	15		T33	2
values[4]	586	1			T23	1		T34	15		T90	21
values[5]	792	1			T12	10		T15	5		T24	1
values[6]	686	1			T14	15		T23	1		T95	2
values[7]	606	1			T14	13		T82	3		T85	16
values[8]	579	1			T21	1		T82	15		T96	1
values[9]	892	1			T12	16		T20	9		T22	17
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	610	1			T24	1		T82	1		T141	11
values[1]	2482	1			T15	11		T17	10		T21	23
values[2]	706	1			T22	15		T33	2		T34	15
values[3]	632	1			T23	1		T90	21		T260	1
values[4]	773	1			T12	10		T15	5		T24	1
values[5]	662	1			T14	15		T23	1		T82	3
values[6]	604	1			T14	13		T85	16		T89	16
values[7]	583	1			T21	1		T82	16		T96	1
values[8]	818	1			T12	16		T20	9		T22	17
values[9]	157	1			T33	32		T247	13		T100	18
minimum	17192	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T24	1		T82	1		T89	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T141	6		T89	5		T135	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T15	1		T17	2		T21	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T98	12		T214	5		T215	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T22	11		T33	1		T125	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T34	15		T216	9		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T218	4		T144	17		T219	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T23	1		T90	11		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T24	1		T95	1		T35	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	10		T15	1		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	8		T23	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T82	1		T86	11		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T89	16		T135	16		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	8		T85	6		T124	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T21	1		T82	1		T132	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T82	1		T96	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	16		T20	1		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T22	7		T34	1		T90	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T100	11		T240	7		T341	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T33	15		T247	1		T118	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16885	1			T13	19		T14	1		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T18	11		T111	1		T101	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T115	13		T225	3		T234	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T141	5		T115	9		T91	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T15	10		T17	8		T21	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T98	12		T214	5		T215	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T22	4		T33	1		T125	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T216	10		T217	1		T100	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T144	7		T219	7		T224	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T90	10		T115	13		T181	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T91	11		T93	10		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	4		T34	11		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	7		T39	1		T220	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T82	2		T86	5		T126	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T126	2		T227	3		T105	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	5		T85	10		T124	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T92	12		T128	4		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T82	14		T97	9		T112	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T20	8		T33	1		T213	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	10		T34	1		T90	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T100	7		T240	2		T342	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T33	17		T247	12		T222	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T18	9		T340	2		T301	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T35	10		T100	11		T289	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T118	1		T104	1		T107	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T211	7		T212	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T340	3		T241	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	1		T18	10		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T18	11		T89	5		T135	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T17	2		T21	11		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T98	12		T141	6		T91	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	1		T22	11		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T216	9		T214	5		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T218	4		T144	17		T219	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T23	1		T34	15		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T24	1		T35	8		T91	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	10		T15	1		T34	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	8		T23	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T95	1		T39	1		T93	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T39	1		T135	16		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	8		T82	1		T85	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T21	1		T132	2		T89	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T82	1		T96	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	16		T20	1		T82	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T22	7		T33	15		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T35	9		T100	7		T227	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T104	8		T107	13		T343	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T212	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T340	2		T241	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T14	4		T18	12		T115	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T18	9		T115	9		T104	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T17	8		T21	12		T85	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T98	12		T141	5		T91	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	10		T22	4		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T216	10		T214	5		T217	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T144	7		T219	7		T224	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T90	10		T181	2		T231	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T91	11		T232	14		T233	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	4		T34	11		T115	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	7		T220	10		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T93	13		T232	11		T234	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	1		T126	2		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	5		T82	2		T85	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T92	12		T128	4		T230	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T82	14		T97	9		T112	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T20	8		T33	1		T213	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T22	10		T33	17		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T24	1		T82	1		T89	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T141	6		T89	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T15	11		T17	10		T21	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T98	13		T214	7		T215	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T22	5		T33	2		T125	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T34	1		T216	11		T217	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T218	1		T144	8		T219	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T23	1		T90	11		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T24	1		T95	1		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T15	5		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	8		T23	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T82	3		T86	10		T126	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T89	1		T135	1		T126	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	6		T85	11		T124	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T21	1		T82	1		T132	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T82	15		T96	1		T97	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	1		T20	9		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T22	11		T34	2		T90	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T100	8		T240	7		T341	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T33	18		T247	13		T118	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17013	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T18	10		T111	1		T101	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T89	2		T120	9		T225	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	5		T89	4		T135	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T21	10		T131	24		T242	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T98	11		T214	3		T215	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T22	10		T125	2		T116	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	14		T216	8		T100	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T218	3		T144	16		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T90	10		T181	2		T236	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T35	7		T91	12		T93	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	9		T34	9		T93	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	7		T220	11		T183	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T86	6		T145	4		T123	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T89	15		T135	15		T53	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	7		T85	5		T124	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T92	5		T238	2		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T112	4		T233	4		T239	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	15		T33	5		T213	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	6		T90	10		T93	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T100	10		T240	2		T341	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T33	14		T222	2		T344	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T18	9		T135	8		T120	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T18	10		T101	2		T340	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T35	10		T100	8		T289	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T118	1		T104	9		T107	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T211	1		T212	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T340	3		T241	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T14	5		T18	13		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T18	10		T89	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T17	10		T21	13		T85	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T98	13		T141	6		T91	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T15	11		T22	5		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T216	11		T214	7		T217	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T218	1		T144	8		T219	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T23	1		T34	1		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T24	1		T35	1		T91	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T15	5		T34	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	8		T23	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T95	1		T39	1		T93	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	2		T135	1		T126	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	6		T82	3		T85	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T21	1		T132	2		T89	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T82	15		T96	1		T97	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	1		T20	9		T82	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T22	11		T33	18		T34	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T35	9		T100	10		T227	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T123	14		T345	12		T346	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T211	6		T212	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T340	2		T241	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T18	9		T89	2		T135	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T18	10		T89	4		T135	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T21	10		T131	24		T242	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T98	11		T141	5		T91	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T22	10		T125	2		T116	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T216	8		T214	3		T100	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T218	3		T144	16		T219	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T34	14		T90	10		T181	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T35	7		T91	12		T232	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	9		T34	9		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	7		T220	11		T183	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T93	10		T232	4		T145	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T135	15		T116	10		T271	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	7		T85	5		T86	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T89	15		T92	5		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T112	4		T233	4		T239	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	15		T33	5		T213	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T22	6		T33	14		T90	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19