Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T85	3		T89	1		T35	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T82	15		T96	1		T97	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T34	12		T91	12		T116	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	6		T115	10		T216	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T22	11		T23	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T124	13		T93	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	5		T24	1		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T82	1		T89	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	6		T35	10		T246	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	11		T21	1		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T21	13		T85	11		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T18	13		T22	5		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T17	10		T18	10		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	8		T134	1		T100	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T82	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T33	18		T221	1		T181	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T132	2		T90	11		T91	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T23	1		T39	2		T183	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T34	1		T132	1		T247	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T14	5		T20	9		T82	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16957	1			T5	1		T28	1		T46	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T89	2		T215	1		T112	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T98	11		T213	1		T183	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	9		T91	12		T116	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T141	5		T216	8		T225	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T22	6		T33	5		T90	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	15		T124	13		T93	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T232	15		T119	10		T224	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T89	15		T135	5		T214	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	7		T35	9		T214	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T92	5		T93	11		T112	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T21	10		T85	5		T135	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T18	9		T22	10		T35	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	887	1			T18	10		T131	24		T242	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T14	7		T100	11		T120	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	9		T135	15		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T33	14		T181	2		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T90	10		T91	4		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T183	9		T232	9		T255	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T34	14		T256	4		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T86	6		T89	4		T171	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T23	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T244	5		T245	1		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T243	15		T251	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T85	3		T89	1		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T82	15		T96	1		T97	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T34	12		T91	12		T116	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T141	6		T213	3		T115	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T23	1		T24	1		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T93	14		T110	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	5		T22	11		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T89	1		T135	1		T124	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T246	10		T214	5		T232	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	11		T18	13		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	6		T21	13		T124	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T21	1		T22	5		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T18	10		T85	11		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	8		T35	1		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T82	1		T220	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T33	18		T120	1		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T17	10		T34	1		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T14	5		T20	9		T82	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T244	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T243	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T89	2		T215	1		T112	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T98	11		T183	9		T93	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	9		T91	12		T116	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T141	5		T213	1		T216	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T33	5		T90	10		T116	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	15		T93	10		T103	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T22	6		T119	10		T257	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T89	15		T135	5		T124	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T214	1		T232	15		T258	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T18	9		T214	3		T112	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	7		T21	10		T124	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T22	10		T92	5		T93	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T18	10		T85	5		T135	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T14	7		T35	7		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	9		T220	11		T91	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T33	14		T120	9		T239	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T34	14		T131	24		T90	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T86	6		T89	4		T183	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19