Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21964

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3255

1

T12

26

T14

13

T15

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19878

1

T5

1

T28

1

T46

3

auto[1]

5341

1

T12

26

T14

20

T15

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	339	1			T18	22		T23	1		T95	1
values[1]	595	1			T12	26		T14	15		T86	16
values[2]	639	1			T22	15		T98	24		T89	3
values[3]	495	1			T82	1		T33	9		T96	1
values[4]	658	1			T22	17		T132	2		T135	9
values[5]	2572	1			T15	5		T17	10		T24	1
values[6]	634	1			T15	11		T82	4		T85	16
values[7]	683	1			T14	5		T24	1		T82	15
values[8]	584	1			T21	24		T95	1		T132	1
values[9]	1065	1			T14	13		T18	20		T20	9
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	633	1			T12	16		T98	24		T86	16
values[1]	519	1			T22	15		T82	1		T217	2
values[2]	503	1			T33	9		T96	1		T34	21
values[3]	2657	1			T17	10		T22	17		T24	1
values[4]	629	1			T15	5		T85	3		T39	1
values[5]	595	1			T15	11		T82	4		T85	16
values[6]	632	1			T14	5		T24	1		T82	15
values[7]	682	1			T21	24		T23	1		T95	1
values[8]	1096	1			T14	13		T18	42		T20	9
values[9]	119	1			T106	2		T53	16		T259	3
minimum	17154	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T260	1		T232	5		T144	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	16		T98	12		T86	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T22	11		T217	1		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T82	1		T120	4		T224	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T33	1		T34	10		T89	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T33	6		T96	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T17	2		T22	7		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T24	1		T132	1		T220	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T85	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T225	8		T261	1		T108	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T82	1		T33	15		T34	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T15	1		T82	1		T85	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T35	8		T91	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	1		T82	1		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T21	11		T23	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T21	1		T95	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T18	11		T23	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T14	8		T18	10		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T106	2		T53	9		T259	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T235	1		T262	3		T263	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16862	1			T13	19		T14	8		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T12	10		T39	1		T100	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T232	11		T144	7		T107	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T98	12		T86	5		T225	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	4		T217	1		T112	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T224	11		T243	14		T234	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T33	1		T34	11		T183	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T33	1		T35	1		T125	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T17	8		T22	10		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T220	10		T91	3		T233	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T15	4		T85	2		T253	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T225	8		T261	2		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T82	2		T33	17		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	10		T85	10		T115	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	4		T91	11		T227	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T82	14		T115	13		T116	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T21	12		T247	12		T121	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T126	2		T100	15		T264	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T18	9		T141	5		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T14	5		T18	12		T20	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T53	7		T259	1		T264	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T235	15		T262	2		T265	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T39	1		T100	17		T237	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T23	1		T95	1		T89	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T18	10		T97	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	8		T260	1		T232	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	26		T86	11		T89	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T22	11		T89	3		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T98	12		T266	1		T224	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T33	1		T34	10		T183	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T82	1		T33	6		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T22	7		T135	9		T93	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T132	2		T220	12		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T15	1		T17	2		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T24	1		T225	8		T261	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T82	1		T33	15		T34	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	1		T82	1		T85	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	1		T35	8		T91	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T24	1		T82	1		T115	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	11		T94	1		T102	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T21	1		T95	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T18	11		T23	1		T141	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T14	8		T20	1		T213	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T259	1		T267	2		T264	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T18	12		T97	9		T116	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	7		T232	11		T144	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T86	5		T39	1		T100	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	4		T217	1		T112	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T98	12		T224	11		T243	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T33	1		T34	11		T183	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T33	1		T35	1		T125	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T22	10		T93	10		T104	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T220	10		T91	3		T233	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T15	4		T17	8		T85	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T225	8		T261	2		T243	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T82	2		T33	17		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	10		T85	10		T92	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	4		T91	11		T268	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T82	14		T115	22		T126	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T21	12		T121	14		T227	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T126	2		T107	19		T269	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T18	9		T141	5		T247	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T14	5		T20	8		T213	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T260	1		T232	12		T144	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	1		T98	13		T86	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T22	5		T217	2		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T82	1		T120	1		T224	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T33	2		T34	12		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T33	2		T96	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T17	10		T22	11		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	1		T132	1		T220	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	5		T85	3		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T225	9		T261	3		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T82	3		T33	18		T34	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	11		T82	1		T85	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	5		T35	1		T91	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T24	1		T82	15		T115	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T21	13		T23	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T21	1		T95	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T18	10		T23	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T14	6		T18	13		T20	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T106	2		T53	8		T259	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T235	16		T262	3		T263	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17002	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T12	1		T39	2		T100	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T232	4		T144	16		T237	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	15		T98	11		T86	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T22	10		T112	4		T120	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T120	3		T224	12		T243	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T34	9		T89	2		T183	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T33	5		T125	2		T218	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T22	6		T131	24		T90	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T220	11		T91	4		T183	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T214	1		T215	1		T112	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T225	7		T108	9		T270	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T33	14		T34	14		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T85	5		T92	5		T144	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T35	7		T91	12		T236	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T116	1		T232	15		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T21	10		T135	15		T102	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T100	18		T271	10		T54	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T18	10		T141	5		T89	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T14	7		T18	9		T213	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T53	8		T264	9		T272	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T262	2		T263	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T14	7		T257	2		T273	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T12	9		T100	11		T237	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T23	1		T95	1		T89	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T18	13		T97	10		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	8		T260	1		T232	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	2		T86	10		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T22	5		T89	1		T217	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T98	13		T266	1		T224	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T33	2		T34	12		T183	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T82	1		T33	2		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T22	11		T135	1		T93	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T132	2		T220	11		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T15	5		T17	10		T85	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T24	1		T225	9		T261	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T82	3		T33	18		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T15	11		T82	1		T85	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	5		T35	1		T91	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T24	1		T82	15		T115	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T21	13		T94	1		T102	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	1		T95	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T18	10		T23	1		T141	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T14	6		T20	9		T213	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T89	4		T182	10		T264	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T18	9		T238	2		T116	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T14	7		T232	4		T257	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	24		T86	6		T89	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T22	10		T89	2		T112	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T98	11		T224	12		T243	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	9		T183	9		T93	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T33	5		T125	2		T120	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T22	6		T135	8		T93	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T220	11		T91	4		T183	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T131	24		T90	10		T242	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T225	7		T108	9		T182	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T33	14		T34	14		T90	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T85	5		T92	5		T255	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T35	7		T91	12		T236	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T116	1		T232	15		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T21	10		T102	2		T121	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T54	12		T182	10		T274	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T18	10		T141	5		T135	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	7		T213	1		T124	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19