Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22247

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

2972

1

T12

26

T14

5

T20

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19853

1

T5

1

T28

1

T46

3

auto[1]

5366

1

T12

10

T14

15

T15

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T275	1		T276	12		T146	11
values[0]	44	1			T82	15		T216	19		T263	9
values[1]	438	1			T23	1		T85	16		T33	7
values[2]	726	1			T12	16		T95	1		T96	1
values[3]	578	1			T12	10		T14	28		T21	1
values[4]	2593	1			T17	10		T24	1		T34	15
values[5]	752	1			T15	11		T91	8		T126	11
values[6]	539	1			T14	5		T20	9		T22	17
values[7]	600	1			T18	20		T95	1		T34	21
values[8]	817	1			T18	22		T24	1		T82	1
values[9]	1133	1			T15	5		T21	23		T23	1
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	601	1			T23	1		T82	15		T33	7
values[1]	705	1			T12	16		T21	1		T85	16
values[2]	686	1			T12	10		T14	28		T22	15
values[3]	2627	1			T17	10		T24	1		T34	15
values[4]	675	1			T14	5		T15	11		T175	1
values[5]	449	1			T20	9		T22	17		T34	21
values[6]	819	1			T18	42		T95	1		T260	1
values[7]	636	1			T24	1		T82	1		T90	21
values[8]	839	1			T15	5		T21	23		T23	1
values[9]	216	1			T85	3		T34	2		T124	26
minimum	16966	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T82	1		T33	6		T90	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T23	1		T246	1		T93	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T95	1		T89	16		T221	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	16		T21	1		T85	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	16		T22	11		T98	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	10		T82	2		T135	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T17	2		T24	1		T34	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T132	2		T277	1		T123	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	1		T175	1		T225	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	1		T91	5		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T22	7		T125	3		T110	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T20	1		T34	10		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T18	21		T95	1		T260	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T175	1		T116	12		T121	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T24	1		T82	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T90	11		T213	3		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	1		T97	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T21	11		T23	1		T33	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T85	1		T126	1		T120	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T34	1		T124	14		T183	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16820	1			T13	19		T16	20		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T82	14		T33	1		T90	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T246	9		T93	10		T279	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T214	5		T226	2		T128	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T85	10		T92	12		T233	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	12		T22	4		T98	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T82	2		T35	9		T214	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T17	8		T142	11		T99	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T224	7		T280	13		T269	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	10		T225	8		T103	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	4		T91	3		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T22	10		T125	1		T112	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T20	8		T34	11		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T18	21		T220	10		T124	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T116	13		T121	14		T171	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T115	13		T121	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T90	10		T213	1		T115	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	4		T97	9		T247	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	12		T33	18		T232	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T85	2		T126	2		T268	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T34	1		T124	12		T116	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T28	1		T46	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T275	1		T276	1		T146	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T82	1		T216	9		T263	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T250	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T33	6		T90	11		T266	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T23	1		T85	6		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T95	1		T89	16		T135	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	16		T96	1		T93	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	16		T22	11		T98	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	10		T21	1		T82	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T17	2		T24	1		T34	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T132	2		T135	16		T35	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	1		T225	8		T103	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T91	5		T126	1		T253	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T22	7		T125	3		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	1		T20	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T18	11		T95	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T34	10		T175	1		T116	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T18	10		T24	1		T82	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T213	3		T260	1		T93	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T15	1		T85	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T21	11		T23	1		T33	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T276	11		T281	9		T147	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T82	14		T216	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T33	1		T90	10		T254	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T85	10		T246	9		T279	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T214	5		T226	2		T128	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T93	10		T233	5		T219	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	12		T22	4		T98	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T82	2		T92	12		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T17	8		T86	5		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T35	9		T105	7		T224	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	10		T225	8		T103	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T91	3		T126	10		T253	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T22	10		T125	1		T112	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	4		T20	8		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T18	9		T220	10		T104	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	11		T116	13		T121	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T18	12		T124	14		T115	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T213	1		T93	13		T116	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T15	4		T85	2		T97	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T21	12		T33	18		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T82	15		T33	2		T90	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T23	1		T246	10		T93	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T95	1		T89	1		T221	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T21	1		T85	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T14	14		T22	5		T98	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T12	1		T82	4		T135	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T17	10		T24	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T132	2		T277	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	11		T175	1		T225	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	5		T91	4		T126	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	11		T125	2		T110	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T20	9		T34	12		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T18	23		T95	1		T260	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T175	1		T116	14		T121	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T24	1		T82	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T90	11		T213	3		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T15	5		T97	10		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T21	13		T23	1		T33	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T85	3		T126	3		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T34	2		T124	13		T183	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16965	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	5		T90	10		T135	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T93	11		T282	2		T283	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T89	15		T214	3		T226	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	15		T85	5		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	14		T22	10		T98	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	9		T135	23		T35	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T34	14		T131	24		T242	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T123	6		T224	6		T284	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T225	7		T103	7		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T91	4		T100	10		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T22	6		T125	2		T112	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T34	9		T35	7		T101	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T18	19		T220	11		T124	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T116	11		T121	13		T171	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T238	2		T120	9		T121	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T90	10		T213	1		T93	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T100	8		T112	4		T144	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T21	10		T33	14		T232	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T120	4		T218	3		T257	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T124	13		T183	9		T116	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T275	1		T276	12		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T82	15		T216	11		T263	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T250	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T33	2		T90	11		T266	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T23	1		T85	11		T246	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T95	1		T89	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	1		T96	1		T93	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	14		T22	5		T98	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	1		T21	1		T82	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T17	10		T24	1		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T132	2		T135	1		T35	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T15	11		T225	9		T103	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T91	4		T126	11		T253	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T22	11		T125	2		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	5		T20	9		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T18	10		T95	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T34	12		T175	1		T116	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T18	13		T24	1		T82	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T213	3		T260	1		T93	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T15	5		T85	3		T97	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T21	13		T23	1		T33	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T146	10		T281	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T216	8		T263	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T33	5		T90	10		T119	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T85	5		T282	2		T283	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T89	15		T135	5		T214	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	15		T93	11		T120	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	14		T22	10		T98	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	9		T89	2		T135	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T34	14		T86	6		T131	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T135	15		T35	9		T102	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T225	7		T103	7		T227	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T91	4		T225	12		T285	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T22	6		T125	2		T112	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T35	7		T100	10		T101	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T18	10		T220	11		T120	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T34	9		T116	11		T121	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T18	9		T124	15		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T213	1		T93	10		T116	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T100	8		T112	4		T120	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T21	10		T33	14		T90	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19