Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22022

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3197

1

T12

10

T14

33

T18

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19844

1

T5

1

T28

1

T46

3

auto[1]

5375

1

T14

13

T17

10

T18

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	398	1			T22	3		T38	9		T90	4
values[0]	104	1			T33	32		T119	9		T285	16
values[1]	554	1			T24	1		T132	1		T89	3
values[2]	2517	1			T17	10		T21	24		T82	2
values[3]	702	1			T33	7		T34	21		T132	1
values[4]	578	1			T12	16		T82	15		T90	21
values[5]	659	1			T20	9		T23	1		T82	3
values[6]	613	1			T24	1		T89	16		T125	4
values[7]	599	1			T14	18		T15	11		T18	20
values[8]	540	1			T22	17		T132	1		T135	6
values[9]	1379	1			T12	10		T14	15		T15	5
minimum	16576	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	753	1			T21	24		T24	1		T33	32
values[1]	2663	1			T17	10		T82	2		T85	3
values[2]	587	1			T12	16		T33	7		T34	21
values[3]	673	1			T20	9		T82	15		T90	21
values[4]	543	1			T82	3		T33	2		T98	24
values[5]	676	1			T23	1		T24	1		T34	2
values[6]	548	1			T14	18		T15	11		T18	20
values[7]	594	1			T14	15		T22	32		T95	1
values[8]	1011	1			T12	10		T15	5		T18	22
values[9]	194	1			T39	2		T91	8		T246	10
minimum	16977	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T21	11		T33	15		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	1		T24	1		T89	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T17	2		T82	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T82	1		T85	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	16		T132	1		T124	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	6		T34	10		T135	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T90	11		T247	1		T35	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T20	1		T82	1		T135	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	1		T125	3		T257	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T82	1		T98	12		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T23	1		T24	1		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T86	11		T89	16		T225	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	1		T18	11		T85	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	9		T135	6		T181	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T22	18		T95	1		T141	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	8		T221	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T15	1		T96	1		T89	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	10		T18	10		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T91	5		T246	1		T100	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T39	1		T118	1		T136	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16831	1			T13	19		T16	20		T19	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T21	12		T33	17		T183	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T115	13		T214	5		T112	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T17	8		T97	9		T142	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T85	2		T126	10		T181	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T124	12		T116	1		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T33	1		T34	11		T91	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T90	10		T247	12		T35	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T20	8		T82	14		T233	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T33	1		T125	1		T206	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T82	2		T98	12		T286	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	1		T100	8		T171	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T86	5		T225	3		T233	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	10		T18	9		T85	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	9		T226	2		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T22	14		T141	5		T90	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T14	7		T230	1		T227	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T15	4		T126	2		T216	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T18	12		T116	13		T232	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T91	3		T246	9		T100	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T39	1		T231	1		T269	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	1		T28	1		T46	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T22	3		T38	9		T90	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T33	15		T148	1		T287	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T119	9		T285	8		T288	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T132	1		T183	10		T214	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T24	1		T89	3		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T17	2		T21	11		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T21	1		T82	1		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T132	1		T213	3		T238	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	6		T34	10		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	16		T90	11		T124	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T82	1		T135	25		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T23	1		T33	1		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T20	1		T82	1		T98	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T24	1		T125	3		T100	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T89	16		T119	11		T289	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	1		T18	11		T85	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	9		T86	11		T181	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T22	7		T132	1		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T135	6		T221	1		T226	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T15	1		T22	11		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T12	10		T14	8		T18	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16440	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T290	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T279	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T33	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T285	8		T251	15		T291	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T183	11		T214	2		T215	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T115	13		T224	11		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T17	8		T21	12		T97	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T85	2		T181	2		T214	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T213	1		T93	13		T121	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	1		T34	11		T91	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T90	10		T124	12		T116	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T82	14		T122	1		T233	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T33	1		T247	12		T35	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T20	8		T82	2		T98	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T125	1		T100	8		T171	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T258	4		T292	9		T293	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	10		T18	9		T85	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	9		T86	5		T116	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T22	10		T115	22		T92	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T226	2		T230	1		T227	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T15	4		T22	4		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	7		T18	12		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T21	13		T33	18		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T21	1		T24	1		T89	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T17	10		T82	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T82	1		T85	3		T126	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T132	1		T124	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T33	2		T34	12		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T90	11		T247	13		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T20	9		T82	15		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T33	2		T125	2		T257	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T82	3		T98	13		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T23	1		T24	1		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T86	10		T89	1		T225	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	11		T18	10		T85	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	11		T135	1		T181	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T22	16		T95	1		T141	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	8		T221	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T15	5		T96	1		T89	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	1		T18	13		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T91	4		T246	10		T100	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T39	2		T118	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16967	1			T5	1		T28	1		T46	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T21	10		T33	14		T183	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T89	2		T214	3		T112	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T34	14		T131	24		T213	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T181	2		T103	7		T54	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	15		T124	13		T116	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T33	5		T34	9		T135	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T90	10		T35	16		T93	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T135	8		T233	4		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T125	2		T257	2		T145	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T98	11		T119	10		T286	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T100	8		T171	13		T294	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T86	6		T89	15		T225	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T18	10		T85	5		T183	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T14	7		T135	5		T226	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T22	16		T141	5		T90	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	7		T171	2		T282	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T89	4		T216	8		T112	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	9		T18	9		T116	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T91	4		T100	10		T225	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T136	11		T162	14		T231	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T287	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	388	1			T22	3		T38	9		T90	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T279	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T33	18		T148	1		T287	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T119	1		T285	9		T288	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T132	1		T183	12		T214	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	1		T89	1		T115	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T17	10		T21	13		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T21	1		T82	1		T85	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T132	1		T213	3		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T33	2		T34	12		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T90	11		T124	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T82	15		T135	2		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T23	1		T33	2		T247	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T20	9		T82	3		T98	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T24	1		T125	2		T100	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T89	1		T119	1		T289	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	11		T18	10		T85	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	11		T86	10		T181	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T22	11		T132	1		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T135	1		T221	1		T226	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	388	1			T15	5		T22	5		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T12	1		T14	8		T18	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16576	1			T5	1		T28	1		T46	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T33	14		T287	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T119	8		T285	7		T251	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T183	9		T214	1		T215	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T89	2		T182	15		T224	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T21	10		T34	14		T131	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T181	2		T214	3		T112	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T213	1		T238	2		T93	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	5		T34	9		T91	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	15		T90	10		T124	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T135	23		T233	4		T144	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T35	16		T93	11		T120	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T98	11		T233	12		T255	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T125	2		T100	8		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T89	15		T119	10		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T18	10		T85	5		T90	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T14	7		T86	6		T116	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T22	6		T92	5		T271	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T135	5		T226	2		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T22	10		T141	5		T89	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T12	9		T14	7		T18	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19