Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22125

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3094

1

T12

16

T14

20

T15

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19844

1

T5

1

T28

1

T46

3

auto[1]

5375

1

T14

28

T17

10

T18

42

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	251	1			T23	1		T247	13		T183	21
values[0]	2	1			T245	1		T250	1		-	-
values[1]	648	1			T82	15		T85	3		T96	1
values[2]	698	1			T34	21		T141	11		T115	10
values[3]	665	1			T12	16		T23	1		T24	1
values[4]	775	1			T15	5		T22	17		T24	1
values[5]	492	1			T15	11		T82	1		T95	1
values[6]	673	1			T14	13		T18	22		T21	24
values[7]	524	1			T14	15		T18	20		T95	1
values[8]	697	1			T12	10		T82	1		T33	32
values[9]	2839	1			T14	5		T17	10		T20	9
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	675	1			T82	15		T85	3		T96	1
values[1]	713	1			T34	21		T141	11		T115	10
values[2]	575	1			T12	16		T22	17		T23	1
values[3]	775	1			T15	5		T24	1		T89	16
values[4]	580	1			T14	13		T15	11		T21	1
values[5]	688	1			T18	22		T21	23		T22	15
values[6]	2369	1			T14	15		T17	10		T18	20
values[7]	612	1			T12	10		T82	1		T33	32
values[8]	985	1			T14	5		T23	1		T34	15
values[9]	123	1			T20	9		T82	3		T132	1
minimum	17124	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T85	1		T89	3		T116	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T82	1		T96	1		T97	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T34	10		T91	13		T112	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	6		T115	1		T216	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T22	7		T23	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	16		T93	11		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	1		T24	1		T124	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T89	16		T135	6		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	8		T35	10		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	1		T21	1		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T21	11		T85	6		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T18	10		T22	11		T135	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T17	2		T18	11		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T14	8		T134	1		T100	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	10		T82	1		T220	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T33	15		T221	1		T181	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T34	15		T132	2		T90	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	1		T23	1		T86	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T132	1		T295	1		T256	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T20	1		T82	1		T89	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T13	19		T16	20		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T260	1		T282	3		T211	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T85	2		T116	13		T215	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T82	14		T97	9		T98	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	11		T91	11		T112	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T141	5		T115	9		T216	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	10		T33	1		T90	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T93	13		T103	8		T107	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	4		T124	12		T232	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T126	10		T214	5		T217	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	5		T35	9		T246	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	10		T33	1		T115	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	12		T85	10		T126	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T18	12		T22	4		T124	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T17	8		T18	9		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	7		T100	17		T268	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T220	10		T128	4		T122	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T33	17		T181	2		T296	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T90	10		T247	12		T91	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T14	4		T86	5		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T249	15		T297	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T20	8		T82	2		T248	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T243	14		T267	11		T262	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T247	1		T298	1		T280	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T23	1		T183	10		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T250	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T85	1		T89	3		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T82	1		T96	1		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T34	10		T91	13		T116	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T141	6		T115	1		T216	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T23	1		T24	1		T33	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	16		T93	11		T110	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	1		T22	7		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T89	16		T135	6		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T246	1		T214	4		T232	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	1		T82	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	8		T21	11		T85	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T18	10		T21	1		T22	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T18	11		T95	1		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T14	8		T134	1		T135	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	10		T82	1		T220	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	15		T181	4		T238	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T17	2		T34	15		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	1		T20	1		T82	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T247	12		T280	13		T272	26
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T183	11		T137	3		T269	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T85	2		T35	1		T215	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T82	14		T97	9		T98	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T34	11		T91	11		T116	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T141	5		T115	9		T216	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T33	1		T90	10		T116	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T93	13		T103	8		T237	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	4		T22	10		T124	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T126	10		T100	8		T107	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T246	9		T214	2		T232	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	10		T33	1		T92	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	5		T21	12		T85	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T18	12		T22	4		T115	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T18	9		T34	1		T125	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	7		T124	14		T100	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T220	10		T128	4		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T33	17		T181	2		T296	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T17	8		T142	11		T99	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T14	4		T20	8		T82	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T85	3		T89	1		T116	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T82	15		T96	1		T97	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	12		T91	12		T112	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T141	6		T115	10		T216	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T22	11		T23	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	1		T93	14		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	5		T24	1		T124	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T89	1		T135	1		T126	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	6		T35	10		T246	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	11		T21	1		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T21	13		T85	11		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T18	13		T22	5		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T17	10		T18	10		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	8		T134	1		T100	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T82	1		T220	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T33	18		T221	1		T181	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T34	1		T132	2		T90	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T14	5		T23	1		T86	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T132	1		T295	1		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T20	9		T82	3		T89	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17022	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T260	1		T282	1		T211	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T89	2		T116	11		T215	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T98	11		T213	1		T183	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	9		T91	12		T112	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T141	5		T216	8		T225	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T22	6		T33	5		T90	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	15		T93	10		T103	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T124	13		T232	15		T119	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T89	15		T135	5		T214	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	7		T35	9		T214	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T92	5		T93	11		T112	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T21	10		T85	5		T100	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T18	9		T22	10		T135	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T18	10		T131	24		T242	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T14	7		T100	11		T120	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	9		T220	11		T144	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T33	14		T181	2		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T34	14		T90	10		T135	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T86	6		T183	9		T232	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T256	4		T249	11		T299	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T89	4		T300	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T121	13		T237	13		T293	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T282	2		T211	6		T243	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T247	13		T298	1		T280	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T23	1		T183	12		T137	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T250	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T85	3		T89	1		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T82	15		T96	1		T97	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T34	12		T91	12		T116	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T141	6		T115	10		T216	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T23	1		T24	1		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	1		T93	14		T110	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T15	5		T22	11		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T89	1		T135	1		T126	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T246	10		T214	5		T232	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	11		T82	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	6		T21	13		T85	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T18	13		T21	1		T22	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T18	10		T95	1		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	8		T134	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	1		T82	1		T220	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	18		T181	4		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T17	10		T34	1		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T14	5		T20	9		T82	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T299	7		T265	13		T272	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T183	9		T300	12		T301	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T89	2		T215	1		T112	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T98	11		T213	1		T183	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T34	9		T91	12		T116	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T141	5		T216	8		T225	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T33	5		T90	10		T116	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	15		T93	10		T103	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T22	6		T124	13		T119	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T89	15		T135	5		T100	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T214	1		T232	15		T258	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T92	5		T214	3		T112	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	7		T21	10		T85	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T18	9		T22	10		T93	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T18	10		T125	2		T116	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T14	7		T135	8		T124	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	9		T220	11		T144	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T33	14		T181	2		T238	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T34	14		T131	24		T90	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T86	6		T89	4		T232	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19