Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22205

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3014

1

T12

26

T14

5

T20

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19894

1

T5

1

T28

1

T46

3

auto[1]

5325

1

T12

10

T14

15

T15

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	243	1			T124	26		T116	3		T100	17
values[0]	34	1			T82	15		T216	19		-	-
values[1]	403	1			T23	1		T95	1		T33	7
values[2]	717	1			T12	16		T85	16		T96	1
values[3]	637	1			T12	10		T14	28		T21	1
values[4]	2659	1			T17	10		T24	1		T34	15
values[5]	702	1			T15	11		T91	8		T126	11
values[6]	489	1			T14	5		T20	9		T22	17
values[7]	640	1			T18	20		T95	1		T34	21
values[8]	804	1			T18	22		T24	1		T82	1
values[9]	936	1			T15	5		T21	23		T23	1
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	469	1			T82	15		T95	1		T33	7
values[1]	737	1			T12	16		T21	1		T22	15
values[2]	716	1			T12	10		T14	28		T82	3
values[3]	2553	1			T17	10		T24	1		T34	15
values[4]	726	1			T14	5		T15	11		T175	1
values[5]	453	1			T20	9		T22	17		T34	21
values[6]	742	1			T18	42		T95	1		T260	1
values[7]	736	1			T24	1		T82	1		T90	21
values[8]	829	1			T15	5		T21	23		T23	1
values[9]	181	1			T85	3		T34	2		T124	26
minimum	17077	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T82	1		T95	1		T33	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T93	12		T111	1		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T22	11		T89	16		T90	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	16		T21	1		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T14	16		T98	12		T86	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	10		T82	1		T135	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T17	2		T24	1		T34	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T132	2		T277	1		T102	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	1		T225	8		T103	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	1		T175	1		T91	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T125	3		T112	5		T302	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T20	1		T22	7		T34	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T18	21		T95	1		T260	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T175	1		T116	12		T121	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T24	1		T82	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T90	11		T213	3		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	1		T97	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	11		T23	1		T33	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T85	1		T218	4		T257	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T34	1		T124	14		T183	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T13	19		T16	20		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T23	1		T246	1		T282	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T82	14		T33	1		T254	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T93	10		T279	9		T283	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T22	4		T90	10		T214	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T85	10		T92	12		T233	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	12		T98	12		T86	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T82	2		T35	9		T214	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T17	8		T142	11		T99	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T224	7		T280	13		T285	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	10		T225	8		T103	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	4		T91	3		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T125	1		T112	4		T234	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T20	8		T22	10		T34	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T18	21		T220	10		T124	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T116	13		T121	14		T171	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T35	1		T115	13		T121	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T90	10		T213	1		T115	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T15	4		T97	9		T247	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T21	12		T33	18		T116	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T85	2		T222	7		T235	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T34	1		T124	12		T222	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T246	9		T296	1		T301	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T100	9		T222	4		T235	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T124	14		T116	2		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T82	1		T216	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T95	1		T33	6		T266	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T23	1		T246	1		T93	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T89	16		T90	11		T135	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	16		T85	6		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	16		T22	11		T98	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	10		T21	1		T82	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T17	2		T24	1		T34	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T132	2		T135	16		T35	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	1		T225	8		T103	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T91	5		T126	1		T253	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T125	3		T110	2		T112	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T20	1		T22	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T18	11		T95	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	10		T175	1		T116	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T18	10		T24	1		T82	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T213	3		T260	1		T93	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T15	1		T85	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T21	11		T23	1		T33	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T100	8		T222	7		T235	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T124	12		T116	1		T219	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T82	14		T216	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T33	1		T254	6		T303	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T246	9		T93	10		T279	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T90	10		T214	5		T226	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T85	10		T233	5		T304	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	12		T22	4		T98	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T82	2		T92	12		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T17	8		T141	5		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T35	9		T105	7		T224	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	10		T225	8		T103	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T91	3		T126	10		T253	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T125	1		T112	4		T305	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	4		T20	8		T22	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T18	9		T220	10		T104	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T34	11		T116	13		T121	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T18	12		T124	14		T115	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T213	1		T93	13		T116	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	4		T85	2		T97	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T21	12		T33	18		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T82	15		T95	1		T33	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T93	11		T111	1		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T22	5		T89	1		T90	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	1		T21	1		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T14	14		T98	13		T86	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T12	1		T82	3		T135	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T17	10		T24	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T132	2		T277	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	11		T225	9		T103	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	5		T175	1		T91	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T125	2		T112	5		T302	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	9		T22	11		T34	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T18	23		T95	1		T260	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T175	1		T116	14		T121	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T24	1		T82	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T90	11		T213	3		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T15	5		T97	10		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T21	13		T23	1		T33	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T85	3		T218	1		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T34	2		T124	13		T183	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16973	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T23	1		T246	10		T282	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T33	5		T135	5		T271	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T93	11		T283	2		T138	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T22	10		T89	15		T90	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	15		T85	5		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	14		T98	11		T86	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	9		T135	23		T35	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T34	14		T131	24		T242	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T102	2		T123	6		T224	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T225	7		T103	7		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T91	4		T100	10		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T125	2		T112	4		T306	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T22	6		T34	9		T35	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T18	19		T220	11		T124	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T116	11		T121	13		T171	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T238	2		T121	9		T233	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T90	10		T213	1		T93	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T100	8		T112	4		T120	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	10		T33	14		T116	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T218	3		T257	2		T222	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T124	13		T183	9		T222	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T216	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T282	2		T301	6		T273	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T100	9		T222	8		T235	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T124	13		T116	2		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T82	15		T216	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T95	1		T33	2		T266	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T23	1		T246	10		T93	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T89	1		T90	11		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T85	11		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	14		T22	5		T98	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T12	1		T21	1		T82	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T17	10		T24	1		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T132	2		T135	1		T35	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	11		T225	9		T103	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T91	4		T126	11		T253	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T125	2		T110	2		T112	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	5		T20	9		T22	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T18	10		T95	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T34	12		T175	1		T116	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T18	13		T24	1		T82	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T213	3		T260	1		T93	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T15	5		T85	3		T97	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T21	13		T23	1		T33	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T100	8		T222	3		T307	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T124	13		T116	1		T219	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T216	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T33	5		T119	10		T162	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T93	11		T282	2		T283	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T89	15		T90	10		T135	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	15		T85	5		T120	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	14		T22	10		T98	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	9		T89	2		T135	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T34	14		T141	5		T131	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T135	15		T35	9		T102	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T225	7		T103	7		T227	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T91	4		T225	12		T285	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T125	2		T112	4		T306	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	6		T35	7		T100	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T18	10		T220	11		T120	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	9		T116	11		T101	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T18	9		T124	15		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T213	1		T93	10		T116	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T112	4		T120	4		T121	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T21	10		T33	14		T90	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19