Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20043

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

5176

1

T14

18

T17

10

T20

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19814

1

T5

1

T28

1

T46

3

auto[1]

5405

1

T12

10

T14

15

T15

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T308	13		T309	10		-	-
values[0]	96	1			T171	28		T243	24		T164	9
values[1]	539	1			T21	23		T85	16		T33	7
values[2]	518	1			T20	9		T24	1		T97	10
values[3]	859	1			T12	16		T22	17		T34	15
values[4]	667	1			T18	20		T21	1		T22	15
values[5]	628	1			T82	19		T85	3		T33	2
values[6]	628	1			T82	1		T141	11		T217	1
values[7]	658	1			T14	15		T15	11		T18	22
values[8]	735	1			T14	5		T23	2		T95	1
values[9]	2913	1			T12	10		T14	13		T15	5
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	710	1			T20	9		T21	23		T85	16
values[1]	2548	1			T17	10		T24	1		T97	10
values[2]	793	1			T12	16		T18	20		T22	17
values[3]	598	1			T21	1		T82	3		T135	6
values[4]	666	1			T22	15		T82	17		T85	3
values[5]	667	1			T15	11		T86	16		T132	1
values[6]	575	1			T14	15		T18	22		T95	1
values[7]	831	1			T14	5		T15	5		T23	2
values[8]	705	1			T12	10		T14	13		T132	1
values[9]	134	1			T34	2		T103	1		T280	14
minimum	16992	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T85	6		T33	6		T34	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	1		T21	11		T90	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T260	1		T181	4		T216	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1281	1			T17	2		T24	1		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	16		T18	11		T22	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T34	15		T98	12		T135	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	1		T82	1		T135	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T183	10		T226	10		T116	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T82	2		T33	1		T141	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	11		T82	1		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	1		T86	11		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T89	16		T217	1		T100	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	8		T18	10		T92	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T95	1		T134	1		T35	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	1		T23	1		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	1		T23	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	10		T132	1		T89	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	8		T39	1		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T305	11		T310	2		T311	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T34	1		T103	1		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16822	1			T13	19		T16	20		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T112	5		T237	13		T156	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T85	10		T33	1		T34	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T20	8		T21	12		T90	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T181	2		T216	10		T268	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	996	1			T17	8		T97	9		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T18	9		T22	10		T90	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T98	12		T115	22		T93	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T82	2		T247	12		T124	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T226	2		T116	1		T104	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	1		T141	5		T171	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T22	4		T82	14		T85	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	10		T86	5		T144	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T217	1		T100	17		T112	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	7		T18	12		T92	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T35	1		T112	8		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	4		T33	17		T124	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	4		T220	10		T225	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T213	1		T35	9		T126	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	5		T39	1		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T305	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T34	1		T280	13		T312	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T112	4		T237	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T308	8		T309	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T243	10		T313	12		T314	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T171	14		T164	3		T315	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T85	6		T33	6		T34	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T21	11		T90	11		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T89	3		T181	4		T216	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T20	1		T24	1		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	16		T22	7		T90	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T34	15		T98	12		T115	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T18	11		T21	1		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T22	11		T135	25		T183	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T82	2		T33	1		T135	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T82	1		T85	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T82	1		T141	6		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T112	7		T289	1		T105	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	8		T15	1		T18	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T95	1		T35	1		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T23	1		T33	15		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	1		T23	1		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T12	10		T15	1		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1382	1			T14	8		T17	2		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T308	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T243	14		T314	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T171	14		T164	6		T315	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T85	10		T33	1		T34	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T21	12		T90	10		T125	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T181	2		T216	10		T234	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T20	8		T97	9		T116	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T22	10		T90	10		T126	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T98	12		T115	22		T227	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T18	9		T247	12		T93	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T22	4		T93	6		T116	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T82	2		T33	1		T124	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T82	14		T85	2		T115	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T141	5		T107	13		T53	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T112	10		T105	7		T316	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	7		T15	10		T18	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T35	1		T217	1		T100	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T33	17		T183	11		T214	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	4		T220	10		T112	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	4		T213	1		T124	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1064	1			T14	5		T17	8		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T85	11		T33	2		T34	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	9		T21	13		T90	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T260	1		T181	4		T216	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1314	1			T17	10		T24	1		T97	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T18	10		T22	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T34	1		T98	13		T135	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T21	1		T82	3		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T183	1		T226	10		T116	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T82	2		T33	2		T141	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T22	5		T82	15		T85	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T15	11		T86	10		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T89	1		T217	2		T100	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	8		T18	13		T92	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T95	1		T134	1		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	5		T23	1		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T14	5		T23	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T132	1		T89	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	6		T39	2		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T305	8		T310	1		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T34	2		T103	1		T280	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16956	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T112	5		T237	12		T156	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T85	5		T33	5		T34	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T21	10		T90	10		T125	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T181	2		T216	8		T145	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	963	1			T131	24		T242	5		T317	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	15		T18	10		T22	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T34	14		T98	11		T135	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T135	5		T124	13		T120	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T183	9		T226	2		T116	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T141	5		T119	10		T171	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T22	10		T91	12		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T86	6		T101	2		T144	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T89	15		T100	11		T112	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T14	7		T18	9		T92	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T35	7		T112	4		T120	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	14		T124	15		T91	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T220	11		T225	12		T233	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	9		T89	4		T213	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	7		T144	16		T237	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T305	10		T310	1		T311	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T312	11		T310	7		T281	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T318	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T112	4		T237	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T308	6		T309	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T243	15		T313	1		T314	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T171	15		T164	7		T315	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T85	11		T33	2		T34	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T21	13		T90	11		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T89	1		T181	4		T216	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	9		T24	1		T97	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T22	11		T90	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T34	1		T98	13		T115	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T18	10		T21	1		T247	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	5		T135	2		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T82	4		T33	2		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T82	15		T85	3		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T82	1		T141	6		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T112	11		T289	1		T105	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	8		T15	11		T18	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T95	1		T35	2		T217	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T23	1		T33	18		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	5		T23	1		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T12	1		T15	5		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1403	1			T14	6		T17	10		T34	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T308	7		T309	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T243	9		T313	11		T314	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T171	13		T164	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T85	5		T33	5		T34	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T21	10		T90	10		T125	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T89	2		T181	2		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T116	11		T102	2		T54	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	15		T22	6		T90	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T34	14		T98	11		T224	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T18	10		T93	11		T120	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T22	10		T135	23		T183	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T135	5		T124	13		T103	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T89	15		T91	12		T238	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T141	5		T101	2		T119	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T112	6		T105	7		T182	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	7		T18	9		T86	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T100	11		T120	3		T225	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T33	14		T183	9		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T220	11		T35	7		T112	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	9		T89	4		T213	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1043	1			T14	7		T131	24		T242	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19