Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25219

1

T5

1

T28

1

T46

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21951

1

T5

1

T28

1

T46

3

auto[ADC_CTRL_FILTER_COND_OUT]

3268

1

T12

26

T14

13

T15

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19874

1

T5

1

T28

1

T46

3

auto[1]

5345

1

T12

26

T14

20

T15

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21287

1

T12

26

T13

19

T14

17

auto[1]

3932

1

T5

1

T28

1

T46

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T233	18		T106	1		T251	2
values[0]	47	1			T175	1		T100	29		T232	16
values[1]	611	1			T12	26		T14	15		T98	24
values[2]	615	1			T22	15		T34	21		T89	3
values[3]	483	1			T82	1		T33	2		T96	1
values[4]	610	1			T22	17		T24	1		T85	3
values[5]	2619	1			T15	5		T17	10		T142	12
values[6]	627	1			T15	11		T82	4		T85	16
values[7]	621	1			T14	5		T24	1		T82	15
values[8]	634	1			T21	24		T95	1		T132	1
values[9]	1376	1			T14	13		T18	42		T20	9
minimum	16955	1			T5	1		T28	1		T46	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	839	1			T12	26		T14	15		T98	24
values[1]	492	1			T22	15		T82	1		T217	2
values[2]	542	1			T22	17		T33	9		T96	1
values[3]	2651	1			T15	5		T17	10		T24	1
values[4]	622	1			T82	3		T85	3		T260	1
values[5]	554	1			T15	11		T82	1		T85	16
values[6]	614	1			T14	5		T24	1		T82	15
values[7]	765	1			T21	24		T23	1		T95	1
values[8]	1029	1			T14	13		T18	42		T23	1
values[9]	154	1			T20	9		T89	5		T213	4
minimum	16957	1			T5	1		T28	1		T46	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

3443

1

T12

24

T14

14

T18

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T14	8		T260	1		T232	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	26		T98	12		T86	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T22	11		T217	1		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T82	1		T120	4		T103	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T22	7		T33	1		T34	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T33	6		T96	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T15	1		T17	2		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T24	1		T132	1		T220	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T82	1		T85	1		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T221	1		T225	8		T261	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T33	15		T34	16		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T15	1		T82	1		T85	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	1		T35	8		T91	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	1		T82	1		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T21	11		T23	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T21	1		T95	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T18	11		T23	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T14	8		T18	10		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T89	5		T175	1		T106	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T20	1		T213	3		T235	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T39	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	7		T232	11		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T98	12		T86	5		T100	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T22	4		T217	1		T112	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T224	11		T243	14		T234	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T22	10		T33	1		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T33	1		T35	1		T125	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T15	4		T17	8		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T220	10		T91	3		T233	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T82	2		T85	2		T253	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T225	8		T261	2		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T33	17		T34	1		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	10		T85	10		T115	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	4		T91	11		T227	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T82	14		T115	13		T232	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T21	12		T247	12		T121	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T126	2		T116	1		T100	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T18	9		T141	5		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T14	5		T18	12		T97	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T53	7		T259	1		T264	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T20	8		T213	1		T235	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T39	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T106	1		T251	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T233	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T232	5		T283	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T175	1		T100	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	8		T260	1		T119	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	26		T98	12		T86	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T22	11		T34	10		T89	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T266	1		T224	13		T243	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T33	1		T183	10		T93	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T82	1		T96	1		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T22	7		T85	1		T135	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T24	1		T33	6		T132	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T15	1		T17	2		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T225	8		T103	1		T233	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T82	1		T33	15		T34	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	1		T82	1		T85	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	1		T35	8		T91	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	1		T82	1		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T21	11		T102	3		T121	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T21	1		T95	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T18	11		T23	2		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	439	1			T14	8		T18	10		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16819	1			T13	19		T16	20		T19	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T251	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T233	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T232	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T100	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T14	7		T144	7		T107	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T98	12		T86	5		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T22	4		T34	11		T217	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T224	11		T243	14		T234	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T33	1		T183	11		T93	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T35	1		T125	1		T319	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T22	10		T85	2		T93	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T33	1		T220	10		T91	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T15	4		T17	8		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T225	8		T233	2		T105	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T82	2		T33	17		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	10		T85	10		T92	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	4		T91	11		T227	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T82	14		T115	9		T126	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T21	12		T121	14		T171	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T115	13		T126	2		T107	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T18	9		T141	5		T247	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T14	5		T18	12		T20	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T28	1		T46	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T14	8		T260	1		T232	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	2		T98	13		T86	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T22	5		T217	2		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T82	1		T120	1		T103	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T22	11		T33	2		T34	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T33	2		T96	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T15	5		T17	10		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T24	1		T132	1		T220	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T82	3		T85	3		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T221	1		T225	9		T261	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T33	18		T34	3		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	11		T82	1		T85	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	5		T35	1		T91	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T24	1		T82	15		T115	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T21	13		T23	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T21	1		T95	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T18	10		T23	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T14	6		T18	13		T97	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T89	1		T175	1		T106	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T20	9		T213	3		T235	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T39	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	7		T232	4		T257	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	24		T98	11		T86	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	10		T112	4		T120	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T120	3		T224	12		T243	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T22	6		T34	9		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T33	5		T125	2		T218	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T131	24		T90	10		T242	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T220	11		T91	4		T183	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T214	1		T215	1		T121	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T225	7		T108	9		T320	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T33	14		T34	14		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T85	5		T92	5		T255	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	7		T91	12		T236	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T232	15		T144	5		T54	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T21	10		T135	15		T102	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T116	1		T100	18		T271	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T18	10		T141	5		T135	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T14	7		T18	9		T124	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T89	4		T53	8		T264	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T213	1		T262	2		T263	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T106	1		T251	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T233	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T232	12		T283	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T175	1		T100	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	8		T260	1		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	2		T98	13		T86	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T22	5		T34	12		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T266	1		T224	12		T243	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T33	2		T183	12		T93	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T82	1		T96	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T22	11		T85	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	1		T33	2		T132	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T15	5		T17	10		T142	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T225	9		T103	1		T233	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T82	3		T33	18		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T15	11		T82	1		T85	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	5		T35	1		T91	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T24	1		T82	15		T115	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T21	13		T102	1		T121	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	1		T95	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T18	10		T23	2		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	435	1			T14	6		T18	13		T20	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T5	1		T28	1		T46	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T233	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T232	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T100	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	7		T119	10		T257	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	24		T98	11		T86	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T22	10		T34	9		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T224	12		T243	13		T270	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T183	9		T93	6		T216	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T125	2		T120	3		T218	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T22	6		T135	8		T93	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T33	5		T220	11		T91	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T131	24		T90	10		T242	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T225	7		T233	4		T108	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T33	14		T34	14		T90	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T85	5		T92	5		T144	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T35	7		T91	12		T236	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T116	1		T232	15		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T21	10		T102	2		T121	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T54	12		T182	10		T274	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T18	10		T141	5		T89	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T14	7		T18	9		T213	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21776

1

T5

1

T28

1

T46

3

auto[1]

auto[0]

3443

1

T12

24

T14

14

T18

19