Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.54 98.98 95.70 100.00 100.00 98.18 98.64 91.29


Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T771 /workspace/coverage/default/32.adc_ctrl_clock_gating.445320723 Dec 24 01:14:57 PM PST 23 Dec 24 01:16:09 PM PST 23 162537151855 ps
T149 /workspace/coverage/default/25.adc_ctrl_clock_gating.3097595344 Dec 24 01:14:48 PM PST 23 Dec 24 01:17:45 PM PST 23 490268284512 ps
T772 /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4159806996 Dec 24 01:14:53 PM PST 23 Dec 24 01:17:51 PM PST 23 164743780651 ps
T773 /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3093476975 Dec 24 01:14:06 PM PST 23 Dec 24 01:32:47 PM PST 23 487313549247 ps
T774 /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.740563666 Dec 24 01:14:51 PM PST 23 Dec 24 01:18:10 PM PST 23 77755104584 ps
T775 /workspace/coverage/default/16.adc_ctrl_alert_test.3916984933 Dec 24 01:14:51 PM PST 23 Dec 24 01:15:13 PM PST 23 466278435 ps
T297 /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4048474723 Dec 24 01:14:00 PM PST 23 Dec 24 01:16:07 PM PST 23 212955195686 ps
T776 /workspace/coverage/default/18.adc_ctrl_alert_test.3189979134 Dec 24 01:14:34 PM PST 23 Dec 24 01:14:42 PM PST 23 454134583 ps
T777 /workspace/coverage/default/48.adc_ctrl_alert_test.2024146119 Dec 24 01:15:26 PM PST 23 Dec 24 01:15:51 PM PST 23 348402013 ps
T778 /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1506560882 Dec 24 01:14:49 PM PST 23 Dec 24 01:33:11 PM PST 23 492036630060 ps
T779 /workspace/coverage/default/21.adc_ctrl_alert_test.1024194478 Dec 24 01:14:45 PM PST 23 Dec 24 01:14:55 PM PST 23 521318428 ps
T780 /workspace/coverage/default/6.adc_ctrl_lowpower_counter.8823529 Dec 24 01:13:58 PM PST 23 Dec 24 01:14:30 PM PST 23 41184185452 ps
T781 /workspace/coverage/default/19.adc_ctrl_poweron_counter.1849349659 Dec 24 01:14:31 PM PST 23 Dec 24 01:14:42 PM PST 23 5271930271 ps
T782 /workspace/coverage/default/46.adc_ctrl_filters_polled.3748934350 Dec 24 01:15:20 PM PST 23 Dec 24 01:19:00 PM PST 23 324273374673 ps
T783 /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2838596008 Dec 24 01:14:57 PM PST 23 Dec 24 01:15:36 PM PST 23 30921114365 ps
T784 /workspace/coverage/default/25.adc_ctrl_filters_polled.1057453292 Dec 24 01:14:33 PM PST 23 Dec 24 01:19:42 PM PST 23 498171604541 ps
T785 /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2374803566 Dec 24 01:14:10 PM PST 23 Dec 24 01:33:26 PM PST 23 484145212955 ps
T331 /workspace/coverage/default/18.adc_ctrl_clock_gating.1177637048 Dec 24 01:14:34 PM PST 23 Dec 24 01:22:38 PM PST 23 498799570474 ps
T786 /workspace/coverage/default/5.adc_ctrl_filters_both.2974687122 Dec 24 01:14:32 PM PST 23 Dec 24 01:25:32 PM PST 23 500588962667 ps
T787 /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2320519494 Dec 24 01:14:15 PM PST 23 Dec 24 01:15:35 PM PST 23 28735509572 ps
T349 /workspace/coverage/default/5.adc_ctrl_clock_gating.2041244219 Dec 24 01:14:19 PM PST 23 Dec 24 01:27:20 PM PST 23 493145418451 ps
T251 /workspace/coverage/default/27.adc_ctrl_clock_gating.3447269933 Dec 24 01:14:40 PM PST 23 Dec 24 01:21:50 PM PST 23 485063986705 ps
T788 /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3129723219 Dec 24 01:15:28 PM PST 23 Dec 24 01:16:27 PM PST 23 169517699766 ps
T789 /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.711166005 Dec 24 01:15:07 PM PST 23 Dec 24 01:17:01 PM PST 23 500767446776 ps
T790 /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2089298352 Dec 24 01:14:03 PM PST 23 Dec 24 01:20:32 PM PST 23 160721625351 ps
T291 /workspace/coverage/default/24.adc_ctrl_filters_both.2371080279 Dec 24 01:14:50 PM PST 23 Dec 24 01:22:11 PM PST 23 360638526556 ps
T791 /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3861533464 Dec 24 01:15:01 PM PST 23 Dec 24 01:18:51 PM PST 23 160457397422 ps
T792 /workspace/coverage/default/6.adc_ctrl_filters_both.2749278197 Dec 24 01:13:59 PM PST 23 Dec 24 01:22:59 PM PST 23 492463720661 ps
T793 /workspace/coverage/default/32.adc_ctrl_poweron_counter.4040529974 Dec 24 01:14:57 PM PST 23 Dec 24 01:15:33 PM PST 23 4186948629 ps
T794 /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.57278759 Dec 24 01:14:21 PM PST 23 Dec 24 01:27:08 PM PST 23 330937711071 ps
T795 /workspace/coverage/default/28.adc_ctrl_poweron_counter.2342885469 Dec 24 01:14:40 PM PST 23 Dec 24 01:14:50 PM PST 23 3841818231 ps
T796 /workspace/coverage/default/31.adc_ctrl_filters_both.3410931636 Dec 24 01:14:52 PM PST 23 Dec 24 01:18:20 PM PST 23 326126604360 ps
T797 /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3166975225 Dec 24 01:14:30 PM PST 23 Dec 24 01:16:18 PM PST 23 44925710814 ps
T798 /workspace/coverage/default/17.adc_ctrl_filters_both.1529911645 Dec 24 01:14:44 PM PST 23 Dec 24 01:18:11 PM PST 23 161061355386 ps
T799 /workspace/coverage/default/27.adc_ctrl_poweron_counter.833350190 Dec 24 01:14:46 PM PST 23 Dec 24 01:14:59 PM PST 23 4990776181 ps
T800 /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.864117632 Dec 24 01:14:39 PM PST 23 Dec 24 01:28:02 PM PST 23 326879188952 ps
T801 /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2572636650 Dec 24 01:14:46 PM PST 23 Dec 24 01:17:11 PM PST 23 495570422596 ps
T802 /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2779737793 Dec 24 01:14:01 PM PST 23 Dec 24 01:15:21 PM PST 23 162357109219 ps
T278 /workspace/coverage/default/43.adc_ctrl_filters_polled.851749853 Dec 24 01:15:20 PM PST 23 Dec 24 01:18:08 PM PST 23 330760988096 ps
T803 /workspace/coverage/default/22.adc_ctrl_fsm_reset.2418696720 Dec 24 01:14:32 PM PST 23 Dec 24 01:19:53 PM PST 23 83001293346 ps
T287 /workspace/coverage/default/35.adc_ctrl_filters_wakeup.605254029 Dec 24 01:14:56 PM PST 23 Dec 24 01:20:15 PM PST 23 494361211767 ps
T309 /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4028777834 Dec 24 01:14:37 PM PST 23 Dec 24 01:25:55 PM PST 23 327953062177 ps
T804 /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.910683182 Dec 24 01:15:27 PM PST 23 Dec 24 01:16:59 PM PST 23 331730243736 ps
T805 /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2645015813 Dec 24 01:14:46 PM PST 23 Dec 24 01:15:08 PM PST 23 36288034221 ps
T806 /workspace/coverage/default/42.adc_ctrl_smoke.2926037845 Dec 24 01:15:20 PM PST 23 Dec 24 01:15:49 PM PST 23 5865855352 ps
T807 /workspace/coverage/default/46.adc_ctrl_clock_gating.4212145644 Dec 24 01:15:25 PM PST 23 Dec 24 01:17:11 PM PST 23 162025210066 ps
T808 /workspace/coverage/default/15.adc_ctrl_filters_polled.1563992814 Dec 24 01:14:21 PM PST 23 Dec 24 01:34:20 PM PST 23 489892402142 ps
T809 /workspace/coverage/default/22.adc_ctrl_poweron_counter.1571452099 Dec 24 01:14:32 PM PST 23 Dec 24 01:14:42 PM PST 23 3737450776 ps
T150 /workspace/coverage/default/16.adc_ctrl_filters_both.3418994809 Dec 24 01:14:46 PM PST 23 Dec 24 01:24:22 PM PST 23 501315100149 ps
T810 /workspace/coverage/default/12.adc_ctrl_filters_polled.3205382952 Dec 24 01:14:43 PM PST 23 Dec 24 01:18:07 PM PST 23 160513485156 ps
T811 /workspace/coverage/default/1.adc_ctrl_filters_both.4179717472 Dec 24 01:14:01 PM PST 23 Dec 24 01:26:43 PM PST 23 327949917891 ps
T812 /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3120309908 Dec 24 01:14:57 PM PST 23 Dec 24 01:22:06 PM PST 23 332667976814 ps
T813 /workspace/coverage/default/27.adc_ctrl_lowpower_counter.4156484030 Dec 24 01:14:49 PM PST 23 Dec 24 01:16:46 PM PST 23 44924243037 ps
T814 /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2532294981 Dec 24 01:14:06 PM PST 23 Dec 24 01:27:49 PM PST 23 328039940570 ps
T815 /workspace/coverage/default/17.adc_ctrl_filters_polled.1372750726 Dec 24 01:14:36 PM PST 23 Dec 24 01:28:09 PM PST 23 325594126007 ps
T816 /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2853988423 Dec 24 01:15:25 PM PST 23 Dec 24 01:22:03 PM PST 23 164109420065 ps
T817 /workspace/coverage/default/47.adc_ctrl_stress_all.304739507 Dec 24 01:15:25 PM PST 23 Dec 24 01:22:28 PM PST 23 170963074260 ps
T338 /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2026389815 Dec 24 01:14:46 PM PST 23 Dec 24 01:16:30 PM PST 23 161907242881 ps
T818 /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1196827415 Dec 24 01:15:00 PM PST 23 Dec 24 01:28:03 PM PST 23 337094693059 ps
T819 /workspace/coverage/default/24.adc_ctrl_filters_polled.4055390942 Dec 24 01:14:38 PM PST 23 Dec 24 01:16:17 PM PST 23 161937314595 ps
T820 /workspace/coverage/default/28.adc_ctrl_alert_test.320964797 Dec 24 01:14:49 PM PST 23 Dec 24 01:15:09 PM PST 23 459297831 ps
T821 /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3898458985 Dec 24 01:14:47 PM PST 23 Dec 24 01:16:43 PM PST 23 164432455780 ps
T822 /workspace/coverage/default/6.adc_ctrl_fsm_reset.3961952524 Dec 24 01:13:56 PM PST 23 Dec 24 01:21:53 PM PST 23 134265903510 ps
T151 /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2664179675 Dec 24 01:14:39 PM PST 23 Dec 24 01:16:38 PM PST 23 326932366544 ps
T823 /workspace/coverage/default/19.adc_ctrl_fsm_reset.3893220392 Dec 24 01:14:51 PM PST 23 Dec 24 01:23:10 PM PST 23 88959641990 ps
T824 /workspace/coverage/default/46.adc_ctrl_alert_test.1290964567 Dec 24 01:15:20 PM PST 23 Dec 24 01:15:46 PM PST 23 427711152 ps
T825 /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4166924420 Dec 24 01:15:26 PM PST 23 Dec 24 01:17:18 PM PST 23 160528938720 ps
T826 /workspace/coverage/default/38.adc_ctrl_fsm_reset.2719656030 Dec 24 01:15:09 PM PST 23 Dec 24 01:24:07 PM PST 23 135512612550 ps
T827 /workspace/coverage/default/11.adc_ctrl_smoke.726319573 Dec 24 01:14:31 PM PST 23 Dec 24 01:14:42 PM PST 23 5720376533 ps
T342 /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1588851347 Dec 24 01:14:52 PM PST 23 Dec 24 01:17:22 PM PST 23 163807684499 ps
T828 /workspace/coverage/default/18.adc_ctrl_fsm_reset.2410208034 Dec 24 01:14:46 PM PST 23 Dec 24 01:21:49 PM PST 23 81391202040 ps
T829 /workspace/coverage/default/31.adc_ctrl_smoke.2535794692 Dec 24 01:14:52 PM PST 23 Dec 24 01:15:15 PM PST 23 5960075779 ps
T830 /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3461573026 Dec 24 01:14:51 PM PST 23 Dec 24 01:16:04 PM PST 23 44106546676 ps
T831 /workspace/coverage/default/42.adc_ctrl_filters_both.592319934 Dec 24 01:15:08 PM PST 23 Dec 24 01:24:25 PM PST 23 487342546822 ps
T832 /workspace/coverage/default/6.adc_ctrl_poweron_counter.1551069884 Dec 24 01:14:06 PM PST 23 Dec 24 01:14:27 PM PST 23 3729114987 ps
T833 /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2309574019 Dec 24 01:15:22 PM PST 23 Dec 24 01:19:09 PM PST 23 337689428064 ps
T834 /workspace/coverage/default/9.adc_ctrl_alert_test.3246967650 Dec 24 01:14:12 PM PST 23 Dec 24 01:14:29 PM PST 23 401199245 ps
T835 /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.989101321 Dec 24 01:14:08 PM PST 23 Dec 24 01:17:31 PM PST 23 327902566493 ps
T836 /workspace/coverage/default/29.adc_ctrl_smoke.1391324866 Dec 24 01:14:53 PM PST 23 Dec 24 01:15:19 PM PST 23 6089114078 ps
T837 /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.659967106 Dec 24 01:14:42 PM PST 23 Dec 24 01:17:26 PM PST 23 124163497068 ps
T838 /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2142190319 Dec 24 01:13:59 PM PST 23 Dec 24 01:15:00 PM PST 23 23373526372 ps
T839 /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2965012802 Dec 24 01:14:01 PM PST 23 Dec 24 01:17:44 PM PST 23 161345304116 ps
T252 /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2577196859 Dec 24 01:14:01 PM PST 23 Dec 24 01:27:20 PM PST 23 330625587560 ps
T840 /workspace/coverage/default/19.adc_ctrl_alert_test.35258289 Dec 24 01:14:48 PM PST 23 Dec 24 01:15:00 PM PST 23 530537258 ps
T841 /workspace/coverage/default/13.adc_ctrl_alert_test.694780308 Dec 24 01:14:33 PM PST 23 Dec 24 01:14:42 PM PST 23 488119097 ps
T152 /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2945440142 Dec 24 01:15:29 PM PST 23 Dec 24 01:18:42 PM PST 23 505782232474 ps
T842 /workspace/coverage/default/44.adc_ctrl_filters_both.1169458284 Dec 24 01:15:26 PM PST 23 Dec 24 01:25:38 PM PST 23 325964948351 ps
T843 /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2073326189 Dec 24 01:14:42 PM PST 23 Dec 24 01:16:09 PM PST 23 165448875011 ps
T844 /workspace/coverage/default/41.adc_ctrl_alert_test.1140817033 Dec 24 01:15:17 PM PST 23 Dec 24 01:15:43 PM PST 23 324429542 ps
T845 /workspace/coverage/default/43.adc_ctrl_poweron_counter.3686222205 Dec 24 01:15:11 PM PST 23 Dec 24 01:15:36 PM PST 23 4348891667 ps
T846 /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4075223871 Dec 24 01:14:57 PM PST 23 Dec 24 01:35:23 PM PST 23 496019416119 ps
T332 /workspace/coverage/default/18.adc_ctrl_filters_both.1629887186 Dec 24 01:14:50 PM PST 23 Dec 24 01:27:32 PM PST 23 334919076572 ps
T337 /workspace/coverage/default/19.adc_ctrl_filters_both.1883956000 Dec 24 01:14:47 PM PST 23 Dec 24 01:24:16 PM PST 23 482962974427 ps
T847 /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1726199139 Dec 24 01:14:09 PM PST 23 Dec 24 01:15:56 PM PST 23 168261430535 ps
T848 /workspace/coverage/default/0.adc_ctrl_smoke.481850979 Dec 24 01:14:03 PM PST 23 Dec 24 01:14:26 PM PST 23 5928411432 ps
T849 /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3042038842 Dec 24 01:14:53 PM PST 23 Dec 24 01:33:34 PM PST 23 494524246824 ps
T153 /workspace/coverage/default/8.adc_ctrl_filters_polled.399116013 Dec 24 01:14:00 PM PST 23 Dec 24 01:15:20 PM PST 23 492516788091 ps
T850 /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.4155303098 Dec 24 01:14:32 PM PST 23 Dec 24 01:18:18 PM PST 23 275165575974 ps
T851 /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2560288765 Dec 24 01:15:20 PM PST 23 Dec 24 01:20:58 PM PST 23 320042923204 ps
T852 /workspace/coverage/default/0.adc_ctrl_poweron_counter.3448431547 Dec 24 01:14:10 PM PST 23 Dec 24 01:14:27 PM PST 23 3292256677 ps
T853 /workspace/coverage/default/30.adc_ctrl_clock_gating.338125083 Dec 24 01:14:49 PM PST 23 Dec 24 01:15:22 PM PST 23 161483872699 ps
T854 /workspace/coverage/default/12.adc_ctrl_poweron_counter.3985515738 Dec 24 01:14:22 PM PST 23 Dec 24 01:14:37 PM PST 23 2928317353 ps
T855 /workspace/coverage/default/3.adc_ctrl_lowpower_counter.204858199 Dec 24 01:14:00 PM PST 23 Dec 24 01:14:25 PM PST 23 24898940037 ps
T856 /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1196955903 Dec 24 01:14:13 PM PST 23 Dec 24 01:15:27 PM PST 23 93004298329 ps
T857 /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2085388672 Dec 24 01:15:23 PM PST 23 Dec 24 01:20:00 PM PST 23 489536781618 ps
T858 /workspace/coverage/default/36.adc_ctrl_stress_all.939977455 Dec 24 01:14:57 PM PST 23 Dec 24 01:21:59 PM PST 23 329868545854 ps
T859 /workspace/coverage/default/1.adc_ctrl_stress_all.1392201497 Dec 24 01:13:55 PM PST 23 Dec 24 01:18:35 PM PST 23 102265168903 ps
T860 /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2009277117 Dec 24 01:14:00 PM PST 23 Dec 24 01:33:19 PM PST 23 484251894709 ps
T861 /workspace/coverage/default/28.adc_ctrl_clock_gating.672671357 Dec 24 01:14:50 PM PST 23 Dec 24 01:30:44 PM PST 23 501612619423 ps
T862 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2942718362 Dec 24 12:30:06 PM PST 23 Dec 24 12:30:44 PM PST 23 4374076236 ps
T863 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2506415632 Dec 24 12:27:59 PM PST 23 Dec 24 12:28:15 PM PST 23 535787666 ps
T864 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.602910566 Dec 24 12:27:56 PM PST 23 Dec 24 12:28:17 PM PST 23 2465490146 ps
T865 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1477944414 Dec 24 12:28:37 PM PST 23 Dec 24 12:28:44 PM PST 23 376520777 ps
T866 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3847942454 Dec 24 12:28:41 PM PST 23 Dec 24 12:28:50 PM PST 23 509713575 ps
T867 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1204995189 Dec 24 12:28:10 PM PST 23 Dec 24 12:28:36 PM PST 23 4072920298 ps
T868 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3105361038 Dec 24 12:28:49 PM PST 23 Dec 24 12:29:10 PM PST 23 4004696758 ps
T869 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2494679072 Dec 24 12:29:37 PM PST 23 Dec 24 12:29:56 PM PST 23 564143503 ps
T870 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2757557938 Dec 24 12:28:46 PM PST 23 Dec 24 12:28:55 PM PST 23 1178356436 ps
T871 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.765257120 Dec 24 12:28:56 PM PST 23 Dec 24 12:29:32 PM PST 23 26301913811 ps
T872 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3239495046 Dec 24 12:28:47 PM PST 23 Dec 24 12:28:57 PM PST 23 409772373 ps
T873 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2092898266 Dec 24 12:30:24 PM PST 23 Dec 24 12:30:49 PM PST 23 798081292 ps
T874 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3857336590 Dec 24 12:28:50 PM PST 23 Dec 24 12:29:01 PM PST 23 504799299 ps
T875 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1903636275 Dec 24 12:29:36 PM PST 23 Dec 24 12:29:51 PM PST 23 328083289 ps
T876 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.88670233 Dec 24 12:28:36 PM PST 23 Dec 24 12:28:45 PM PST 23 1410184758 ps
T877 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3452540953 Dec 24 12:29:39 PM PST 23 Dec 24 12:30:05 PM PST 23 508016854 ps
T878 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3638850150 Dec 24 12:28:04 PM PST 23 Dec 24 12:28:23 PM PST 23 4293550998 ps
T879 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2808630649 Dec 24 12:28:27 PM PST 23 Dec 24 12:28:41 PM PST 23 1105611454 ps
T880 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.849459071 Dec 24 12:28:40 PM PST 23 Dec 24 12:28:49 PM PST 23 368029062 ps
T881 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1638232887 Dec 24 12:29:27 PM PST 23 Dec 24 12:29:41 PM PST 23 434807616 ps
T882 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3177210427 Dec 24 12:29:27 PM PST 23 Dec 24 12:29:43 PM PST 23 8660974331 ps
T883 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1360089743 Dec 24 12:29:31 PM PST 23 Dec 24 12:29:44 PM PST 23 520470482 ps
T884 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2118530697 Dec 24 12:28:36 PM PST 23 Dec 24 12:28:44 PM PST 23 542911897 ps
T885 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1462216583 Dec 24 12:29:30 PM PST 23 Dec 24 12:29:52 PM PST 23 4080735996 ps
T886 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2467394364 Dec 24 12:28:30 PM PST 23 Dec 24 12:28:41 PM PST 23 4940424394 ps
T887 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2870349255 Dec 24 12:30:03 PM PST 23 Dec 24 12:30:30 PM PST 23 472137812 ps
T888 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2905964584 Dec 24 12:28:47 PM PST 23 Dec 24 12:29:09 PM PST 23 4815936006 ps
T889 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.522328609 Dec 24 12:28:31 PM PST 23 Dec 24 12:28:40 PM PST 23 474612361 ps
T355 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3222885297 Dec 24 12:29:13 PM PST 23 Dec 24 12:29:40 PM PST 23 9090475914 ps
T890 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.954774491 Dec 24 12:29:54 PM PST 23 Dec 24 12:30:20 PM PST 23 545777787 ps
T356 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1288830318 Dec 24 12:28:40 PM PST 23 Dec 24 12:28:54 PM PST 23 8690564058 ps
T891 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2123118917 Dec 24 12:30:03 PM PST 23 Dec 24 12:30:39 PM PST 23 4993833392 ps
T892 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2313426305 Dec 24 12:28:04 PM PST 23 Dec 24 12:28:17 PM PST 23 388592171 ps
T893 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3366330357 Dec 24 12:28:30 PM PST 23 Dec 24 12:28:49 PM PST 23 4402801195 ps
T894 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3068795083 Dec 24 12:28:08 PM PST 23 Dec 24 12:28:23 PM PST 23 328868481 ps
T895 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.608583488 Dec 24 12:30:02 PM PST 23 Dec 24 12:30:30 PM PST 23 475025775 ps
T896 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4013471252 Dec 24 12:28:44 PM PST 23 Dec 24 12:28:51 PM PST 23 621556680 ps
T897 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.534560254 Dec 24 12:28:08 PM PST 23 Dec 24 12:28:24 PM PST 23 4863930193 ps
T898 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1891340681 Dec 24 12:28:51 PM PST 23 Dec 24 12:29:05 PM PST 23 516350852 ps
T899 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1095277573 Dec 24 12:29:38 PM PST 23 Dec 24 12:29:59 PM PST 23 471157491 ps
T900 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2753086982 Dec 24 12:28:44 PM PST 23 Dec 24 12:28:51 PM PST 23 535466765 ps
T901 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3471790819 Dec 24 12:28:48 PM PST 23 Dec 24 12:29:15 PM PST 23 26974854119 ps
T902 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2125976352 Dec 24 12:28:39 PM PST 23 Dec 24 12:28:47 PM PST 23 516593344 ps
T903 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.392622754 Dec 24 12:30:23 PM PST 23 Dec 24 12:30:47 PM PST 23 502180633 ps
T904 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.163080030 Dec 24 12:28:04 PM PST 23 Dec 24 12:28:38 PM PST 23 8424377017 ps
T905 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.866009430 Dec 24 12:29:47 PM PST 23 Dec 24 12:30:13 PM PST 23 495956047 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3644065483 Dec 24 12:29:40 PM PST 23 Dec 24 12:30:10 PM PST 23 4922898423 ps
T907 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1905461264 Dec 24 12:28:27 PM PST 23 Dec 24 12:28:36 PM PST 23 531884926 ps
T908 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3494456548 Dec 24 12:28:58 PM PST 23 Dec 24 12:29:11 PM PST 23 562407782 ps
T909 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4032759623 Dec 24 12:27:56 PM PST 23 Dec 24 12:28:10 PM PST 23 425769559 ps
T910 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4243636197 Dec 24 12:28:44 PM PST 23 Dec 24 12:29:11 PM PST 23 7481695131 ps
T911 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2684812989 Dec 24 12:28:29 PM PST 23 Dec 24 12:28:39 PM PST 23 2738476090 ps
T912 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2957167497 Dec 24 12:29:13 PM PST 23 Dec 24 12:29:18 PM PST 23 418297899 ps

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1709884000
Short name T5
Test name
Test status
Simulation time 455876821 ps
CPU time 0.86 seconds
Started Dec 24 12:29:30 PM PST 23
Finished Dec 24 12:29:42 PM PST 23
Peak memory 200356 kb
Host smart-cb1d68dd-7f4b-496a-9632-a5610f488c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709884000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1709884000
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.518303005
Short name T8
Test name
Test status
Simulation time 709631564 ps
CPU time 0.93 seconds
Started Dec 24 12:28:46 PM PST 23
Finished Dec 24 12:28:55 PM PST 23
Peak memory 200528 kb
Host smart-8ebefee9-795c-4eb5-9a46-583597a7f96c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518303005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.518303005
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1154425485
Short name T14
Test name
Test status
Simulation time 509061477366 ps
CPU time 329.53 seconds
Started Dec 24 01:15:05 PM PST 23
Finished Dec 24 01:20:59 PM PST 23
Peak memory 200940 kb
Host smart-d4e60ab6-193a-4110-9d32-d394b2c5f8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154425485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1154425485
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.319072907
Short name T82
Test name
Test status
Simulation time 663649735520 ps
CPU time 409.89 seconds
Started Dec 24 01:15:09 PM PST 23
Finished Dec 24 01:22:21 PM PST 23
Peak memory 200852 kb
Host smart-4caeb9ca-ef0b-4aa4-a60e-56c874a5fd76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319072907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
319072907
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4222003847
Short name T116
Test name
Test status
Simulation time 498350529332 ps
CPU time 1027.15 seconds
Started Dec 24 01:14:04 PM PST 23
Finished Dec 24 01:31:30 PM PST 23
Peak memory 200860 kb
Host smart-c4307e87-48e6-487d-a406-925604fdb811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222003847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4222003847
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.617569222
Short name T25
Test name
Test status
Simulation time 588607933 ps
CPU time 1.59 seconds
Started Dec 24 12:29:34 PM PST 23
Finished Dec 24 12:29:50 PM PST 23
Peak memory 200748 kb
Host smart-3ee26646-4a07-4b65-9106-6e06a7035d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617569222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.617569222
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3829052530
Short name T90
Test name
Test status
Simulation time 486385100066 ps
CPU time 430.03 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:22:32 PM PST 23
Peak memory 201284 kb
Host smart-5bea1b69-7495-463e-8c4a-72a3d477ba15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829052530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3829052530
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4282830023
Short name T100
Test name
Test status
Simulation time 486466343366 ps
CPU time 1160.33 seconds
Started Dec 24 01:15:07 PM PST 23
Finished Dec 24 01:34:50 PM PST 23
Peak memory 200932 kb
Host smart-9936debb-35f8-40e9-85b6-38adbb294700
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282830023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4282830023
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3841254246
Short name T93
Test name
Test status
Simulation time 480961042843 ps
CPU time 909.7 seconds
Started Dec 24 01:15:25 PM PST 23
Finished Dec 24 01:30:58 PM PST 23
Peak memory 200816 kb
Host smart-2b10a5c5-568e-4925-8412-7ffdf6794a4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841254246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3841254246
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.686195628
Short name T89
Test name
Test status
Simulation time 502899586684 ps
CPU time 460.25 seconds
Started Dec 24 01:15:06 PM PST 23
Finished Dec 24 01:23:10 PM PST 23
Peak memory 200900 kb
Host smart-6985e81f-9576-4da8-8c5c-b9b7e53638de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686195628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.686195628
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2107058305
Short name T112
Test name
Test status
Simulation time 498545618354 ps
CPU time 1112.82 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:33:46 PM PST 23
Peak memory 200876 kb
Host smart-36b8591d-2b3b-47f5-b606-867e2a97562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107058305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2107058305
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2645345128
Short name T66
Test name
Test status
Simulation time 4139352111 ps
CPU time 3.93 seconds
Started Dec 24 12:28:11 PM PST 23
Finished Dec 24 12:28:30 PM PST 23
Peak memory 200660 kb
Host smart-604ea5fb-7117-4caa-b6cc-1bf9ffde07e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645345128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2645345128
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.660314719
Short name T103
Test name
Test status
Simulation time 484631040889 ps
CPU time 79.18 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:16:46 PM PST 23
Peak memory 200952 kb
Host smart-f588606f-8964-4328-8223-eaf3e0b97e3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660314719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.660314719
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3058002987
Short name T224
Test name
Test status
Simulation time 496924672174 ps
CPU time 1120.49 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:33:43 PM PST 23
Peak memory 200928 kb
Host smart-d5f7988a-c235-4f65-9084-e33dd2f7da9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058002987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3058002987
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3904273090
Short name T171
Test name
Test status
Simulation time 497375205735 ps
CPU time 290.38 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:20:09 PM PST 23
Peak memory 200940 kb
Host smart-cdb022dd-756b-4b29-b417-5e1ce499c127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904273090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3904273090
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.204169258
Short name T3
Test name
Test status
Simulation time 2335437055 ps
CPU time 2.28 seconds
Started Dec 24 12:29:32 PM PST 23
Finished Dec 24 12:29:46 PM PST 23
Peak memory 200544 kb
Host smart-9b612478-0b69-4f09-b3c9-90c648466604
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204169258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.204169258
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.277176235
Short name T34
Test name
Test status
Simulation time 499586073824 ps
CPU time 152.44 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:16:59 PM PST 23
Peak memory 200860 kb
Host smart-786140fc-2c73-4fb1-84b6-3539a5e23b43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277176235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.277176235
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2726565599
Short name T33
Test name
Test status
Simulation time 482309359549 ps
CPU time 387.59 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:21:18 PM PST 23
Peak memory 200940 kb
Host smart-190e04b1-5dc4-4a8c-a2fb-c4f40294aadc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726565599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2726565599
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3305232740
Short name T233
Test name
Test status
Simulation time 491304944302 ps
CPU time 554.26 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:23:53 PM PST 23
Peak memory 201000 kb
Host smart-dd218d35-c105-4b9e-aa8e-2904099dc7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305232740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3305232740
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3011807164
Short name T85
Test name
Test status
Simulation time 335349146869 ps
CPU time 156.56 seconds
Started Dec 24 01:14:37 PM PST 23
Finished Dec 24 01:17:21 PM PST 23
Peak memory 200844 kb
Host smart-3defef1b-3e4f-4384-8edd-04a9e915a73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011807164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3011807164
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.4270144286
Short name T107
Test name
Test status
Simulation time 493875506630 ps
CPU time 178.63 seconds
Started Dec 24 01:15:29 PM PST 23
Finished Dec 24 01:18:50 PM PST 23
Peak memory 200796 kb
Host smart-34b9a666-763d-4fd9-b538-da7238e301ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270144286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.4270144286
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3055344919
Short name T22
Test name
Test status
Simulation time 456139293151 ps
CPU time 642.68 seconds
Started Dec 24 01:15:09 PM PST 23
Finished Dec 24 01:26:14 PM PST 23
Peak memory 216760 kb
Host smart-efe2c306-41ea-4361-a484-5a61b630e23b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055344919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3055344919
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4212654481
Short name T214
Test name
Test status
Simulation time 148277557900 ps
CPU time 167.5 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:17:15 PM PST 23
Peak memory 209600 kb
Host smart-ed52ae97-cf3e-4af5-bca3-00eb188be9ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212654481 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.4212654481
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2026295538
Short name T185
Test name
Test status
Simulation time 545574933 ps
CPU time 1.06 seconds
Started Dec 24 12:29:22 PM PST 23
Finished Dec 24 12:29:33 PM PST 23
Peak memory 200428 kb
Host smart-9f67fc3d-92ac-4088-8ee7-ab401ed672fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026295538 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2026295538
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2286811432
Short name T47
Test name
Test status
Simulation time 8077389021 ps
CPU time 4.22 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:14:59 PM PST 23
Peak memory 217092 kb
Host smart-8cb88a88-8d72-42b3-9b5c-6e6883ed25c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286811432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2286811432
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1524343491
Short name T91
Test name
Test status
Simulation time 329728926514 ps
CPU time 218.26 seconds
Started Dec 24 01:14:28 PM PST 23
Finished Dec 24 01:18:14 PM PST 23
Peak memory 200952 kb
Host smart-1e46da21-9d7d-43b5-835d-c2639c730343
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524343491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1524343491
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3447269933
Short name T251
Test name
Test status
Simulation time 485063986705 ps
CPU time 423.01 seconds
Started Dec 24 01:14:40 PM PST 23
Finished Dec 24 01:21:50 PM PST 23
Peak memory 200892 kb
Host smart-dfc8f11d-2c80-46e2-9d8e-d2aa533b8201
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447269933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3447269933
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.183589547
Short name T181
Test name
Test status
Simulation time 110630934932 ps
CPU time 91.72 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:16:23 PM PST 23
Peak memory 209168 kb
Host smart-0f1b684c-91e6-4c14-8e32-c5abfc9a128d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183589547 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.183589547
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2131994887
Short name T301
Test name
Test status
Simulation time 127740333494 ps
CPU time 63.04 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:16:49 PM PST 23
Peak memory 209092 kb
Host smart-3f8985c9-b4dc-406d-bd44-041f488cb202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131994887 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2131994887
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1070731073
Short name T83
Test name
Test status
Simulation time 387670753 ps
CPU time 2.28 seconds
Started Dec 24 12:28:35 PM PST 23
Finished Dec 24 12:28:44 PM PST 23
Peak memory 200700 kb
Host smart-ce8b3313-d1f3-4247-85bd-b46ac47516e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070731073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1070731073
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.496353444
Short name T211
Test name
Test status
Simulation time 164618811318 ps
CPU time 99.03 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:16:05 PM PST 23
Peak memory 200908 kb
Host smart-66e2a51e-4d15-4b0f-a64a-081c69f984e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496353444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.496353444
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2787506113
Short name T283
Test name
Test status
Simulation time 441820278846 ps
CPU time 597.24 seconds
Started Dec 24 01:15:06 PM PST 23
Finished Dec 24 01:25:27 PM PST 23
Peak memory 209612 kb
Host smart-9029a305-b02a-4049-9431-5250694cff23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787506113 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2787506113
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.103929096
Short name T264
Test name
Test status
Simulation time 495987819336 ps
CPU time 328.93 seconds
Started Dec 24 01:15:02 PM PST 23
Finished Dec 24 01:20:56 PM PST 23
Peak memory 200908 kb
Host smart-e37c339c-0406-4057-93dd-424091f61c22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103929096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.103929096
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.545572785
Short name T234
Test name
Test status
Simulation time 488344582339 ps
CPU time 1179.28 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:35:16 PM PST 23
Peak memory 200904 kb
Host smart-25673187-3333-4c08-90b3-a4975a07dfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545572785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.545572785
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.272575937
Short name T39
Test name
Test status
Simulation time 184596467449 ps
CPU time 289.22 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:19:47 PM PST 23
Peak memory 209556 kb
Host smart-8b193144-7a50-42dd-8a6c-643f605c482f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272575937 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.272575937
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3335512530
Short name T164
Test name
Test status
Simulation time 496093006280 ps
CPU time 293.64 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:20:17 PM PST 23
Peak memory 200952 kb
Host smart-a42d2e23-1783-4563-9549-26af90e8c29d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335512530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3335512530
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3782554186
Short name T121
Test name
Test status
Simulation time 328290246174 ps
CPU time 203.85 seconds
Started Dec 24 01:15:20 PM PST 23
Finished Dec 24 01:19:09 PM PST 23
Peak memory 199832 kb
Host smart-d1112662-509b-4991-bf5f-ad973b6468ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782554186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3782554186
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1561964216
Short name T249
Test name
Test status
Simulation time 330973016116 ps
CPU time 59.51 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:16:12 PM PST 23
Peak memory 200824 kb
Host smart-14e1a6d5-ae4f-41b8-a344-5db8fc0a2fc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561964216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1561964216
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1690312027
Short name T310
Test name
Test status
Simulation time 495582554442 ps
CPU time 1154.71 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:33:30 PM PST 23
Peak memory 200836 kb
Host smart-6ea71abf-d0ba-4e39-a367-3892f90f41b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690312027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1690312027
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.871530102
Short name T417
Test name
Test status
Simulation time 493272007164 ps
CPU time 1159.81 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:34:10 PM PST 23
Peak memory 200848 kb
Host smart-d04b4ba3-62fd-4277-95ef-fff9ac3ecc4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=871530102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.871530102
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.325628984
Short name T265
Test name
Test status
Simulation time 837678916510 ps
CPU time 1949.5 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:47:29 PM PST 23
Peak memory 200860 kb
Host smart-04fce159-88fc-4674-b5ea-7aed97b88592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325628984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
325628984
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1670874702
Short name T111
Test name
Test status
Simulation time 295212773637 ps
CPU time 461.16 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:22:36 PM PST 23
Peak memory 217692 kb
Host smart-88a0018b-3811-4f3a-9c7e-4a3b80bab6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670874702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1670874702
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3806896897
Short name T182
Test name
Test status
Simulation time 494168799811 ps
CPU time 265.25 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:19:11 PM PST 23
Peak memory 200844 kb
Host smart-0c015f1b-8977-40cc-b772-0953e7988f94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806896897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3806896897
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4125554741
Short name T314
Test name
Test status
Simulation time 232902648705 ps
CPU time 279.7 seconds
Started Dec 24 01:15:05 PM PST 23
Finished Dec 24 01:20:09 PM PST 23
Peak memory 210588 kb
Host smart-6c35e65f-e8d0-420f-8f47-0add6c0ddd22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125554741 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4125554741
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1931813953
Short name T9
Test name
Test status
Simulation time 8789325989 ps
CPU time 22.64 seconds
Started Dec 24 12:28:44 PM PST 23
Finished Dec 24 12:29:14 PM PST 23
Peak memory 200704 kb
Host smart-f8e04082-1ada-45e4-bad0-c1ac8163647a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931813953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1931813953
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2128423468
Short name T241
Test name
Test status
Simulation time 360439181381 ps
CPU time 233.06 seconds
Started Dec 24 01:14:18 PM PST 23
Finished Dec 24 01:18:25 PM PST 23
Peak memory 200868 kb
Host smart-cc787642-11ef-4b85-8a55-d5ffce95699a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128423468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2128423468
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3238306796
Short name T212
Test name
Test status
Simulation time 490262627196 ps
CPU time 579.16 seconds
Started Dec 24 01:14:55 PM PST 23
Finished Dec 24 01:24:58 PM PST 23
Peak memory 200952 kb
Host smart-e0e30af4-9b1e-4e33-b6ba-98b8fa712424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238306796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3238306796
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3471428800
Short name T250
Test name
Test status
Simulation time 330497013686 ps
CPU time 410.39 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:22:13 PM PST 23
Peak memory 200932 kb
Host smart-68218f5d-c6a3-49d4-ab0a-e493e16a05a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471428800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3471428800
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.67411410
Short name T281
Test name
Test status
Simulation time 326006657755 ps
CPU time 193.49 seconds
Started Dec 24 01:15:29 PM PST 23
Finished Dec 24 01:19:05 PM PST 23
Peak memory 200840 kb
Host smart-abd1de66-b900-4b1d-adc6-14ceff5e8c57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67411410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gatin
g.67411410
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1553195105
Short name T357
Test name
Test status
Simulation time 123871864307 ps
CPU time 514.45 seconds
Started Dec 24 01:14:07 PM PST 23
Finished Dec 24 01:22:58 PM PST 23
Peak memory 201280 kb
Host smart-9028c34d-7049-482f-9fab-0dead020671e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553195105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1553195105
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2557448041
Short name T367
Test name
Test status
Simulation time 415043206 ps
CPU time 0.86 seconds
Started Dec 24 12:30:34 PM PST 23
Finished Dec 24 12:31:01 PM PST 23
Peak memory 200380 kb
Host smart-cd951ed3-b316-426e-9720-6ac456fa364c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557448041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2557448041
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1629887186
Short name T332
Test name
Test status
Simulation time 334919076572 ps
CPU time 742.52 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:27:32 PM PST 23
Peak memory 200972 kb
Host smart-e2468256-3168-478e-aedd-6c9582f684a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629887186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1629887186
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4294726426
Short name T308
Test name
Test status
Simulation time 219338379375 ps
CPU time 89.1 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:16:21 PM PST 23
Peak memory 200956 kb
Host smart-ff383476-9cd0-4558-aa65-478d6fcf711c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294726426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4294726426
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1160954328
Short name T321
Test name
Test status
Simulation time 481382847761 ps
CPU time 1145.79 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:33:52 PM PST 23
Peak memory 200856 kb
Host smart-dd161479-c73b-4e77-b663-5b7e0614eccc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160954328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1160954328
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1309438111
Short name T262
Test name
Test status
Simulation time 337741623602 ps
CPU time 483.92 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:23:07 PM PST 23
Peak memory 200868 kb
Host smart-9821f61a-6274-451f-a029-5e12a87c1748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309438111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1309438111
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2371080279
Short name T291
Test name
Test status
Simulation time 360638526556 ps
CPU time 420.87 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:22:11 PM PST 23
Peak memory 200948 kb
Host smart-7c99a5ec-cfed-4a45-92ba-dc788f2b6754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371080279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2371080279
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2853944576
Short name T206
Test name
Test status
Simulation time 477527973595 ps
CPU time 1537.41 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:40:27 PM PST 23
Peak memory 217768 kb
Host smart-ed5de289-e366-47cf-99c9-857ab9d2f861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853944576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2853944576
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2920608261
Short name T230
Test name
Test status
Simulation time 333051958464 ps
CPU time 427.72 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:22:06 PM PST 23
Peak memory 200892 kb
Host smart-83d0d381-f2bd-42ca-9781-e172e206087d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920608261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2920608261
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1176098824
Short name T244
Test name
Test status
Simulation time 334881984450 ps
CPU time 197.39 seconds
Started Dec 24 01:15:10 PM PST 23
Finished Dec 24 01:18:49 PM PST 23
Peak memory 200852 kb
Host smart-95791f4a-e713-4a06-8517-48b1b2097e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176098824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1176098824
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1055605917
Short name T44
Test name
Test status
Simulation time 329853009 ps
CPU time 1 seconds
Started Dec 24 01:14:08 PM PST 23
Finished Dec 24 01:14:26 PM PST 23
Peak memory 200612 kb
Host smart-971f3174-29f4-4fd2-8077-e1135d0a6c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055605917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1055605917
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2658237332
Short name T279
Test name
Test status
Simulation time 161239551002 ps
CPU time 209.63 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:18:48 PM PST 23
Peak memory 200916 kb
Host smart-83249859-27d3-41f2-a1e2-c7718e68a410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658237332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2658237332
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1438225261
Short name T227
Test name
Test status
Simulation time 327584250913 ps
CPU time 402.65 seconds
Started Dec 24 01:15:04 PM PST 23
Finished Dec 24 01:22:12 PM PST 23
Peak memory 200848 kb
Host smart-d9508dbe-f30f-4b03-b7e9-c1c817070231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438225261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1438225261
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1786323687
Short name T23
Test name
Test status
Simulation time 333542867898 ps
CPU time 779.29 seconds
Started Dec 24 01:15:36 PM PST 23
Finished Dec 24 01:28:53 PM PST 23
Peak memory 200776 kb
Host smart-bb86c5c1-53d4-4a72-b667-4351c87d3b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786323687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1786323687
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4125853205
Short name T216
Test name
Test status
Simulation time 171617308592 ps
CPU time 133.82 seconds
Started Dec 24 01:15:30 PM PST 23
Finished Dec 24 01:18:07 PM PST 23
Peak memory 200792 kb
Host smart-b51ffa82-9fc9-4549-8b8a-292f84f45272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125853205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4125853205
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.322825931
Short name T344
Test name
Test status
Simulation time 133090341597 ps
CPU time 251.23 seconds
Started Dec 24 01:14:17 PM PST 23
Finished Dec 24 01:18:42 PM PST 23
Peak memory 209572 kb
Host smart-b059762d-3697-4fd5-9d52-ec65db18496a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322825931 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.322825931
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1128431637
Short name T245
Test name
Test status
Simulation time 330100289746 ps
CPU time 367.74 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:20:34 PM PST 23
Peak memory 200952 kb
Host smart-561804ab-37b2-4c5b-bfdd-17206fb67f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128431637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1128431637
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3306258163
Short name T205
Test name
Test status
Simulation time 141933057031 ps
CPU time 551.76 seconds
Started Dec 24 01:14:15 PM PST 23
Finished Dec 24 01:23:41 PM PST 23
Peak memory 201304 kb
Host smart-ee998824-ce40-4133-b78d-f0641e579004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306258163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3306258163
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1883956000
Short name T337
Test name
Test status
Simulation time 482962974427 ps
CPU time 559.11 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:24:16 PM PST 23
Peak memory 200892 kb
Host smart-b5689ba0-271b-421d-9990-9729272666be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883956000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1883956000
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2058745628
Short name T18
Test name
Test status
Simulation time 336483671646 ps
CPU time 426.97 seconds
Started Dec 24 01:15:14 PM PST 23
Finished Dec 24 01:22:46 PM PST 23
Peak memory 200908 kb
Host smart-0fde27a3-3f36-4fdc-a6fe-b164ee65c3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058745628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2058745628
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.351485421
Short name T232
Test name
Test status
Simulation time 503773687429 ps
CPU time 909.14 seconds
Started Dec 24 01:15:09 PM PST 23
Finished Dec 24 01:30:39 PM PST 23
Peak memory 200864 kb
Host smart-09c089cb-c490-4929-850d-855d0e466e94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351485421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.351485421
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.851749853
Short name T278
Test name
Test status
Simulation time 330760988096 ps
CPU time 143.55 seconds
Started Dec 24 01:15:20 PM PST 23
Finished Dec 24 01:18:08 PM PST 23
Peak memory 199944 kb
Host smart-4f6d571f-a4d1-4b2a-8b27-2c52954f9f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851749853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.851749853
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3879668816
Short name T196
Test name
Test status
Simulation time 129183232419 ps
CPU time 554.89 seconds
Started Dec 24 01:15:37 PM PST 23
Finished Dec 24 01:25:09 PM PST 23
Peak memory 201336 kb
Host smart-57f02033-b792-4c3b-9f78-edb936965fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879668816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3879668816
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1359209849
Short name T353
Test name
Test status
Simulation time 4134187677 ps
CPU time 6.04 seconds
Started Dec 24 12:28:11 PM PST 23
Finished Dec 24 12:28:32 PM PST 23
Peak memory 200712 kb
Host smart-b11d6776-3bab-4b52-ba10-fb4bafc59f47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359209849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1359209849
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1055563806
Short name T354
Test name
Test status
Simulation time 4409902967 ps
CPU time 6.53 seconds
Started Dec 24 12:28:15 PM PST 23
Finished Dec 24 12:28:34 PM PST 23
Peak memory 200744 kb
Host smart-e2e31a69-4c7c-472c-a926-3705caf4e5da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055563806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1055563806
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4048474723
Short name T297
Test name
Test status
Simulation time 212955195686 ps
CPU time 115.75 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:16:07 PM PST 23
Peak memory 209548 kb
Host smart-0b492b0e-2a99-4dd7-99c3-eeddb6ea8ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048474723 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.4048474723
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2966754633
Short name T346
Test name
Test status
Simulation time 168363240882 ps
CPU time 190.12 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:18:02 PM PST 23
Peak memory 200936 kb
Host smart-dda21983-618a-48be-a9ba-55d7eeb9bfb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966754633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2966754633
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2617461245
Short name T179
Test name
Test status
Simulation time 81710887366 ps
CPU time 314.53 seconds
Started Dec 24 01:14:33 PM PST 23
Finished Dec 24 01:19:55 PM PST 23
Peak memory 201324 kb
Host smart-079affbc-6492-4198-9dc0-bc303a0b369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617461245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2617461245
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3806399385
Short name T305
Test name
Test status
Simulation time 492781528576 ps
CPU time 777.64 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:27:54 PM PST 23
Peak memory 200940 kb
Host smart-b2610b44-a231-48be-a0b5-82e4233150b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806399385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3806399385
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3893220392
Short name T823
Test name
Test status
Simulation time 88959641990 ps
CPU time 467.71 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:23:10 PM PST 23
Peak memory 201288 kb
Host smart-65279185-3974-48bc-ba73-3d8c2119a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893220392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3893220392
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.54216228
Short name T124
Test name
Test status
Simulation time 325621040515 ps
CPU time 322.03 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:19:38 PM PST 23
Peak memory 200960 kb
Host smart-60199353-7325-4eab-82de-cea2b3cde9ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54216228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating
.54216228
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1226670704
Short name T335
Test name
Test status
Simulation time 328617532947 ps
CPU time 198.76 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:18:32 PM PST 23
Peak memory 200940 kb
Host smart-226d96db-8cfe-46cd-9af8-47474da549ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226670704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1226670704
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2510090906
Short name T243
Test name
Test status
Simulation time 325695859072 ps
CPU time 397.45 seconds
Started Dec 24 01:14:31 PM PST 23
Finished Dec 24 01:21:16 PM PST 23
Peak memory 200884 kb
Host smart-f0e923e2-f96b-4f08-87fb-90ef6176f571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510090906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2510090906
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.326199474
Short name T290
Test name
Test status
Simulation time 484810584196 ps
CPU time 1155.45 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:34:14 PM PST 23
Peak memory 200952 kb
Host smart-f7d1942d-91b2-4800-8594-046d147549af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326199474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.326199474
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.605254029
Short name T287
Test name
Test status
Simulation time 494361211767 ps
CPU time 293.33 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:20:15 PM PST 23
Peak memory 200912 kb
Host smart-9d4a9eec-8c1d-435a-a19f-f1abc6b49657
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605254029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.605254029
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1002841864
Short name T318
Test name
Test status
Simulation time 328693688384 ps
CPU time 185.53 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:18:24 PM PST 23
Peak memory 200852 kb
Host smart-a3da8583-4df8-48ea-8928-7e63a6153997
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002841864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1002841864
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.173422470
Short name T391
Test name
Test status
Simulation time 784438963 ps
CPU time 1.92 seconds
Started Dec 24 12:28:43 PM PST 23
Finished Dec 24 12:28:51 PM PST 23
Peak memory 200688 kb
Host smart-6e4f152d-cf92-4d04-a4fe-50a1dd9637c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173422470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.173422470
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3471790819
Short name T901
Test name
Test status
Simulation time 26974854119 ps
CPU time 18.4 seconds
Started Dec 24 12:28:48 PM PST 23
Finished Dec 24 12:29:15 PM PST 23
Peak memory 200808 kb
Host smart-cee5032b-4a7a-4f4d-a7ba-9753257508dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471790819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3471790819
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2757557938
Short name T870
Test name
Test status
Simulation time 1178356436 ps
CPU time 0.93 seconds
Started Dec 24 12:28:46 PM PST 23
Finished Dec 24 12:28:55 PM PST 23
Peak memory 200528 kb
Host smart-c8cffc8b-e32d-4af2-b9f0-c8e7d6dbfcad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757557938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2757557938
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1684708880
Short name T72
Test name
Test status
Simulation time 477177432 ps
CPU time 1.98 seconds
Started Dec 24 12:28:41 PM PST 23
Finished Dec 24 12:28:49 PM PST 23
Peak memory 200456 kb
Host smart-493f106f-d5cc-413e-a152-a699801821f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684708880 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1684708880
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2125976352
Short name T902
Test name
Test status
Simulation time 516593344 ps
CPU time 1.12 seconds
Started Dec 24 12:28:39 PM PST 23
Finished Dec 24 12:28:47 PM PST 23
Peak memory 200616 kb
Host smart-aba97d01-f9c4-40aa-bb17-3bc1bf89abd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125976352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2125976352
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3914738056
Short name T409
Test name
Test status
Simulation time 406997656 ps
CPU time 1.02 seconds
Started Dec 24 12:28:59 PM PST 23
Finished Dec 24 12:29:09 PM PST 23
Peak memory 200212 kb
Host smart-41fa4945-c270-40cb-bdb7-756ea625214e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914738056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3914738056
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3644065483
Short name T906
Test name
Test status
Simulation time 4922898423 ps
CPU time 3.83 seconds
Started Dec 24 12:29:40 PM PST 23
Finished Dec 24 12:30:10 PM PST 23
Peak memory 200804 kb
Host smart-af6214cf-cede-4828-8363-03751a85f5a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644065483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3644065483
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.608583488
Short name T895
Test name
Test status
Simulation time 475025775 ps
CPU time 2.53 seconds
Started Dec 24 12:30:02 PM PST 23
Finished Dec 24 12:30:30 PM PST 23
Peak memory 200772 kb
Host smart-5deb290d-8e42-44a5-8b2e-549f23000619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608583488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.608583488
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1891340681
Short name T898
Test name
Test status
Simulation time 516350852 ps
CPU time 3.27 seconds
Started Dec 24 12:28:51 PM PST 23
Finished Dec 24 12:29:05 PM PST 23
Peak memory 200748 kb
Host smart-87fc0fb2-b978-42de-b68b-d57f5f733088
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891340681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1891340681
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.765257120
Short name T871
Test name
Test status
Simulation time 26301913811 ps
CPU time 26.35 seconds
Started Dec 24 12:28:56 PM PST 23
Finished Dec 24 12:29:32 PM PST 23
Peak memory 200820 kb
Host smart-6e07c4ec-395e-4516-bd61-8f46ad0beb06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765257120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.765257120
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4283891790
Short name T187
Test name
Test status
Simulation time 921002834 ps
CPU time 2.7 seconds
Started Dec 24 12:28:39 PM PST 23
Finished Dec 24 12:28:48 PM PST 23
Peak memory 200536 kb
Host smart-68f5a1f0-82a9-4110-bed0-a47fa8327fb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283891790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.4283891790
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3570293124
Short name T6
Test name
Test status
Simulation time 440650998 ps
CPU time 1.84 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 200572 kb
Host smart-c6991452-1600-4008-abd9-6199dd2793cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570293124 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3570293124
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4032759623
Short name T909
Test name
Test status
Simulation time 425769559 ps
CPU time 1.77 seconds
Started Dec 24 12:27:56 PM PST 23
Finished Dec 24 12:28:10 PM PST 23
Peak memory 199836 kb
Host smart-c44066a6-7d05-4259-8349-7685646665fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032759623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4032759623
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3867526951
Short name T28
Test name
Test status
Simulation time 410268641 ps
CPU time 1.45 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 200208 kb
Host smart-6e3a5424-4d57-4093-81cf-b70f6e52df1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867526951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3867526951
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3105361038
Short name T868
Test name
Test status
Simulation time 4004696758 ps
CPU time 11.45 seconds
Started Dec 24 12:28:49 PM PST 23
Finished Dec 24 12:29:10 PM PST 23
Peak memory 200712 kb
Host smart-ff48b12a-facd-478a-96d9-eca629908f23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105361038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3105361038
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3494456548
Short name T908
Test name
Test status
Simulation time 562407782 ps
CPU time 3.14 seconds
Started Dec 24 12:28:58 PM PST 23
Finished Dec 24 12:29:11 PM PST 23
Peak memory 208928 kb
Host smart-a452acce-edd6-4253-93e7-3a0a6eeb32c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494456548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3494456548
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3764348495
Short name T393
Test name
Test status
Simulation time 4468972299 ps
CPU time 6.88 seconds
Started Dec 24 12:28:02 PM PST 23
Finished Dec 24 12:28:23 PM PST 23
Peak memory 200724 kb
Host smart-e7a1b4a9-a356-4512-9aa5-472cc5950eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764348495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3764348495
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2957167497
Short name T912
Test name
Test status
Simulation time 418297899 ps
CPU time 1.66 seconds
Started Dec 24 12:29:13 PM PST 23
Finished Dec 24 12:29:18 PM PST 23
Peak memory 200544 kb
Host smart-05b2f0ba-f923-419d-9906-6566f7c1c80d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957167497 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2957167497
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2118530697
Short name T884
Test name
Test status
Simulation time 542911897 ps
CPU time 1.94 seconds
Started Dec 24 12:28:36 PM PST 23
Finished Dec 24 12:28:44 PM PST 23
Peak memory 200436 kb
Host smart-39eed0ba-f488-4de7-97ed-a9067d963987
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118530697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2118530697
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.874066178
Short name T402
Test name
Test status
Simulation time 385169175 ps
CPU time 0.85 seconds
Started Dec 24 12:28:57 PM PST 23
Finished Dec 24 12:29:08 PM PST 23
Peak memory 200140 kb
Host smart-a9467ae4-f52d-4f30-bc8c-cd0b0ad1329e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874066178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.874066178
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3029083742
Short name T188
Test name
Test status
Simulation time 4320343880 ps
CPU time 14.98 seconds
Started Dec 24 12:29:28 PM PST 23
Finished Dec 24 12:29:53 PM PST 23
Peak memory 200652 kb
Host smart-f41b11dd-818a-4035-9ded-0fbfb9072ba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029083742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3029083742
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2927772125
Short name T67
Test name
Test status
Simulation time 551860285 ps
CPU time 3.25 seconds
Started Dec 24 12:28:06 PM PST 23
Finished Dec 24 12:28:24 PM PST 23
Peak memory 208928 kb
Host smart-5a1de7b6-6836-4d5b-a175-1960718ec470
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927772125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2927772125
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3638850150
Short name T878
Test name
Test status
Simulation time 4293550998 ps
CPU time 6.15 seconds
Started Dec 24 12:28:04 PM PST 23
Finished Dec 24 12:28:23 PM PST 23
Peak memory 200692 kb
Host smart-200259e5-b340-4554-b278-fc1a7e6f3422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638850150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3638850150
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1124344790
Short name T26
Test name
Test status
Simulation time 560607180 ps
CPU time 2.04 seconds
Started Dec 24 12:28:44 PM PST 23
Finished Dec 24 12:28:59 PM PST 23
Peak memory 200592 kb
Host smart-5d1c9335-18ee-47b3-ac95-8f7d5b1bf99d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124344790 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1124344790
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3847942454
Short name T866
Test name
Test status
Simulation time 509713575 ps
CPU time 0.97 seconds
Started Dec 24 12:28:41 PM PST 23
Finished Dec 24 12:28:50 PM PST 23
Peak memory 200220 kb
Host smart-46c62a9a-d021-4f4f-8a47-96d6e3d260cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847942454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3847942454
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1929643168
Short name T186
Test name
Test status
Simulation time 4333384566 ps
CPU time 9.65 seconds
Started Dec 24 12:29:20 PM PST 23
Finished Dec 24 12:29:40 PM PST 23
Peak memory 200716 kb
Host smart-a5e465e1-6c8b-4158-b48f-3df097a58187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929643168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1929643168
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1837267949
Short name T84
Test name
Test status
Simulation time 4790706495 ps
CPU time 4.53 seconds
Started Dec 24 12:29:07 PM PST 23
Finished Dec 24 12:29:16 PM PST 23
Peak memory 200720 kb
Host smart-7d08177d-28c6-4dd9-8f5a-72a2bead27fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837267949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1837267949
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3604317954
Short name T396
Test name
Test status
Simulation time 507916380 ps
CPU time 1.89 seconds
Started Dec 24 12:29:29 PM PST 23
Finished Dec 24 12:29:41 PM PST 23
Peak memory 200572 kb
Host smart-be25b315-9ed1-4106-bfdd-55d1838e73e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604317954 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3604317954
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.575221847
Short name T386
Test name
Test status
Simulation time 447635882 ps
CPU time 0.96 seconds
Started Dec 24 12:29:03 PM PST 23
Finished Dec 24 12:29:10 PM PST 23
Peak memory 200456 kb
Host smart-c568269b-e064-45d2-b769-7fd2a2e1f35c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575221847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.575221847
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3239495046
Short name T872
Test name
Test status
Simulation time 409772373 ps
CPU time 1.53 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:28:57 PM PST 23
Peak memory 200360 kb
Host smart-983ba798-6f01-427c-bee0-48b59b36d974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239495046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3239495046
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3033301555
Short name T2
Test name
Test status
Simulation time 2195732872 ps
CPU time 2.01 seconds
Started Dec 24 12:28:44 PM PST 23
Finished Dec 24 12:28:52 PM PST 23
Peak memory 200572 kb
Host smart-72af4c93-cc07-49d0-a3d6-8693fc516f37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033301555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3033301555
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.866009430
Short name T905
Test name
Test status
Simulation time 495956047 ps
CPU time 2.7 seconds
Started Dec 24 12:29:47 PM PST 23
Finished Dec 24 12:30:13 PM PST 23
Peak memory 200444 kb
Host smart-891b492c-caba-43ba-ae92-ecb084ab1905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866009430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.866009430
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3503881422
Short name T189
Test name
Test status
Simulation time 413317756 ps
CPU time 1.82 seconds
Started Dec 24 12:29:58 PM PST 23
Finished Dec 24 12:30:26 PM PST 23
Peak memory 200492 kb
Host smart-6c941563-48f6-4bc5-8b3a-2d7ac8dfeeea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503881422 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3503881422
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.214682738
Short name T31
Test name
Test status
Simulation time 454472860 ps
CPU time 1.72 seconds
Started Dec 24 12:28:49 PM PST 23
Finished Dec 24 12:29:01 PM PST 23
Peak memory 200356 kb
Host smart-659e2ccd-1804-4361-8eed-f6af53dd1a7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214682738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.214682738
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1550760459
Short name T411
Test name
Test status
Simulation time 494114197 ps
CPU time 1.22 seconds
Started Dec 24 12:30:20 PM PST 23
Finished Dec 24 12:30:43 PM PST 23
Peak memory 200144 kb
Host smart-4bbc647c-a3a9-4f52-8250-172303e50b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550760459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1550760459
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2123118917
Short name T891
Test name
Test status
Simulation time 4993833392 ps
CPU time 10.14 seconds
Started Dec 24 12:30:03 PM PST 23
Finished Dec 24 12:30:39 PM PST 23
Peak memory 200620 kb
Host smart-2d6f251a-9d56-47d6-b2a2-2c21522c657b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123118917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2123118917
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1694054435
Short name T414
Test name
Test status
Simulation time 677795559 ps
CPU time 2.12 seconds
Started Dec 24 12:29:47 PM PST 23
Finished Dec 24 12:30:11 PM PST 23
Peak memory 200696 kb
Host smart-e07e593a-45b8-4789-a246-68c8fbcd97ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694054435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1694054435
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1204995189
Short name T867
Test name
Test status
Simulation time 4072920298 ps
CPU time 11.18 seconds
Started Dec 24 12:28:10 PM PST 23
Finished Dec 24 12:28:36 PM PST 23
Peak memory 200724 kb
Host smart-212de470-4709-4680-8fbd-6203a0c4ae2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204995189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1204995189
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.388837085
Short name T32
Test name
Test status
Simulation time 633707530 ps
CPU time 0.97 seconds
Started Dec 24 12:28:42 PM PST 23
Finished Dec 24 12:28:49 PM PST 23
Peak memory 200492 kb
Host smart-55f45408-49d6-4f0e-a867-b24eb0b7733d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388837085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.388837085
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1231758422
Short name T408
Test name
Test status
Simulation time 284653354 ps
CPU time 0.98 seconds
Started Dec 24 12:29:47 PM PST 23
Finished Dec 24 12:30:10 PM PST 23
Peak memory 200164 kb
Host smart-18547459-538b-48af-85ad-daf7395b903c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231758422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1231758422
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2920372147
Short name T384
Test name
Test status
Simulation time 2896365368 ps
CPU time 1.8 seconds
Started Dec 24 12:28:39 PM PST 23
Finished Dec 24 12:28:46 PM PST 23
Peak memory 200472 kb
Host smart-ba1fd7d0-1bfb-42a2-83ad-362a2ec31ec1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920372147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2920372147
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1258743680
Short name T29
Test name
Test status
Simulation time 700481631 ps
CPU time 3.04 seconds
Started Dec 24 12:29:43 PM PST 23
Finished Dec 24 12:30:06 PM PST 23
Peak memory 217072 kb
Host smart-9ef1c2ee-bd21-402a-8b9c-43e431f3f789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258743680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1258743680
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3857336590
Short name T874
Test name
Test status
Simulation time 504799299 ps
CPU time 1.36 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:01 PM PST 23
Peak memory 200672 kb
Host smart-9b6d4d7b-7501-46ca-9f22-28167625bcfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857336590 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3857336590
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2288843995
Short name T77
Test name
Test status
Simulation time 488277289 ps
CPU time 0.97 seconds
Started Dec 24 12:28:42 PM PST 23
Finished Dec 24 12:28:49 PM PST 23
Peak memory 200508 kb
Host smart-7052f4ef-6733-4999-8153-732017db688e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288843995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2288843995
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.25822315
Short name T193
Test name
Test status
Simulation time 540486711 ps
CPU time 0.94 seconds
Started Dec 24 12:29:35 PM PST 23
Finished Dec 24 12:29:50 PM PST 23
Peak memory 200212 kb
Host smart-f4dd6aa4-98f8-4ddc-b4b1-aee76f63bc41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25822315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.25822315
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.684118977
Short name T190
Test name
Test status
Simulation time 4747460489 ps
CPU time 4.46 seconds
Started Dec 24 12:30:00 PM PST 23
Finished Dec 24 12:30:31 PM PST 23
Peak memory 200784 kb
Host smart-9df6e4ee-6090-442e-aea6-81727a7c56fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684118977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.684118977
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1638232887
Short name T881
Test name
Test status
Simulation time 434807616 ps
CPU time 1.99 seconds
Started Dec 24 12:29:27 PM PST 23
Finished Dec 24 12:29:41 PM PST 23
Peak memory 200724 kb
Host smart-0b2cb451-baeb-47ca-b072-41a949e3252a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638232887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1638232887
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1288830318
Short name T356
Test name
Test status
Simulation time 8690564058 ps
CPU time 7.14 seconds
Started Dec 24 12:28:40 PM PST 23
Finished Dec 24 12:28:54 PM PST 23
Peak memory 200644 kb
Host smart-08110022-1137-488c-b576-c528ee2d1add
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288830318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1288830318
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2650663119
Short name T385
Test name
Test status
Simulation time 542649402 ps
CPU time 2.06 seconds
Started Dec 24 12:29:17 PM PST 23
Finished Dec 24 12:29:28 PM PST 23
Peak memory 200584 kb
Host smart-237602c9-55ec-4a04-b550-ecf82e3996af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650663119 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2650663119
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2753086982
Short name T900
Test name
Test status
Simulation time 535466765 ps
CPU time 1.12 seconds
Started Dec 24 12:28:44 PM PST 23
Finished Dec 24 12:28:51 PM PST 23
Peak memory 200460 kb
Host smart-9336f5d9-de0c-4952-89f4-f841f00a5138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753086982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2753086982
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.279879329
Short name T372
Test name
Test status
Simulation time 397033080 ps
CPU time 0.7 seconds
Started Dec 24 12:28:43 PM PST 23
Finished Dec 24 12:28:51 PM PST 23
Peak memory 200064 kb
Host smart-d522077a-8a08-4ffe-9827-096224424764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279879329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.279879329
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1462216583
Short name T885
Test name
Test status
Simulation time 4080735996 ps
CPU time 10.45 seconds
Started Dec 24 12:29:30 PM PST 23
Finished Dec 24 12:29:52 PM PST 23
Peak memory 200600 kb
Host smart-555deed2-20d5-445f-a3a1-22a131f4f72b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462216583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1462216583
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.849459071
Short name T880
Test name
Test status
Simulation time 368029062 ps
CPU time 3.23 seconds
Started Dec 24 12:28:40 PM PST 23
Finished Dec 24 12:28:49 PM PST 23
Peak memory 217096 kb
Host smart-9d88de3d-4fbd-4c1f-b5f9-d5535e188680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849459071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.849459071
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3177210427
Short name T882
Test name
Test status
Simulation time 8660974331 ps
CPU time 7.46 seconds
Started Dec 24 12:29:27 PM PST 23
Finished Dec 24 12:29:43 PM PST 23
Peak memory 200736 kb
Host smart-ba837d8d-52cb-4026-9513-4584c27ba12b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177210427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3177210427
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.639443371
Short name T184
Test name
Test status
Simulation time 396369179 ps
CPU time 1.48 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:28:57 PM PST 23
Peak memory 200524 kb
Host smart-ed463198-c92f-4848-ba32-c107a029a0f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639443371 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.639443371
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1119976588
Short name T10
Test name
Test status
Simulation time 353586713 ps
CPU time 1.59 seconds
Started Dec 24 12:28:56 PM PST 23
Finished Dec 24 12:29:08 PM PST 23
Peak memory 200472 kb
Host smart-da274c5a-9b8d-436d-9255-a6a3362d9aea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119976588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1119976588
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2610324589
Short name T394
Test name
Test status
Simulation time 350435825 ps
CPU time 0.83 seconds
Started Dec 24 12:28:04 PM PST 23
Finished Dec 24 12:28:18 PM PST 23
Peak memory 200304 kb
Host smart-37a47130-a525-4073-a842-96c30f9a3103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610324589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2610324589
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4131148606
Short name T81
Test name
Test status
Simulation time 2478187461 ps
CPU time 1.38 seconds
Started Dec 24 12:29:02 PM PST 23
Finished Dec 24 12:29:11 PM PST 23
Peak memory 200592 kb
Host smart-46969f84-f888-484d-a93a-f642c9391635
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131148606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.4131148606
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4257186525
Short name T63
Test name
Test status
Simulation time 527245409 ps
CPU time 2.17 seconds
Started Dec 24 12:28:49 PM PST 23
Finished Dec 24 12:29:02 PM PST 23
Peak memory 200760 kb
Host smart-29a4588c-3615-4257-9680-d3dd14af8b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257186525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.4257186525
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3222885297
Short name T355
Test name
Test status
Simulation time 9090475914 ps
CPU time 23.39 seconds
Started Dec 24 12:29:13 PM PST 23
Finished Dec 24 12:29:40 PM PST 23
Peak memory 200788 kb
Host smart-38dfb8d7-1957-4eda-8771-f35d56078ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222885297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3222885297
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.406345426
Short name T1
Test name
Test status
Simulation time 481600895 ps
CPU time 0.9 seconds
Started Dec 24 12:29:36 PM PST 23
Finished Dec 24 12:29:52 PM PST 23
Peak memory 200456 kb
Host smart-59f3f70c-1e5b-4dec-96e8-65a1998c8315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406345426 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.406345426
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1399326056
Short name T68
Test name
Test status
Simulation time 412963041 ps
CPU time 1.33 seconds
Started Dec 24 12:28:44 PM PST 23
Finished Dec 24 12:28:53 PM PST 23
Peak memory 200444 kb
Host smart-1cb20652-9882-44ac-a44a-d273f0bbea44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399326056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1399326056
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1004403405
Short name T403
Test name
Test status
Simulation time 380849056 ps
CPU time 1.41 seconds
Started Dec 24 12:28:05 PM PST 23
Finished Dec 24 12:28:19 PM PST 23
Peak memory 200140 kb
Host smart-44d07d58-3d6e-45be-bb33-9ec36e8d7869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004403405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1004403405
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2905964584
Short name T888
Test name
Test status
Simulation time 4815936006 ps
CPU time 10.69 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:29:09 PM PST 23
Peak memory 200820 kb
Host smart-7f2ece6a-ac73-45a2-a03c-5972b56047d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905964584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2905964584
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1954311048
Short name T62
Test name
Test status
Simulation time 1072987187 ps
CPU time 1.24 seconds
Started Dec 24 12:29:00 PM PST 23
Finished Dec 24 12:29:10 PM PST 23
Peak memory 200576 kb
Host smart-2a0d2851-c28a-48d6-8f9e-9634e36e4d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954311048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1954311048
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2942718362
Short name T862
Test name
Test status
Simulation time 4374076236 ps
CPU time 12.83 seconds
Started Dec 24 12:30:06 PM PST 23
Finished Dec 24 12:30:44 PM PST 23
Peak memory 200640 kb
Host smart-e7cc6b4f-1bf0-4db6-8ec6-6deb9d76e3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942718362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2942718362
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3826466479
Short name T388
Test name
Test status
Simulation time 368651163 ps
CPU time 1.19 seconds
Started Dec 24 12:29:49 PM PST 23
Finished Dec 24 12:30:14 PM PST 23
Peak memory 200512 kb
Host smart-0345407f-d89c-4948-9b3b-7561d3a9a066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826466479 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3826466479
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1345065622
Short name T7
Test name
Test status
Simulation time 392135897 ps
CPU time 1.17 seconds
Started Dec 24 12:29:59 PM PST 23
Finished Dec 24 12:30:27 PM PST 23
Peak memory 200516 kb
Host smart-fc14c76d-a9ad-491f-a805-4ac54aacb872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345065622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1345065622
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4013471252
Short name T896
Test name
Test status
Simulation time 621556680 ps
CPU time 0.74 seconds
Started Dec 24 12:28:44 PM PST 23
Finished Dec 24 12:28:51 PM PST 23
Peak memory 200140 kb
Host smart-4baf8cc3-cd71-45ba-9190-16b8442d219b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013471252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.4013471252
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2807553527
Short name T71
Test name
Test status
Simulation time 2152423669 ps
CPU time 4.29 seconds
Started Dec 24 12:29:43 PM PST 23
Finished Dec 24 12:30:07 PM PST 23
Peak memory 200440 kb
Host smart-90bf005d-28b7-4ea8-b240-b4da2429d7bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807553527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2807553527
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.468871609
Short name T406
Test name
Test status
Simulation time 567882296 ps
CPU time 1.76 seconds
Started Dec 24 12:28:41 PM PST 23
Finished Dec 24 12:28:56 PM PST 23
Peak memory 208884 kb
Host smart-39d95583-23d6-48b9-b082-4793dc3d1504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468871609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.468871609
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1862229939
Short name T60
Test name
Test status
Simulation time 8354701036 ps
CPU time 12.48 seconds
Started Dec 24 12:28:43 PM PST 23
Finished Dec 24 12:29:02 PM PST 23
Peak memory 200728 kb
Host smart-e419ef64-e91c-4dbd-bc20-2ce7e25cff06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862229939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1862229939
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1956763009
Short name T79
Test name
Test status
Simulation time 970509280 ps
CPU time 5.26 seconds
Started Dec 24 12:28:30 PM PST 23
Finished Dec 24 12:28:42 PM PST 23
Peak memory 200648 kb
Host smart-794c98d3-930c-41a4-bdb7-28d465726ed7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956763009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1956763009
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.452418661
Short name T412
Test name
Test status
Simulation time 11536163728 ps
CPU time 12.82 seconds
Started Dec 24 12:28:02 PM PST 23
Finished Dec 24 12:28:28 PM PST 23
Peak memory 200728 kb
Host smart-2e1a8eb3-da4a-4f72-8817-a7a1b64c4849
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452418661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.452418661
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3699904438
Short name T80
Test name
Test status
Simulation time 899344224 ps
CPU time 0.83 seconds
Started Dec 24 12:28:07 PM PST 23
Finished Dec 24 12:28:22 PM PST 23
Peak memory 200420 kb
Host smart-59a782de-8cdc-436f-94e7-640fcc8e8629
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699904438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3699904438
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.142692346
Short name T27
Test name
Test status
Simulation time 598046642 ps
CPU time 1.45 seconds
Started Dec 24 12:27:59 PM PST 23
Finished Dec 24 12:28:13 PM PST 23
Peak memory 200408 kb
Host smart-2cfa65eb-a761-4af8-ab34-82cdd736eb43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142692346 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.142692346
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2954502861
Short name T78
Test name
Test status
Simulation time 380381543 ps
CPU time 1.55 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:22 PM PST 23
Peak memory 200444 kb
Host smart-7b7ddb0b-1932-4571-847e-06230aee1138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954502861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2954502861
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1914870136
Short name T404
Test name
Test status
Simulation time 431900263 ps
CPU time 0.87 seconds
Started Dec 24 12:30:11 PM PST 23
Finished Dec 24 12:30:36 PM PST 23
Peak memory 200164 kb
Host smart-c28ba24a-5292-410e-8f80-3931b8a524e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914870136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1914870136
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.602910566
Short name T864
Test name
Test status
Simulation time 2465490146 ps
CPU time 7.8 seconds
Started Dec 24 12:27:56 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 200492 kb
Host smart-382f01de-61aa-4495-89b7-7c5c87aeb75f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602910566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.602910566
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1653666705
Short name T410
Test name
Test status
Simulation time 490411353 ps
CPU time 2.25 seconds
Started Dec 24 12:28:41 PM PST 23
Finished Dec 24 12:28:49 PM PST 23
Peak memory 201080 kb
Host smart-3d634b1f-0f79-40f4-b647-8232b4ac4657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653666705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1653666705
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2275331564
Short name T398
Test name
Test status
Simulation time 7530220841 ps
CPU time 20.06 seconds
Started Dec 24 12:27:56 PM PST 23
Finished Dec 24 12:28:28 PM PST 23
Peak memory 199704 kb
Host smart-77186fe2-8de1-4d1b-bdb7-af79e444d7b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275331564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2275331564
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4026057614
Short name T371
Test name
Test status
Simulation time 343489780 ps
CPU time 1.03 seconds
Started Dec 24 12:28:53 PM PST 23
Finished Dec 24 12:29:05 PM PST 23
Peak memory 200148 kb
Host smart-a79ba33e-868f-46ca-a25f-e29f0e27866e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026057614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4026057614
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1903636275
Short name T875
Test name
Test status
Simulation time 328083289 ps
CPU time 0.78 seconds
Started Dec 24 12:29:36 PM PST 23
Finished Dec 24 12:29:51 PM PST 23
Peak memory 200176 kb
Host smart-1b671cb2-ee26-4763-ba03-6db6faeaa214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903636275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1903636275
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1912505736
Short name T36
Test name
Test status
Simulation time 481794527 ps
CPU time 0.93 seconds
Started Dec 24 12:29:24 PM PST 23
Finished Dec 24 12:29:34 PM PST 23
Peak memory 200172 kb
Host smart-696fc1d3-2e23-433a-a01a-7435dee689e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912505736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1912505736
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2593096194
Short name T374
Test name
Test status
Simulation time 375489054 ps
CPU time 0.83 seconds
Started Dec 24 12:29:22 PM PST 23
Finished Dec 24 12:29:33 PM PST 23
Peak memory 200096 kb
Host smart-e0bf53b4-e4f5-4334-91a1-b5769c215826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593096194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2593096194
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2521019033
Short name T397
Test name
Test status
Simulation time 362246536 ps
CPU time 0.9 seconds
Started Dec 24 12:28:56 PM PST 23
Finished Dec 24 12:29:08 PM PST 23
Peak memory 200148 kb
Host smart-b0797c2d-3330-4192-af98-e7130e3ad98a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521019033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2521019033
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.954774491
Short name T890
Test name
Test status
Simulation time 545777787 ps
CPU time 0.96 seconds
Started Dec 24 12:29:54 PM PST 23
Finished Dec 24 12:30:20 PM PST 23
Peak memory 200148 kb
Host smart-49df72e3-a21f-481b-be31-5caf7d114ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954774491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.954774491
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1477944414
Short name T865
Test name
Test status
Simulation time 376520777 ps
CPU time 0.81 seconds
Started Dec 24 12:28:37 PM PST 23
Finished Dec 24 12:28:44 PM PST 23
Peak memory 200136 kb
Host smart-516c4808-99f0-4c63-811b-cd017fbc7945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477944414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1477944414
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3345724068
Short name T413
Test name
Test status
Simulation time 290048939 ps
CPU time 1.34 seconds
Started Dec 24 12:29:49 PM PST 23
Finished Dec 24 12:30:13 PM PST 23
Peak memory 200200 kb
Host smart-3386b946-564b-4bfb-82e4-27ffbc581831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345724068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3345724068
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1697729651
Short name T395
Test name
Test status
Simulation time 504329622 ps
CPU time 1.78 seconds
Started Dec 24 12:29:38 PM PST 23
Finished Dec 24 12:29:58 PM PST 23
Peak memory 200216 kb
Host smart-589d1a1d-7c53-4f30-a736-3d0b033c417b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697729651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1697729651
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1909414462
Short name T365
Test name
Test status
Simulation time 486071717 ps
CPU time 1.22 seconds
Started Dec 24 12:28:14 PM PST 23
Finished Dec 24 12:28:28 PM PST 23
Peak memory 200184 kb
Host smart-870f010e-7bb9-4c43-b0ae-6cb2cdeadb62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909414462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1909414462
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4054103479
Short name T74
Test name
Test status
Simulation time 1038256336 ps
CPU time 3.35 seconds
Started Dec 24 12:28:07 PM PST 23
Finished Dec 24 12:28:24 PM PST 23
Peak memory 200680 kb
Host smart-dde2e3d4-30fa-48c7-a2dd-abb1905a8bb5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054103479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4054103479
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.457425667
Short name T73
Test name
Test status
Simulation time 30299307931 ps
CPU time 70.67 seconds
Started Dec 24 12:28:21 PM PST 23
Finished Dec 24 12:29:42 PM PST 23
Peak memory 200656 kb
Host smart-dce1e87d-b041-45c1-853e-0e6f19e906b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457425667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.457425667
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1270988866
Short name T45
Test name
Test status
Simulation time 1365683107 ps
CPU time 1.13 seconds
Started Dec 24 12:27:58 PM PST 23
Finished Dec 24 12:28:13 PM PST 23
Peak memory 200480 kb
Host smart-532d1c46-3364-4244-990f-5335c86b4a8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270988866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1270988866
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1900459825
Short name T41
Test name
Test status
Simulation time 411685336 ps
CPU time 1.61 seconds
Started Dec 24 12:27:59 PM PST 23
Finished Dec 24 12:28:14 PM PST 23
Peak memory 200584 kb
Host smart-bf7bc212-331a-46d8-afc6-f8a8a94454cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900459825 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1900459825
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2506415632
Short name T863
Test name
Test status
Simulation time 535787666 ps
CPU time 1.98 seconds
Started Dec 24 12:27:59 PM PST 23
Finished Dec 24 12:28:15 PM PST 23
Peak memory 200392 kb
Host smart-b2411cc1-bb50-420b-9d67-f58f64c627fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506415632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2506415632
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2313426305
Short name T892
Test name
Test status
Simulation time 388592171 ps
CPU time 1.08 seconds
Started Dec 24 12:28:04 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 200424 kb
Host smart-cff34311-1974-4375-9dde-07e3dcd7f75f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313426305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2313426305
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.998716647
Short name T387
Test name
Test status
Simulation time 2603379014 ps
CPU time 2.23 seconds
Started Dec 24 12:29:37 PM PST 23
Finished Dec 24 12:29:57 PM PST 23
Peak memory 200416 kb
Host smart-dbedacb3-d4f5-4c40-9025-2b03f44f5558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998716647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.998716647
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2092898266
Short name T873
Test name
Test status
Simulation time 798081292 ps
CPU time 1.77 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:30:49 PM PST 23
Peak memory 200672 kb
Host smart-f192f4be-088b-406e-b29c-df4d8cf33963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092898266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2092898266
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3366330357
Short name T893
Test name
Test status
Simulation time 4402801195 ps
CPU time 12.22 seconds
Started Dec 24 12:28:30 PM PST 23
Finished Dec 24 12:28:49 PM PST 23
Peak memory 200740 kb
Host smart-35a9dd0f-48ff-44e4-b6db-bc068c3f70c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366330357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3366330357
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.392622754
Short name T903
Test name
Test status
Simulation time 502180633 ps
CPU time 1.2 seconds
Started Dec 24 12:30:23 PM PST 23
Finished Dec 24 12:30:47 PM PST 23
Peak memory 200464 kb
Host smart-d533b71d-ae0a-4fef-aa3b-b5aa73a20f50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392622754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.392622754
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1111912160
Short name T366
Test name
Test status
Simulation time 305072168 ps
CPU time 0.94 seconds
Started Dec 24 12:29:46 PM PST 23
Finished Dec 24 12:30:09 PM PST 23
Peak memory 200128 kb
Host smart-300c3f12-fff6-4913-b994-f45081b33047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111912160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1111912160
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1808947397
Short name T380
Test name
Test status
Simulation time 516926533 ps
CPU time 0.88 seconds
Started Dec 24 12:28:43 PM PST 23
Finished Dec 24 12:28:50 PM PST 23
Peak memory 200216 kb
Host smart-246bfd5d-d626-4179-89e3-b2c3a8b6b353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808947397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1808947397
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3997948561
Short name T390
Test name
Test status
Simulation time 508705109 ps
CPU time 1.18 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:29:00 PM PST 23
Peak memory 200352 kb
Host smart-c8c9b647-e753-4cb2-8cd4-84c2daa0de61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997948561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3997948561
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3375476151
Short name T382
Test name
Test status
Simulation time 473944205 ps
CPU time 1.18 seconds
Started Dec 24 12:29:32 PM PST 23
Finished Dec 24 12:29:46 PM PST 23
Peak memory 200196 kb
Host smart-85603030-727b-4473-9de5-331392a51138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375476151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3375476151
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2870349255
Short name T887
Test name
Test status
Simulation time 472137812 ps
CPU time 0.91 seconds
Started Dec 24 12:30:03 PM PST 23
Finished Dec 24 12:30:30 PM PST 23
Peak memory 200248 kb
Host smart-1df4aaa2-b121-473c-8c8a-36c97c84587b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870349255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2870349255
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2855428900
Short name T46
Test name
Test status
Simulation time 439297672 ps
CPU time 0.92 seconds
Started Dec 24 12:28:30 PM PST 23
Finished Dec 24 12:28:38 PM PST 23
Peak memory 200188 kb
Host smart-16523a4a-d265-4640-a7ae-3c267dc9de73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855428900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2855428900
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3068795083
Short name T894
Test name
Test status
Simulation time 328868481 ps
CPU time 0.79 seconds
Started Dec 24 12:28:08 PM PST 23
Finished Dec 24 12:28:23 PM PST 23
Peak memory 200220 kb
Host smart-66467cf9-f19e-4715-b3ed-740d7e31c395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068795083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3068795083
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1905461264
Short name T907
Test name
Test status
Simulation time 531884926 ps
CPU time 0.91 seconds
Started Dec 24 12:28:27 PM PST 23
Finished Dec 24 12:28:36 PM PST 23
Peak memory 200140 kb
Host smart-15afd201-dfb7-40de-8936-5de5d21bd063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905461264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1905461264
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.88670233
Short name T876
Test name
Test status
Simulation time 1410184758 ps
CPU time 3.18 seconds
Started Dec 24 12:28:36 PM PST 23
Finished Dec 24 12:28:45 PM PST 23
Peak memory 200640 kb
Host smart-19825f3a-fc3b-4cc5-8c79-e23b127641fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88670233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasi
ng.88670233
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2808630649
Short name T879
Test name
Test status
Simulation time 1105611454 ps
CPU time 5.97 seconds
Started Dec 24 12:28:27 PM PST 23
Finished Dec 24 12:28:41 PM PST 23
Peak memory 200644 kb
Host smart-93bc30af-5af2-4a82-b30b-a995cf56b047
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808630649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2808630649
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3909168177
Short name T415
Test name
Test status
Simulation time 1262683358 ps
CPU time 2.21 seconds
Started Dec 24 12:29:31 PM PST 23
Finished Dec 24 12:29:46 PM PST 23
Peak memory 200536 kb
Host smart-aa4761c8-e16f-4bd7-ad39-5ed3771723cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909168177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3909168177
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4200719950
Short name T389
Test name
Test status
Simulation time 435225480 ps
CPU time 1.89 seconds
Started Dec 24 12:30:13 PM PST 23
Finished Dec 24 12:30:38 PM PST 23
Peak memory 200544 kb
Host smart-88b675c2-e616-47bf-b92f-be77be4c6aaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200719950 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.4200719950
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.522328609
Short name T889
Test name
Test status
Simulation time 474612361 ps
CPU time 1.89 seconds
Started Dec 24 12:28:31 PM PST 23
Finished Dec 24 12:28:40 PM PST 23
Peak memory 200436 kb
Host smart-9b99d069-9bd0-4370-a432-b02e5a10ce48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522328609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.522328609
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2559773458
Short name T401
Test name
Test status
Simulation time 421349438 ps
CPU time 0.86 seconds
Started Dec 24 12:27:59 PM PST 23
Finished Dec 24 12:28:13 PM PST 23
Peak memory 200232 kb
Host smart-2b901d51-6dcf-4759-8569-b50d42ff5d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559773458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2559773458
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4200564065
Short name T30
Test name
Test status
Simulation time 2462634585 ps
CPU time 2.36 seconds
Started Dec 24 12:29:32 PM PST 23
Finished Dec 24 12:29:47 PM PST 23
Peak memory 200572 kb
Host smart-702558b8-5baf-45b0-8225-c6cc2501e850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200564065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.4200564065
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.4268779101
Short name T64
Test name
Test status
Simulation time 718170650 ps
CPU time 1.85 seconds
Started Dec 24 12:30:13 PM PST 23
Finished Dec 24 12:30:38 PM PST 23
Peak memory 200744 kb
Host smart-74714653-875e-4148-bba1-3a04c1235eca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268779101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.4268779101
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4243636197
Short name T910
Test name
Test status
Simulation time 7481695131 ps
CPU time 19.95 seconds
Started Dec 24 12:28:44 PM PST 23
Finished Dec 24 12:29:11 PM PST 23
Peak memory 200728 kb
Host smart-3a4f932f-575f-4fa5-a4e5-de25db869ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243636197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.4243636197
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2256261565
Short name T376
Test name
Test status
Simulation time 289070133 ps
CPU time 0.96 seconds
Started Dec 24 12:28:23 PM PST 23
Finished Dec 24 12:28:34 PM PST 23
Peak memory 200232 kb
Host smart-e262ed2a-612d-46dd-8ddb-2a3c4ac54fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256261565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2256261565
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1277947648
Short name T416
Test name
Test status
Simulation time 465434927 ps
CPU time 1.65 seconds
Started Dec 24 12:28:08 PM PST 23
Finished Dec 24 12:28:23 PM PST 23
Peak memory 200224 kb
Host smart-f15ce802-2f02-4a86-835b-43a66486243d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277947648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1277947648
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1369088944
Short name T368
Test name
Test status
Simulation time 549152536 ps
CPU time 0.94 seconds
Started Dec 24 12:29:24 PM PST 23
Finished Dec 24 12:29:33 PM PST 23
Peak memory 200096 kb
Host smart-1d08ba43-de92-4bb8-9f11-427b685aa305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369088944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1369088944
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1767316259
Short name T369
Test name
Test status
Simulation time 513890623 ps
CPU time 0.69 seconds
Started Dec 24 12:28:27 PM PST 23
Finished Dec 24 12:28:36 PM PST 23
Peak memory 200212 kb
Host smart-c08214f3-95d4-43f2-97f9-b1378915c713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767316259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1767316259
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4055455689
Short name T400
Test name
Test status
Simulation time 421936361 ps
CPU time 0.88 seconds
Started Dec 24 12:31:31 PM PST 23
Finished Dec 24 12:31:57 PM PST 23
Peak memory 200156 kb
Host smart-d1468ecb-31f6-4f78-bfce-a4aefebfc5ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055455689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4055455689
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3344644489
Short name T192
Test name
Test status
Simulation time 519718584 ps
CPU time 0.96 seconds
Started Dec 24 12:31:03 PM PST 23
Finished Dec 24 12:31:23 PM PST 23
Peak memory 200328 kb
Host smart-ffddfa22-050c-4d6f-9503-99c490ab2354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344644489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3344644489
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2647315805
Short name T375
Test name
Test status
Simulation time 473631306 ps
CPU time 1.64 seconds
Started Dec 24 12:28:48 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 200080 kb
Host smart-d54b267a-f2c9-411d-91fd-4ab3d85d8ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647315805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2647315805
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1095277573
Short name T899
Test name
Test status
Simulation time 471157491 ps
CPU time 1.77 seconds
Started Dec 24 12:29:38 PM PST 23
Finished Dec 24 12:29:59 PM PST 23
Peak memory 200224 kb
Host smart-6fba75ce-627b-4831-93b8-1af9b9c4e830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095277573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1095277573
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3631551580
Short name T370
Test name
Test status
Simulation time 362248452 ps
CPU time 0.89 seconds
Started Dec 24 12:29:31 PM PST 23
Finished Dec 24 12:29:44 PM PST 23
Peak memory 200212 kb
Host smart-fa4445af-589c-4d95-a0cd-213c966976b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631551580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3631551580
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3249941467
Short name T381
Test name
Test status
Simulation time 447752740 ps
CPU time 1.27 seconds
Started Dec 24 12:28:39 PM PST 23
Finished Dec 24 12:28:46 PM PST 23
Peak memory 200584 kb
Host smart-c0691943-48ec-46b9-9d65-764fb3f7b7d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249941467 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3249941467
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1652956696
Short name T76
Test name
Test status
Simulation time 491297138 ps
CPU time 1.13 seconds
Started Dec 24 12:28:32 PM PST 23
Finished Dec 24 12:28:40 PM PST 23
Peak memory 200436 kb
Host smart-5a03bb30-eaf6-42f4-84c6-726fa29c5e96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652956696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1652956696
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3441164598
Short name T378
Test name
Test status
Simulation time 350336267 ps
CPU time 1.03 seconds
Started Dec 24 12:29:30 PM PST 23
Finished Dec 24 12:29:42 PM PST 23
Peak memory 200428 kb
Host smart-c36cd88b-1979-410f-91ba-c67e197c1acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441164598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3441164598
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3179051613
Short name T4
Test name
Test status
Simulation time 3864472472 ps
CPU time 2.57 seconds
Started Dec 24 12:28:43 PM PST 23
Finished Dec 24 12:28:52 PM PST 23
Peak memory 200812 kb
Host smart-5dfba70f-1318-4757-929c-6279de00f1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179051613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3179051613
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3664779455
Short name T407
Test name
Test status
Simulation time 956624940 ps
CPU time 1.4 seconds
Started Dec 24 12:28:43 PM PST 23
Finished Dec 24 12:28:51 PM PST 23
Peak memory 200520 kb
Host smart-f7ffc428-4b23-4208-a660-996e6a122a99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664779455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3664779455
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.163080030
Short name T904
Test name
Test status
Simulation time 8424377017 ps
CPU time 22.24 seconds
Started Dec 24 12:28:04 PM PST 23
Finished Dec 24 12:28:38 PM PST 23
Peak memory 200756 kb
Host smart-29643e60-d3bf-43f8-98f8-d238334ee2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163080030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.163080030
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1639455468
Short name T383
Test name
Test status
Simulation time 446643024 ps
CPU time 1.05 seconds
Started Dec 24 12:28:28 PM PST 23
Finished Dec 24 12:28:37 PM PST 23
Peak memory 200528 kb
Host smart-65f2045b-4fd3-44f7-953c-5eb625554d67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639455468 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1639455468
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.893919848
Short name T69
Test name
Test status
Simulation time 589421949 ps
CPU time 1.11 seconds
Started Dec 24 12:31:01 PM PST 23
Finished Dec 24 12:31:22 PM PST 23
Peak memory 200476 kb
Host smart-3c080a5b-4461-4d9b-974e-0ee28cdb2641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893919848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.893919848
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3568914682
Short name T377
Test name
Test status
Simulation time 335151719 ps
CPU time 0.97 seconds
Started Dec 24 12:28:43 PM PST 23
Finished Dec 24 12:28:50 PM PST 23
Peak memory 200216 kb
Host smart-2a0defe5-ed06-46f3-9ef9-bf4c1a52579b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568914682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3568914682
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2684812989
Short name T911
Test name
Test status
Simulation time 2738476090 ps
CPU time 2.65 seconds
Started Dec 24 12:28:29 PM PST 23
Finished Dec 24 12:28:39 PM PST 23
Peak memory 200532 kb
Host smart-a21ddcaf-85de-41f3-addc-885b89ddc7c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684812989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2684812989
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3452540953
Short name T877
Test name
Test status
Simulation time 508016854 ps
CPU time 3.26 seconds
Started Dec 24 12:29:39 PM PST 23
Finished Dec 24 12:30:05 PM PST 23
Peak memory 200804 kb
Host smart-1cd03ee0-4647-474f-847f-0cb78f87b251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452540953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3452540953
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.801066146
Short name T11
Test name
Test status
Simulation time 5103814370 ps
CPU time 4.51 seconds
Started Dec 24 12:30:07 PM PST 23
Finished Dec 24 12:30:36 PM PST 23
Peak memory 200772 kb
Host smart-417cb14a-db9c-479a-b1d7-3d3203aea4fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801066146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.801066146
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1658993736
Short name T405
Test name
Test status
Simulation time 600844483 ps
CPU time 2.21 seconds
Started Dec 24 12:29:28 PM PST 23
Finished Dec 24 12:29:40 PM PST 23
Peak memory 200560 kb
Host smart-63853102-9dcf-43e5-9715-a153767344fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658993736 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1658993736
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3255562590
Short name T379
Test name
Test status
Simulation time 564096660 ps
CPU time 0.81 seconds
Started Dec 24 12:31:25 PM PST 23
Finished Dec 24 12:31:51 PM PST 23
Peak memory 200464 kb
Host smart-ce37bc2d-73fd-4ab2-bb32-66c33c4dad43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255562590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3255562590
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2905042743
Short name T392
Test name
Test status
Simulation time 491418094 ps
CPU time 0.74 seconds
Started Dec 24 12:29:38 PM PST 23
Finished Dec 24 12:29:57 PM PST 23
Peak memory 200152 kb
Host smart-c98b9991-50db-41e8-85af-80500fa05762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905042743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2905042743
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2593848340
Short name T191
Test name
Test status
Simulation time 2196100624 ps
CPU time 1.96 seconds
Started Dec 24 12:29:00 PM PST 23
Finished Dec 24 12:29:11 PM PST 23
Peak memory 200576 kb
Host smart-fe52126b-76e0-4843-9126-11dfec04c3e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593848340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2593848340
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4097332763
Short name T65
Test name
Test status
Simulation time 320228903 ps
CPU time 3.16 seconds
Started Dec 24 12:29:54 PM PST 23
Finished Dec 24 12:30:23 PM PST 23
Peak memory 216636 kb
Host smart-ac8cfe50-1601-466f-b8b1-a5c60b28dd62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097332763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4097332763
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2530945251
Short name T399
Test name
Test status
Simulation time 4607552558 ps
CPU time 6.38 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:07 PM PST 23
Peak memory 200736 kb
Host smart-800f4c1c-b24f-48d2-91b5-875d7bd4e213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530945251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2530945251
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2494679072
Short name T869
Test name
Test status
Simulation time 564143503 ps
CPU time 1.26 seconds
Started Dec 24 12:29:37 PM PST 23
Finished Dec 24 12:29:56 PM PST 23
Peak memory 200488 kb
Host smart-a80e328c-0da9-4cad-b31b-cb05077167dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494679072 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2494679072
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2491350330
Short name T70
Test name
Test status
Simulation time 385560968 ps
CPU time 0.93 seconds
Started Dec 24 12:28:29 PM PST 23
Finished Dec 24 12:28:37 PM PST 23
Peak memory 200512 kb
Host smart-6a5602d8-02b0-4005-902e-050f04f8d07f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491350330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2491350330
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1360089743
Short name T883
Test name
Test status
Simulation time 520470482 ps
CPU time 0.85 seconds
Started Dec 24 12:29:31 PM PST 23
Finished Dec 24 12:29:44 PM PST 23
Peak memory 200072 kb
Host smart-ed4f36c8-d121-4566-974c-1455d3269182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360089743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1360089743
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2467394364
Short name T886
Test name
Test status
Simulation time 4940424394 ps
CPU time 3.1 seconds
Started Dec 24 12:28:30 PM PST 23
Finished Dec 24 12:28:41 PM PST 23
Peak memory 200700 kb
Host smart-0faed457-6871-4653-8a1e-257ae54bd47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467394364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2467394364
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1651431036
Short name T61
Test name
Test status
Simulation time 479242448 ps
CPU time 1.77 seconds
Started Dec 24 12:28:04 PM PST 23
Finished Dec 24 12:28:18 PM PST 23
Peak memory 200796 kb
Host smart-e421b891-698a-4bd3-bb07-15d335003793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651431036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1651431036
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.21027888
Short name T40
Test name
Test status
Simulation time 391019620 ps
CPU time 1.78 seconds
Started Dec 24 12:29:42 PM PST 23
Finished Dec 24 12:30:04 PM PST 23
Peak memory 200596 kb
Host smart-06a585fb-db9f-41ec-a140-30a7c2dc110d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21027888 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.21027888
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2562015652
Short name T75
Test name
Test status
Simulation time 509783397 ps
CPU time 1.72 seconds
Started Dec 24 12:28:18 PM PST 23
Finished Dec 24 12:28:34 PM PST 23
Peak memory 200356 kb
Host smart-242899ee-3d7c-4c54-a821-3f44ba4190da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562015652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2562015652
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3580356700
Short name T373
Test name
Test status
Simulation time 477348298 ps
CPU time 0.89 seconds
Started Dec 24 12:28:02 PM PST 23
Finished Dec 24 12:28:22 PM PST 23
Peak memory 200388 kb
Host smart-fbe307d2-6b9a-46fa-b6bb-03cb763e4f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580356700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3580356700
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.534560254
Short name T897
Test name
Test status
Simulation time 4863930193 ps
CPU time 2.87 seconds
Started Dec 24 12:28:08 PM PST 23
Finished Dec 24 12:28:24 PM PST 23
Peak memory 200764 kb
Host smart-63e8a187-55cc-4d41-b408-8b4c63ef8c54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534560254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.534560254
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2613812786
Short name T724
Test name
Test status
Simulation time 330990421220 ps
CPU time 190.63 seconds
Started Dec 24 01:14:20 PM PST 23
Finished Dec 24 01:17:43 PM PST 23
Peak memory 200892 kb
Host smart-36a72208-0b64-4736-969d-80c9f8992a6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613812786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2613812786
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.260247504
Short name T641
Test name
Test status
Simulation time 165640270331 ps
CPU time 391.29 seconds
Started Dec 24 01:14:28 PM PST 23
Finished Dec 24 01:21:07 PM PST 23
Peak memory 200948 kb
Host smart-c41b21d5-9cf3-4fca-ad03-fb50cc225ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260247504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.260247504
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3880980966
Short name T248
Test name
Test status
Simulation time 329171777339 ps
CPU time 796.64 seconds
Started Dec 24 01:14:11 PM PST 23
Finished Dec 24 01:27:43 PM PST 23
Peak memory 200880 kb
Host smart-ef7dcff4-0630-42a4-9cfd-407c86773d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880980966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3880980966
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.438020669
Short name T605
Test name
Test status
Simulation time 168507437927 ps
CPU time 167.23 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:17:13 PM PST 23
Peak memory 200880 kb
Host smart-198dfe2f-5d89-4751-9909-2a09bd77062a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=438020669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.438020669
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.928044017
Short name T623
Test name
Test status
Simulation time 491209586911 ps
CPU time 300.97 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:19:20 PM PST 23
Peak memory 200852 kb
Host smart-6e5f370c-0af9-4975-9c27-f6f1b44c9cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928044017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.928044017
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.634169254
Short name T704
Test name
Test status
Simulation time 162815246417 ps
CPU time 359.48 seconds
Started Dec 24 01:14:13 PM PST 23
Finished Dec 24 01:20:27 PM PST 23
Peak memory 200864 kb
Host smart-b29b205c-0467-4bcb-a640-657389dee3f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=634169254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.634169254
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3864321838
Short name T669
Test name
Test status
Simulation time 494179075793 ps
CPU time 757.47 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:27:21 PM PST 23
Peak memory 200824 kb
Host smart-4538c034-d166-46d2-be3a-1d1598eab661
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864321838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3864321838
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3276893084
Short name T364
Test name
Test status
Simulation time 82873761669 ps
CPU time 269.01 seconds
Started Dec 24 01:14:14 PM PST 23
Finished Dec 24 01:18:57 PM PST 23
Peak memory 201332 kb
Host smart-99e052d3-fe7d-4216-a418-81ab08c04704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276893084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3276893084
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1098792023
Short name T441
Test name
Test status
Simulation time 36774537982 ps
CPU time 88.37 seconds
Started Dec 24 01:14:04 PM PST 23
Finished Dec 24 01:15:49 PM PST 23
Peak memory 200716 kb
Host smart-d4374e5e-b7bb-406d-80b4-180557b028cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098792023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1098792023
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3448431547
Short name T852
Test name
Test status
Simulation time 3292256677 ps
CPU time 1.19 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:14:27 PM PST 23
Peak memory 200756 kb
Host smart-a2ad6076-3cdd-4518-94ae-3477dbddc189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448431547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3448431547
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3868270534
Short name T51
Test name
Test status
Simulation time 7995455814 ps
CPU time 10.16 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:14:26 PM PST 23
Peak memory 217160 kb
Host smart-1d05f75c-8c87-4719-b96e-66732d96c9a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868270534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3868270534
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.481850979
Short name T848
Test name
Test status
Simulation time 5928411432 ps
CPU time 7.79 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:14:26 PM PST 23
Peak memory 200664 kb
Host smart-e2d942d4-77d5-4536-b20f-7ca529742bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481850979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.481850979
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2172679310
Short name T358
Test name
Test status
Simulation time 80831171878 ps
CPU time 405.15 seconds
Started Dec 24 01:14:04 PM PST 23
Finished Dec 24 01:21:06 PM PST 23
Peak memory 216292 kb
Host smart-6c3396c2-f750-4924-b4a6-d55ff01cf86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172679310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2172679310
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.878975806
Short name T296
Test name
Test status
Simulation time 357357872618 ps
CPU time 136.88 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:16:22 PM PST 23
Peak memory 209284 kb
Host smart-a3de6e9e-4f70-4437-819d-08aa2538a1eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878975806 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.878975806
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.325424132
Short name T172
Test name
Test status
Simulation time 457390836 ps
CPU time 0.87 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:14:09 PM PST 23
Peak memory 200624 kb
Host smart-c9eaa4f1-ed3e-4c30-88a1-025c586610c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325424132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.325424132
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.112138618
Short name T147
Test name
Test status
Simulation time 333703886138 ps
CPU time 85.79 seconds
Started Dec 24 01:13:57 PM PST 23
Finished Dec 24 01:15:28 PM PST 23
Peak memory 200880 kb
Host smart-31deafa4-6c19-4927-ab2d-dfcdacd34f22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112138618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.112138618
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.4179717472
Short name T811
Test name
Test status
Simulation time 327949917891 ps
CPU time 747.3 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:26:43 PM PST 23
Peak memory 200876 kb
Host smart-6173681d-7e21-4b0c-8bce-7a1e6d3f84b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179717472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4179717472
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2577196859
Short name T252
Test name
Test status
Simulation time 330625587560 ps
CPU time 784.17 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:27:20 PM PST 23
Peak memory 200916 kb
Host smart-0d0b1338-fdf6-46d8-90bb-be13043c4490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577196859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2577196859
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2965012802
Short name T839
Test name
Test status
Simulation time 161345304116 ps
CPU time 208.91 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:17:44 PM PST 23
Peak memory 200904 kb
Host smart-64602fa1-1654-4988-9c2d-6a61d3ef5b15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965012802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2965012802
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3571058360
Short name T117
Test name
Test status
Simulation time 163092940224 ps
CPU time 29.28 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:14:37 PM PST 23
Peak memory 200940 kb
Host smart-0f7ea931-bb03-4518-b562-fe80c5af3619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571058360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3571058360
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2912795799
Short name T562
Test name
Test status
Simulation time 337476934938 ps
CPU time 774.08 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:27:10 PM PST 23
Peak memory 200940 kb
Host smart-80d55066-1a94-4fd2-901a-b42b024fa89c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912795799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2912795799
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.501485873
Short name T12
Test name
Test status
Simulation time 323546951107 ps
CPU time 211.91 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:17:55 PM PST 23
Peak memory 200824 kb
Host smart-5b319f2e-32a1-4da7-8d16-4da00dac5a48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501485873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.501485873
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2092127370
Short name T547
Test name
Test status
Simulation time 498993122909 ps
CPU time 1213.9 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:34:30 PM PST 23
Peak memory 200828 kb
Host smart-1547761a-fc2a-414e-8430-acd203c6ea79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092127370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2092127370
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.596450953
Short name T613
Test name
Test status
Simulation time 105137672076 ps
CPU time 373.77 seconds
Started Dec 24 01:14:07 PM PST 23
Finished Dec 24 01:20:36 PM PST 23
Peak memory 201336 kb
Host smart-c4eaa003-1bdd-4be1-b1de-9ec1d6bb3003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596450953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.596450953
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2142190319
Short name T838
Test name
Test status
Simulation time 23373526372 ps
CPU time 52.73 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:15:00 PM PST 23
Peak memory 200680 kb
Host smart-26d61eb8-9ca2-475f-b2d7-87c7998dfe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142190319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2142190319
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.211986230
Short name T424
Test name
Test status
Simulation time 4079481973 ps
CPU time 3.05 seconds
Started Dec 24 01:14:04 PM PST 23
Finished Dec 24 01:14:23 PM PST 23
Peak memory 199956 kb
Host smart-e4a15679-a26f-4049-9751-6d39fa58c243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211986230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.211986230
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.4020094882
Short name T48
Test name
Test status
Simulation time 8063555571 ps
CPU time 19.79 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:14:29 PM PST 23
Peak memory 217072 kb
Host smart-337db1e8-1ef3-4e9a-8936-e7352db6e2b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020094882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4020094882
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.166287497
Short name T723
Test name
Test status
Simulation time 5685078336 ps
CPU time 4 seconds
Started Dec 24 01:13:56 PM PST 23
Finished Dec 24 01:14:04 PM PST 23
Peak memory 200676 kb
Host smart-7e489417-62be-4fcd-9afc-bcd9ddac258c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166287497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.166287497
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1392201497
Short name T859
Test name
Test status
Simulation time 102265168903 ps
CPU time 276.73 seconds
Started Dec 24 01:13:55 PM PST 23
Finished Dec 24 01:18:35 PM PST 23
Peak memory 201320 kb
Host smart-5c447a76-5824-4897-beed-f2b7790f6c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392201497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1392201497
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.4005881651
Short name T684
Test name
Test status
Simulation time 485337166 ps
CPU time 1.59 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:14:28 PM PST 23
Peak memory 200624 kb
Host smart-04caa09a-c47a-4734-bf19-482e92f8065e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005881651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.4005881651
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1672526644
Short name T323
Test name
Test status
Simulation time 167426496078 ps
CPU time 197.04 seconds
Started Dec 24 01:14:14 PM PST 23
Finished Dec 24 01:17:46 PM PST 23
Peak memory 200868 kb
Host smart-33ddb64c-62aa-4541-aa85-5aba9cfd54f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672526644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1672526644
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1870529379
Short name T649
Test name
Test status
Simulation time 167257160816 ps
CPU time 56.77 seconds
Started Dec 24 01:14:18 PM PST 23
Finished Dec 24 01:15:28 PM PST 23
Peak memory 200896 kb
Host smart-65f75e3f-6ac2-48f9-9a96-f16b2d52d6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870529379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1870529379
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2532294981
Short name T814
Test name
Test status
Simulation time 328039940570 ps
CPU time 806.6 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:27:49 PM PST 23
Peak memory 200944 kb
Host smart-470b6ff4-2bd3-46dc-b7a7-6a264299c933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532294981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2532294981
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2238708812
Short name T477
Test name
Test status
Simulation time 161557837282 ps
CPU time 304.24 seconds
Started Dec 24 01:14:15 PM PST 23
Finished Dec 24 01:19:33 PM PST 23
Peak memory 200896 kb
Host smart-8a3d13f3-69fd-413b-917b-345c1cab8cbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238708812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2238708812
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2364867202
Short name T454
Test name
Test status
Simulation time 489616895707 ps
CPU time 303.62 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:19:49 PM PST 23
Peak memory 200836 kb
Host smart-65bd46d3-6328-4660-be39-1b48d16d988a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364867202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2364867202
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3885233658
Short name T134
Test name
Test status
Simulation time 170497257825 ps
CPU time 365.06 seconds
Started Dec 24 01:14:20 PM PST 23
Finished Dec 24 01:20:37 PM PST 23
Peak memory 200908 kb
Host smart-707dfc92-1b79-471c-bd81-43cd9aebfdd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885233658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3885233658
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2218033539
Short name T574
Test name
Test status
Simulation time 171087706933 ps
CPU time 104.41 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:16:06 PM PST 23
Peak memory 200880 kb
Host smart-c75892e0-5e8b-4e19-9869-f0183e835c55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218033539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2218033539
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3250517734
Short name T766
Test name
Test status
Simulation time 120432816151 ps
CPU time 414.42 seconds
Started Dec 24 01:14:21 PM PST 23
Finished Dec 24 01:21:27 PM PST 23
Peak memory 201332 kb
Host smart-7fed20db-4b25-43fc-bf2f-4024a71f6160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250517734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3250517734
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3104476652
Short name T435
Test name
Test status
Simulation time 28442647769 ps
CPU time 66.16 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:15:18 PM PST 23
Peak memory 200668 kb
Host smart-b2934211-ad05-4028-9e12-9a6c73901281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104476652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3104476652
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2758667300
Short name T497
Test name
Test status
Simulation time 5191682616 ps
CPU time 8.25 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:14:53 PM PST 23
Peak memory 200748 kb
Host smart-39e8e17d-3c5d-4d8c-a10e-48074bb64cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758667300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2758667300
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.33612615
Short name T607
Test name
Test status
Simulation time 5778801877 ps
CPU time 3.69 seconds
Started Dec 24 01:14:15 PM PST 23
Finished Dec 24 01:14:33 PM PST 23
Peak memory 200712 kb
Host smart-84ce6402-086e-4fab-8ab3-16cbef650c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33612615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.33612615
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3820304352
Short name T589
Test name
Test status
Simulation time 47570439696 ps
CPU time 105.74 seconds
Started Dec 24 01:14:16 PM PST 23
Finished Dec 24 01:16:16 PM PST 23
Peak memory 200724 kb
Host smart-1cdc6a78-e32f-4aee-8f26-8976db6c8863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820304352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3820304352
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.737668510
Short name T215
Test name
Test status
Simulation time 44498439753 ps
CPU time 101.78 seconds
Started Dec 24 01:14:11 PM PST 23
Finished Dec 24 01:16:09 PM PST 23
Peak memory 217784 kb
Host smart-b0580ab1-a4b3-46b0-9243-2a824dee2e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737668510 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.737668510
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1641662376
Short name T579
Test name
Test status
Simulation time 430028593 ps
CPU time 0.84 seconds
Started Dec 24 01:14:29 PM PST 23
Finished Dec 24 01:14:38 PM PST 23
Peak memory 200644 kb
Host smart-2c022395-85e4-4e80-aa34-dc2f6b232682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641662376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1641662376
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2529995419
Short name T340
Test name
Test status
Simulation time 165717413476 ps
CPU time 128.27 seconds
Started Dec 24 01:14:13 PM PST 23
Finished Dec 24 01:16:37 PM PST 23
Peak memory 200944 kb
Host smart-7309dfae-74ea-4035-89cd-d6164146da95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529995419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2529995419
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1593579854
Short name T223
Test name
Test status
Simulation time 486509144811 ps
CPU time 1035.63 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:32:07 PM PST 23
Peak memory 200928 kb
Host smart-31eaf702-19a6-4a23-a856-b9b5fe19fb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593579854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1593579854
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2663709963
Short name T160
Test name
Test status
Simulation time 494633515328 ps
CPU time 732.88 seconds
Started Dec 24 01:14:36 PM PST 23
Finished Dec 24 01:26:57 PM PST 23
Peak memory 200896 kb
Host smart-5b6e5a46-c14a-4f96-9bf0-33cf130fcb22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663709963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2663709963
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.4190533361
Short name T598
Test name
Test status
Simulation time 489241417339 ps
CPU time 302.64 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:19:30 PM PST 23
Peak memory 200892 kb
Host smart-cb41897b-210b-40e1-a17c-c643cf9bc416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190533361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4190533361
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.882224587
Short name T744
Test name
Test status
Simulation time 166861985672 ps
CPU time 398.41 seconds
Started Dec 24 01:14:13 PM PST 23
Finished Dec 24 01:21:06 PM PST 23
Peak memory 200832 kb
Host smart-cc96c8e6-4c1c-4c8b-8e69-9052b86e4612
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=882224587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.882224587
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1715017900
Short name T282
Test name
Test status
Simulation time 163093626394 ps
CPU time 205.97 seconds
Started Dec 24 01:14:18 PM PST 23
Finished Dec 24 01:17:58 PM PST 23
Peak memory 200828 kb
Host smart-ba88e81c-a2d4-493a-ab18-6d95ae5d91f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715017900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1715017900
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.966814122
Short name T624
Test name
Test status
Simulation time 322948219557 ps
CPU time 768.33 seconds
Started Dec 24 01:14:28 PM PST 23
Finished Dec 24 01:27:24 PM PST 23
Peak memory 200828 kb
Host smart-331665dc-e207-48eb-9771-049a43c8aea2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966814122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.966814122
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3257572235
Short name T176
Test name
Test status
Simulation time 44371547286 ps
CPU time 108.12 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:16:44 PM PST 23
Peak memory 200720 kb
Host smart-b0e24b27-fd91-4526-96f1-07346b047eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257572235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3257572235
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2269698429
Short name T480
Test name
Test status
Simulation time 3869967193 ps
CPU time 10.23 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:14:59 PM PST 23
Peak memory 200740 kb
Host smart-e0231111-3a5b-4ca5-8ff7-8df2a13f830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269698429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2269698429
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.726319573
Short name T827
Test name
Test status
Simulation time 5720376533 ps
CPU time 4.35 seconds
Started Dec 24 01:14:31 PM PST 23
Finished Dec 24 01:14:42 PM PST 23
Peak memory 200684 kb
Host smart-ff2613b3-f76b-4833-a5da-bc1ad12a9d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726319573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.726319573
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.971151998
Short name T286
Test name
Test status
Simulation time 413382874347 ps
CPU time 1564.11 seconds
Started Dec 24 01:14:30 PM PST 23
Finished Dec 24 01:40:41 PM PST 23
Peak memory 211136 kb
Host smart-cb4f1f1b-1cdf-49ee-82f7-c35da02e40eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971151998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
971151998
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.4155303098
Short name T850
Test name
Test status
Simulation time 275165575974 ps
CPU time 219.92 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:18:18 PM PST 23
Peak memory 209676 kb
Host smart-67a1a22d-7910-4774-9b96-4ade5e9dc1bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155303098 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.4155303098
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1047930369
Short name T732
Test name
Test status
Simulation time 396548223 ps
CPU time 1.04 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:14:40 PM PST 23
Peak memory 200668 kb
Host smart-7b5dcfb8-4426-4dea-a8d6-bbe9f3ae2dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047930369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1047930369
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.832639390
Short name T727
Test name
Test status
Simulation time 161578913821 ps
CPU time 44.92 seconds
Started Dec 24 01:14:15 PM PST 23
Finished Dec 24 01:15:14 PM PST 23
Peak memory 200904 kb
Host smart-4df8e83e-8e5a-40d0-81c8-370e7511b39c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832639390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.832639390
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2505293046
Short name T228
Test name
Test status
Simulation time 500333142574 ps
CPU time 1120.09 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:33:24 PM PST 23
Peak memory 200888 kb
Host smart-c8294668-312b-4b98-a1a7-1e0718461a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505293046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2505293046
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3300647434
Short name T659
Test name
Test status
Simulation time 169841532800 ps
CPU time 410.18 seconds
Started Dec 24 01:14:15 PM PST 23
Finished Dec 24 01:21:19 PM PST 23
Peak memory 200888 kb
Host smart-06542143-bac2-4160-bc38-6530cb591aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300647434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3300647434
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.57278759
Short name T794
Test name
Test status
Simulation time 330937711071 ps
CPU time 754.94 seconds
Started Dec 24 01:14:21 PM PST 23
Finished Dec 24 01:27:08 PM PST 23
Peak memory 200836 kb
Host smart-416dc8dd-f354-4ea0-9be1-f42d60a8c2bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=57278759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt
_fixed.57278759
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3205382952
Short name T810
Test name
Test status
Simulation time 160513485156 ps
CPU time 197.79 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:18:07 PM PST 23
Peak memory 200832 kb
Host smart-3745fdfe-24a5-4b39-9800-2a640d52b987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205382952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3205382952
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.766109516
Short name T501
Test name
Test status
Simulation time 166126611643 ps
CPU time 383.61 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:21:21 PM PST 23
Peak memory 200836 kb
Host smart-289a2f38-c026-4ab6-99ad-50107deea02f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=766109516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.766109516
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3778640501
Short name T102
Test name
Test status
Simulation time 164461792412 ps
CPU time 26.36 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:15:12 PM PST 23
Peak memory 201012 kb
Host smart-116340ea-f885-4a0e-882f-7655bdac31c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778640501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3778640501
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4180777107
Short name T525
Test name
Test status
Simulation time 163213249964 ps
CPU time 93.92 seconds
Started Dec 24 01:14:13 PM PST 23
Finished Dec 24 01:16:02 PM PST 23
Peak memory 200768 kb
Host smart-dbfdd051-94e8-4795-b404-3a89a23da032
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180777107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4180777107
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2499981902
Short name T696
Test name
Test status
Simulation time 70457758705 ps
CPU time 264.88 seconds
Started Dec 24 01:14:28 PM PST 23
Finished Dec 24 01:19:01 PM PST 23
Peak memory 201432 kb
Host smart-3cfd7903-a170-4fa8-8c5d-7ffade282870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499981902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2499981902
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.329655234
Short name T474
Test name
Test status
Simulation time 43727199557 ps
CPU time 51.07 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:15:34 PM PST 23
Peak memory 200728 kb
Host smart-bfe69af7-c336-4ac6-a5ec-24ba74e929ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329655234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.329655234
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3985515738
Short name T854
Test name
Test status
Simulation time 2928317353 ps
CPU time 4.21 seconds
Started Dec 24 01:14:22 PM PST 23
Finished Dec 24 01:14:37 PM PST 23
Peak memory 200764 kb
Host smart-588e2e3b-eaa6-4b6d-812d-46e4f93f9ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985515738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3985515738
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3454420850
Short name T609
Test name
Test status
Simulation time 5898888080 ps
CPU time 4.5 seconds
Started Dec 24 01:14:29 PM PST 23
Finished Dec 24 01:14:41 PM PST 23
Peak memory 200604 kb
Host smart-a6172798-e0f5-47be-b8cf-b6fead14f333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454420850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3454420850
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1907245167
Short name T254
Test name
Test status
Simulation time 355698255025 ps
CPU time 848.97 seconds
Started Dec 24 01:14:15 PM PST 23
Finished Dec 24 01:28:39 PM PST 23
Peak memory 200900 kb
Host smart-ad39789d-ce9e-475e-a1a9-f4d8b33a8bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907245167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1907245167
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1196955903
Short name T856
Test name
Test status
Simulation time 93004298329 ps
CPU time 58.99 seconds
Started Dec 24 01:14:13 PM PST 23
Finished Dec 24 01:15:27 PM PST 23
Peak memory 201228 kb
Host smart-fff55744-8e92-4dd2-9316-897d7b6ba130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196955903 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1196955903
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.694780308
Short name T841
Test name
Test status
Simulation time 488119097 ps
CPU time 1.78 seconds
Started Dec 24 01:14:33 PM PST 23
Finished Dec 24 01:14:42 PM PST 23
Peak memory 200680 kb
Host smart-2634abe0-b33e-470a-a5df-50453d7173f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694780308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.694780308
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3063561211
Short name T270
Test name
Test status
Simulation time 326996239306 ps
CPU time 739.18 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:26:58 PM PST 23
Peak memory 200956 kb
Host smart-d657fdc3-095f-40b9-b8b8-71d9e544b7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063561211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3063561211
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1628295985
Short name T490
Test name
Test status
Simulation time 330479317009 ps
CPU time 216.63 seconds
Started Dec 24 01:14:37 PM PST 23
Finished Dec 24 01:18:21 PM PST 23
Peak memory 200960 kb
Host smart-2b4ac825-350a-43b5-9674-2a4c9b636378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628295985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1628295985
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1654098557
Short name T596
Test name
Test status
Simulation time 160080616010 ps
CPU time 384.88 seconds
Started Dec 24 01:14:30 PM PST 23
Finished Dec 24 01:21:02 PM PST 23
Peak memory 200960 kb
Host smart-13874312-f6a5-44bd-b1bf-d608977ea0b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654098557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1654098557
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1530357859
Short name T731
Test name
Test status
Simulation time 490783010034 ps
CPU time 319.93 seconds
Started Dec 24 01:14:16 PM PST 23
Finished Dec 24 01:19:50 PM PST 23
Peak memory 200892 kb
Host smart-d9ad33a4-da32-4ef2-9f97-ea5ba437602f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530357859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1530357859
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3409330291
Short name T582
Test name
Test status
Simulation time 338554395711 ps
CPU time 200.99 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:18:04 PM PST 23
Peak memory 200792 kb
Host smart-8e80c611-25d3-42be-a6ac-09d4995cc23d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409330291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3409330291
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.876734128
Short name T307
Test name
Test status
Simulation time 166885803747 ps
CPU time 94.73 seconds
Started Dec 24 01:14:16 PM PST 23
Finished Dec 24 01:16:05 PM PST 23
Peak memory 200812 kb
Host smart-a98faa70-a7e3-48b7-8b32-dc0bdf233b79
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876734128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.876734128
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2865925099
Short name T541
Test name
Test status
Simulation time 490865589969 ps
CPU time 287.01 seconds
Started Dec 24 01:14:34 PM PST 23
Finished Dec 24 01:19:28 PM PST 23
Peak memory 200868 kb
Host smart-474a07e2-5e5e-46bc-80f9-c36601240445
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865925099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2865925099
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4265835775
Short name T472
Test name
Test status
Simulation time 37364654998 ps
CPU time 24.73 seconds
Started Dec 24 01:14:28 PM PST 23
Finished Dec 24 01:15:00 PM PST 23
Peak memory 200624 kb
Host smart-859db5ea-b99b-4ba1-9907-166ca3730950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265835775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4265835775
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3350569645
Short name T656
Test name
Test status
Simulation time 3700037749 ps
CPU time 4.91 seconds
Started Dec 24 01:14:22 PM PST 23
Finished Dec 24 01:14:38 PM PST 23
Peak memory 200760 kb
Host smart-be6e965f-c310-4175-b79a-72c77dca8b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350569645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3350569645
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.15305483
Short name T178
Test name
Test status
Simulation time 5845825311 ps
CPU time 3.35 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:14:53 PM PST 23
Peak memory 200680 kb
Host smart-bb90592d-1643-41b4-b3ff-c1d2ca2a8ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15305483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.15305483
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3555872611
Short name T21
Test name
Test status
Simulation time 347820225012 ps
CPU time 230.67 seconds
Started Dec 24 01:14:20 PM PST 23
Finished Dec 24 01:18:23 PM PST 23
Peak memory 200892 kb
Host smart-8c0a7fbc-7a76-4248-9326-c5f6209914bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555872611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3555872611
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2731497392
Short name T640
Test name
Test status
Simulation time 418998851 ps
CPU time 0.75 seconds
Started Dec 24 01:14:18 PM PST 23
Finished Dec 24 01:14:32 PM PST 23
Peak memory 200628 kb
Host smart-5426d90f-5b6a-4c4f-a107-1fc93651d358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731497392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2731497392
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.740727650
Short name T98
Test name
Test status
Simulation time 165854731214 ps
CPU time 357.49 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:21:06 PM PST 23
Peak memory 200944 kb
Host smart-a80e2ccb-dc0b-450c-a056-7499ac378914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740727650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.740727650
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2664179675
Short name T151
Test name
Test status
Simulation time 326932366544 ps
CPU time 111.25 seconds
Started Dec 24 01:14:39 PM PST 23
Finished Dec 24 01:16:38 PM PST 23
Peak memory 200968 kb
Host smart-5f5e9791-6826-45c1-8259-1c6d6a403ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664179675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2664179675
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1561213331
Short name T505
Test name
Test status
Simulation time 161997493730 ps
CPU time 24.52 seconds
Started Dec 24 01:14:15 PM PST 23
Finished Dec 24 01:14:54 PM PST 23
Peak memory 200828 kb
Host smart-5826edfc-351c-4b8b-8c56-261877f805f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561213331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1561213331
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.4054835086
Short name T634
Test name
Test status
Simulation time 335239942895 ps
CPU time 183.18 seconds
Started Dec 24 01:14:15 PM PST 23
Finished Dec 24 01:17:32 PM PST 23
Peak memory 200892 kb
Host smart-2c6d9fb6-f9bd-4d21-ba55-ffb2dd9bfeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054835086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.4054835086
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1930791351
Short name T448
Test name
Test status
Simulation time 333082113627 ps
CPU time 345.63 seconds
Started Dec 24 01:14:22 PM PST 23
Finished Dec 24 01:20:19 PM PST 23
Peak memory 200944 kb
Host smart-7bc0cf81-81cb-4631-aa08-2e9863435c75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930791351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1930791351
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1866256485
Short name T500
Test name
Test status
Simulation time 168169497103 ps
CPU time 99.05 seconds
Started Dec 24 01:14:41 PM PST 23
Finished Dec 24 01:16:26 PM PST 23
Peak memory 200904 kb
Host smart-64d8164e-ab00-41a4-84a5-9de201f1d66b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866256485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1866256485
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2919892141
Short name T204
Test name
Test status
Simulation time 101825982930 ps
CPU time 560 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:24:03 PM PST 23
Peak memory 201308 kb
Host smart-5059b604-f3e5-4e1e-9d3b-a6e6e7966807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919892141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2919892141
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2320519494
Short name T787
Test name
Test status
Simulation time 28735509572 ps
CPU time 66.12 seconds
Started Dec 24 01:14:15 PM PST 23
Finished Dec 24 01:15:35 PM PST 23
Peak memory 200704 kb
Host smart-56929d01-6347-46e7-90bb-4760df4be68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320519494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2320519494
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1386884195
Short name T443
Test name
Test status
Simulation time 4628993562 ps
CPU time 11.08 seconds
Started Dec 24 01:14:18 PM PST 23
Finished Dec 24 01:14:43 PM PST 23
Peak memory 200636 kb
Host smart-da58d9b1-9a07-4a58-b161-f705e8a9cf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386884195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1386884195
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1049550056
Short name T484
Test name
Test status
Simulation time 5978479353 ps
CPU time 14.6 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:14:41 PM PST 23
Peak memory 200692 kb
Host smart-b811942e-4b3d-44a9-89be-f50ea5c4bbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049550056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1049550056
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1596756853
Short name T537
Test name
Test status
Simulation time 41856792992 ps
CPU time 14.07 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:15:04 PM PST 23
Peak memory 200684 kb
Host smart-61eabf52-ad27-4325-b38a-88266624b535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596756853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1596756853
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.865948636
Short name T347
Test name
Test status
Simulation time 48769827385 ps
CPU time 97.95 seconds
Started Dec 24 01:14:16 PM PST 23
Finished Dec 24 01:16:08 PM PST 23
Peak memory 209572 kb
Host smart-0b9342d4-221d-4831-b78e-6db05256e2d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865948636 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.865948636
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1984906214
Short name T600
Test name
Test status
Simulation time 363206910 ps
CPU time 0.83 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:15:13 PM PST 23
Peak memory 200684 kb
Host smart-a61d4159-cba1-4872-b361-6b2e7fdb1656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984906214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1984906214
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1419673262
Short name T339
Test name
Test status
Simulation time 334319312487 ps
CPU time 203.64 seconds
Started Dec 24 01:14:30 PM PST 23
Finished Dec 24 01:18:00 PM PST 23
Peak memory 200968 kb
Host smart-fa8cc7b0-3815-4abf-b1c7-9db491857fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419673262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1419673262
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.479731414
Short name T166
Test name
Test status
Simulation time 327800092616 ps
CPU time 73.33 seconds
Started Dec 24 01:14:19 PM PST 23
Finished Dec 24 01:15:45 PM PST 23
Peak memory 200976 kb
Host smart-549bc264-f8c5-40b4-8d3b-f3741dcc51ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479731414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.479731414
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2859200562
Short name T493
Test name
Test status
Simulation time 320286569380 ps
CPU time 768.79 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:27:28 PM PST 23
Peak memory 200864 kb
Host smart-2eeb0369-e6cd-4a9a-8281-ea69c1def33a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859200562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2859200562
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1563992814
Short name T808
Test name
Test status
Simulation time 489892402142 ps
CPU time 1187.27 seconds
Started Dec 24 01:14:21 PM PST 23
Finished Dec 24 01:34:20 PM PST 23
Peak memory 200840 kb
Host smart-b8b99470-2e48-4cb3-8a1a-faa98a386888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563992814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1563992814
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1890009293
Short name T628
Test name
Test status
Simulation time 165701550828 ps
CPU time 75.7 seconds
Started Dec 24 01:14:17 PM PST 23
Finished Dec 24 01:15:47 PM PST 23
Peak memory 200760 kb
Host smart-2dcf868f-d0d6-4a41-8221-b82aca35f546
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890009293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1890009293
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2012810463
Short name T101
Test name
Test status
Simulation time 169603636533 ps
CPU time 402.02 seconds
Started Dec 24 01:14:13 PM PST 23
Finished Dec 24 01:21:10 PM PST 23
Peak memory 200896 kb
Host smart-d11a4a50-7d94-4bce-888f-313463b46894
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012810463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2012810463
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2442960023
Short name T508
Test name
Test status
Simulation time 488970589535 ps
CPU time 590.34 seconds
Started Dec 24 01:14:14 PM PST 23
Finished Dec 24 01:24:19 PM PST 23
Peak memory 200912 kb
Host smart-57783c1a-b80a-40fc-b72c-3895b6981cc6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442960023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2442960023
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1932951061
Short name T201
Test name
Test status
Simulation time 109154326295 ps
CPU time 438.22 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:22:04 PM PST 23
Peak memory 201284 kb
Host smart-c9338f93-f5b5-48d3-beed-974d1805eae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932951061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1932951061
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.856224714
Short name T429
Test name
Test status
Simulation time 43964594989 ps
CPU time 89.29 seconds
Started Dec 24 01:14:14 PM PST 23
Finished Dec 24 01:15:58 PM PST 23
Peak memory 200744 kb
Host smart-839234cf-7495-46bb-ac3c-3a36fc180288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856224714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.856224714
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1140082174
Short name T475
Test name
Test status
Simulation time 4802388179 ps
CPU time 12.52 seconds
Started Dec 24 01:14:16 PM PST 23
Finished Dec 24 01:14:43 PM PST 23
Peak memory 200700 kb
Host smart-c1efe09e-f371-4f90-b35c-b1e2fca11baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140082174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1140082174
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2936147867
Short name T590
Test name
Test status
Simulation time 5991825297 ps
CPU time 6.2 seconds
Started Dec 24 01:14:31 PM PST 23
Finished Dec 24 01:14:44 PM PST 23
Peak memory 200676 kb
Host smart-4b8feabf-3d43-458b-817e-22577b555703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936147867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2936147867
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3375657798
Short name T105
Test name
Test status
Simulation time 321894172194 ps
CPU time 61.06 seconds
Started Dec 24 01:14:17 PM PST 23
Finished Dec 24 01:15:31 PM PST 23
Peak memory 200904 kb
Host smart-ce9872af-61c7-45f0-a2ff-de23eae50a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375657798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3375657798
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3416879609
Short name T557
Test name
Test status
Simulation time 186915959047 ps
CPU time 45.54 seconds
Started Dec 24 01:14:18 PM PST 23
Finished Dec 24 01:15:17 PM PST 23
Peak memory 209460 kb
Host smart-ad56a773-fde2-422d-86d2-20b3a34b0a43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416879609 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3416879609
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3916984933
Short name T775
Test name
Test status
Simulation time 466278435 ps
CPU time 1.12 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:15:13 PM PST 23
Peak memory 200672 kb
Host smart-dea8a0ce-6f2f-4d98-a998-058a39250b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916984933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3916984933
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3550408680
Short name T35
Test name
Test status
Simulation time 490013226885 ps
CPU time 668.9 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:26:19 PM PST 23
Peak memory 200892 kb
Host smart-7f78ae7b-254f-456c-ba26-9ca7c3fe0d40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550408680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3550408680
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3418994809
Short name T150
Test name
Test status
Simulation time 501315100149 ps
CPU time 567.53 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:24:22 PM PST 23
Peak memory 200944 kb
Host smart-44deed25-c0dc-4bed-9adb-e6a451856e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418994809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3418994809
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1744108236
Short name T96
Test name
Test status
Simulation time 166346411583 ps
CPU time 354.45 seconds
Started Dec 24 01:14:39 PM PST 23
Finished Dec 24 01:20:41 PM PST 23
Peak memory 200964 kb
Host smart-3c428d29-6bc6-47da-ae4f-8a53a2b64a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744108236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1744108236
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.183001787
Short name T715
Test name
Test status
Simulation time 488265192494 ps
CPU time 596.09 seconds
Started Dec 24 01:14:39 PM PST 23
Finished Dec 24 01:24:42 PM PST 23
Peak memory 200884 kb
Host smart-5bc12fbb-7f71-400c-8dd9-af808d1d08d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=183001787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.183001787
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2379870726
Short name T733
Test name
Test status
Simulation time 162896787657 ps
CPU time 152.6 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:17:55 PM PST 23
Peak memory 200936 kb
Host smart-90d4841b-ba03-4f20-a578-a44dd06eaf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379870726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2379870726
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3898458985
Short name T821
Test name
Test status
Simulation time 164432455780 ps
CPU time 106.61 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:16:43 PM PST 23
Peak memory 200864 kb
Host smart-b3af8999-9cf0-483f-b24a-d6f669664781
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898458985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3898458985
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3793281774
Short name T123
Test name
Test status
Simulation time 327661826401 ps
CPU time 396.32 seconds
Started Dec 24 01:14:29 PM PST 23
Finished Dec 24 01:21:13 PM PST 23
Peak memory 200800 kb
Host smart-81a8ed2a-7cf1-48d9-9b4a-bda6590af570
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793281774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3793281774
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3794669247
Short name T753
Test name
Test status
Simulation time 332338447243 ps
CPU time 765.53 seconds
Started Dec 24 01:14:39 PM PST 23
Finished Dec 24 01:27:35 PM PST 23
Peak memory 200808 kb
Host smart-84419489-4d4d-442f-9a44-b92e24a7dcf4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794669247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3794669247
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.538462932
Short name T194
Test name
Test status
Simulation time 66270655540 ps
CPU time 240.95 seconds
Started Dec 24 01:14:59 PM PST 23
Finished Dec 24 01:19:26 PM PST 23
Peak memory 201340 kb
Host smart-141f8e3d-aa86-4f0e-8702-57fde251a6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538462932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.538462932
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1132092890
Short name T59
Test name
Test status
Simulation time 33428361653 ps
CPU time 38.16 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:15:37 PM PST 23
Peak memory 200620 kb
Host smart-3f7ad699-688b-4f3c-ad76-d836d77593f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132092890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1132092890
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1011769960
Short name T721
Test name
Test status
Simulation time 3852071830 ps
CPU time 8.44 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:15:21 PM PST 23
Peak memory 200744 kb
Host smart-ccbe2cdb-5a0a-4254-9ca7-e34628d78e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011769960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1011769960
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3561745911
Short name T464
Test name
Test status
Simulation time 6131506416 ps
CPU time 4.12 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:14:53 PM PST 23
Peak memory 200748 kb
Host smart-b4eb83ec-7532-4392-acc8-b2c3dbfdabe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561745911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3561745911
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.367896108
Short name T207
Test name
Test status
Simulation time 285788806655 ps
CPU time 1272.91 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:35:52 PM PST 23
Peak memory 217208 kb
Host smart-54b73b09-e25d-4d9a-af6a-f5a7ebbe88a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367896108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
367896108
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.446054526
Short name T584
Test name
Test status
Simulation time 50242908711 ps
CPU time 122.8 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:16:55 PM PST 23
Peak memory 209540 kb
Host smart-ff55027b-390f-418f-ad7f-814560b453c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446054526 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.446054526
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.224502658
Short name T556
Test name
Test status
Simulation time 284285601 ps
CPU time 0.93 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:14:59 PM PST 23
Peak memory 200684 kb
Host smart-44a80da4-5d4e-4894-850d-94ec04a36c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224502658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.224502658
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1076062985
Short name T614
Test name
Test status
Simulation time 493639484510 ps
CPU time 285.21 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:19:31 PM PST 23
Peak memory 200964 kb
Host smart-ee322d6a-8ce6-4157-88d8-724fd5b0b526
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076062985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1076062985
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1529911645
Short name T798
Test name
Test status
Simulation time 161061355386 ps
CPU time 200.9 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:18:11 PM PST 23
Peak memory 200952 kb
Host smart-c04d20ab-ab9d-4cb6-bd38-41b7042bbe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529911645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1529911645
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.595635677
Short name T315
Test name
Test status
Simulation time 167849263850 ps
CPU time 98.37 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:16:24 PM PST 23
Peak memory 200840 kb
Host smart-335b9eb0-1dd5-4cb1-8b82-feba2a549f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595635677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.595635677
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1920494821
Short name T444
Test name
Test status
Simulation time 160731475281 ps
CPU time 360.95 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:20:52 PM PST 23
Peak memory 200892 kb
Host smart-496d34d7-faa3-4e85-880c-2fedf07828c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920494821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1920494821
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1372750726
Short name T815
Test name
Test status
Simulation time 325594126007 ps
CPU time 804.41 seconds
Started Dec 24 01:14:36 PM PST 23
Finished Dec 24 01:28:09 PM PST 23
Peak memory 200892 kb
Host smart-28d7d1fb-8daf-4551-a276-2037a540b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372750726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1372750726
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2602058827
Short name T645
Test name
Test status
Simulation time 328986765719 ps
CPU time 809.02 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:28:15 PM PST 23
Peak memory 200820 kb
Host smart-73bf8eb4-0150-45cc-bad7-7fa7f4d439a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602058827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2602058827
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3995274173
Short name T311
Test name
Test status
Simulation time 482781683700 ps
CPU time 1071.24 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:32:40 PM PST 23
Peak memory 201008 kb
Host smart-0ca5fbe3-e484-4780-a692-5536c5b74d6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995274173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3995274173
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.483561920
Short name T422
Test name
Test status
Simulation time 323276069448 ps
CPU time 134.23 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:17:09 PM PST 23
Peak memory 200900 kb
Host smart-e8349003-7bf5-4b0c-916a-3e7aef8c9bee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483561920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.483561920
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.84706544
Short name T591
Test name
Test status
Simulation time 142780973865 ps
CPU time 457.78 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:22:36 PM PST 23
Peak memory 201400 kb
Host smart-5734cb79-8c18-4c5b-8d36-fb6b62cc2956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84706544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.84706544
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1547000923
Short name T507
Test name
Test status
Simulation time 39977857677 ps
CPU time 24.41 seconds
Started Dec 24 01:14:40 PM PST 23
Finished Dec 24 01:15:11 PM PST 23
Peak memory 200728 kb
Host smart-06a8837a-7e68-4765-9115-06ebcebf8ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547000923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1547000923
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2228925679
Short name T666
Test name
Test status
Simulation time 2882909713 ps
CPU time 6.75 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:15:17 PM PST 23
Peak memory 200788 kb
Host smart-fdb4e952-2a85-476b-b960-438cd954a6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228925679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2228925679
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1365941243
Short name T720
Test name
Test status
Simulation time 6086933954 ps
CPU time 14.56 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:14:54 PM PST 23
Peak memory 200528 kb
Host smart-80aa67d2-204e-48ec-a4ee-20324324e6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365941243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1365941243
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.657763105
Short name T710
Test name
Test status
Simulation time 505976262860 ps
CPU time 294.41 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:19:44 PM PST 23
Peak memory 200884 kb
Host smart-34417592-8f44-4cbf-8101-ea7d3b0b513f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657763105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
657763105
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.659967106
Short name T837
Test name
Test status
Simulation time 124163497068 ps
CPU time 157.57 seconds
Started Dec 24 01:14:42 PM PST 23
Finished Dec 24 01:17:26 PM PST 23
Peak memory 210308 kb
Host smart-781a6b26-eff2-4cdb-8de2-6a348bf89d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659967106 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.659967106
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3189979134
Short name T776
Test name
Test status
Simulation time 454134583 ps
CPU time 0.89 seconds
Started Dec 24 01:14:34 PM PST 23
Finished Dec 24 01:14:42 PM PST 23
Peak memory 200420 kb
Host smart-61314bda-0195-4542-8c69-b29b0f79a51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189979134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3189979134
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1177637048
Short name T331
Test name
Test status
Simulation time 498799570474 ps
CPU time 475.98 seconds
Started Dec 24 01:14:34 PM PST 23
Finished Dec 24 01:22:38 PM PST 23
Peak memory 200880 kb
Host smart-1f42eb14-7388-43fc-8c0f-2db0b5029156
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177637048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1177637048
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.8659215
Short name T137
Test name
Test status
Simulation time 322719452059 ps
CPU time 114.25 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:16:51 PM PST 23
Peak memory 200812 kb
Host smart-311075d1-2a93-458a-a317-d476618d3282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8659215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.8659215
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1812425156
Short name T660
Test name
Test status
Simulation time 163507806203 ps
CPU time 62.89 seconds
Started Dec 24 01:14:41 PM PST 23
Finished Dec 24 01:15:50 PM PST 23
Peak memory 201140 kb
Host smart-592ece80-6df9-43ee-8594-93d65f072d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812425156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1812425156
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.4120674060
Short name T560
Test name
Test status
Simulation time 495298201956 ps
CPU time 595.87 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:24:47 PM PST 23
Peak memory 200876 kb
Host smart-5c348101-20c7-4169-bbb9-25dbfba3610e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120674060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.4120674060
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.18272437
Short name T120
Test name
Test status
Simulation time 518106632042 ps
CPU time 307.08 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:20:17 PM PST 23
Peak memory 200868 kb
Host smart-6acaeb52-4c5b-4a4a-a503-a4494c8c1a9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18272437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_w
akeup.18272437
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1506560882
Short name T778
Test name
Test status
Simulation time 492036630060 ps
CPU time 1082.67 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:33:11 PM PST 23
Peak memory 201008 kb
Host smart-742130fb-4861-46cb-880f-1a46fa9d1ee2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506560882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1506560882
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2410208034
Short name T828
Test name
Test status
Simulation time 81391202040 ps
CPU time 413.62 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:21:49 PM PST 23
Peak memory 201320 kb
Host smart-6bf3fd82-5e27-46ed-9913-174b4408188d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410208034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2410208034
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2645015813
Short name T805
Test name
Test status
Simulation time 36288034221 ps
CPU time 13.07 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:15:08 PM PST 23
Peak memory 200216 kb
Host smart-1471db98-2f1d-4b6e-ab6f-58ea2141f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645015813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2645015813
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3787320722
Short name T452
Test name
Test status
Simulation time 2998801037 ps
CPU time 7.61 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:15:20 PM PST 23
Peak memory 200624 kb
Host smart-fad7fa9b-3062-4274-927b-eddafd60c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787320722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3787320722
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2767779523
Short name T620
Test name
Test status
Simulation time 5853615962 ps
CPU time 4.04 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:14:56 PM PST 23
Peak memory 200672 kb
Host smart-9c70cae5-9565-4520-b7d5-4bddeb76b73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767779523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2767779523
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3166975225
Short name T797
Test name
Test status
Simulation time 44925710814 ps
CPU time 101.37 seconds
Started Dec 24 01:14:30 PM PST 23
Finished Dec 24 01:16:18 PM PST 23
Peak memory 209228 kb
Host smart-a0de8fb6-700d-4e38-92fe-b6de65fc106a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166975225 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3166975225
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.35258289
Short name T840
Test name
Test status
Simulation time 530537258 ps
CPU time 1.59 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:15:00 PM PST 23
Peak memory 200704 kb
Host smart-8c5790fd-4128-48bb-8163-24610ff7890f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35258289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.35258289
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2625847523
Short name T267
Test name
Test status
Simulation time 493884034930 ps
CPU time 317.5 seconds
Started Dec 24 01:14:36 PM PST 23
Finished Dec 24 01:20:01 PM PST 23
Peak memory 200768 kb
Host smart-a8c1e3ea-84d4-41ce-8318-a10041f4f61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625847523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2625847523
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2877883124
Short name T430
Test name
Test status
Simulation time 166681792654 ps
CPU time 376.09 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:20:59 PM PST 23
Peak memory 200908 kb
Host smart-37746d20-2f5f-4736-84ea-2cfd986a6e02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877883124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2877883124
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1936332898
Short name T682
Test name
Test status
Simulation time 163778565016 ps
CPU time 58.61 seconds
Started Dec 24 01:14:39 PM PST 23
Finished Dec 24 01:15:45 PM PST 23
Peak memory 200868 kb
Host smart-d467b834-660f-4ffa-bd2d-2aedcd5dd8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936332898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1936332898
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1269973217
Short name T485
Test name
Test status
Simulation time 326092230289 ps
CPU time 398.21 seconds
Started Dec 24 01:14:40 PM PST 23
Finished Dec 24 01:21:25 PM PST 23
Peak memory 200836 kb
Host smart-9b65e7dc-fc51-46b4-8598-376d04d2b139
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269973217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1269973217
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3018139990
Short name T313
Test name
Test status
Simulation time 480923265799 ps
CPU time 589.27 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:24:45 PM PST 23
Peak memory 200896 kb
Host smart-c731a668-12bc-4541-8544-4e09a877ca6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018139990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3018139990
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1181480081
Short name T713
Test name
Test status
Simulation time 481817017228 ps
CPU time 431.38 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:22:08 PM PST 23
Peak memory 200868 kb
Host smart-7482052e-f93b-45eb-97ce-99e2606d98f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181480081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1181480081
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.362211189
Short name T456
Test name
Test status
Simulation time 30886147957 ps
CPU time 74.8 seconds
Started Dec 24 01:15:16 PM PST 23
Finished Dec 24 01:16:57 PM PST 23
Peak memory 200680 kb
Host smart-6c8666a5-aa21-4c72-bef4-1218ef17c1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362211189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.362211189
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1849349659
Short name T781
Test name
Test status
Simulation time 5271930271 ps
CPU time 3.93 seconds
Started Dec 24 01:14:31 PM PST 23
Finished Dec 24 01:14:42 PM PST 23
Peak memory 200616 kb
Host smart-f48c2f8d-8fab-48fd-a8db-1cf26194e10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849349659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1849349659
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3548538215
Short name T688
Test name
Test status
Simulation time 6099899691 ps
CPU time 14.01 seconds
Started Dec 24 01:14:42 PM PST 23
Finished Dec 24 01:15:02 PM PST 23
Peak memory 200680 kb
Host smart-786460d2-ac14-4687-ae6b-967a40d3bdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548538215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3548538215
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2179837771
Short name T676
Test name
Test status
Simulation time 137963957996 ps
CPU time 562.59 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:24:37 PM PST 23
Peak memory 209660 kb
Host smart-30bde12d-03d6-4ec0-b4b5-7eaf1536ab16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179837771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2179837771
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3894254448
Short name T535
Test name
Test status
Simulation time 442442224478 ps
CPU time 101.06 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:16:53 PM PST 23
Peak memory 209208 kb
Host smart-c2d5ad1f-0121-411d-a6b5-43a77d171868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894254448 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3894254448
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1534889891
Short name T734
Test name
Test status
Simulation time 413968252 ps
CPU time 0.79 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:14:17 PM PST 23
Peak memory 200676 kb
Host smart-ad511136-b6e8-41ed-803b-333fa2575b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534889891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1534889891
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.433266458
Short name T719
Test name
Test status
Simulation time 328478652363 ps
CPU time 674.9 seconds
Started Dec 24 01:14:07 PM PST 23
Finished Dec 24 01:25:39 PM PST 23
Peak memory 200932 kb
Host smart-d32d6630-7ae5-4c3b-ab38-4ab2c3cf3306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433266458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.433266458
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3929869991
Short name T324
Test name
Test status
Simulation time 488071307350 ps
CPU time 1111.85 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:32:42 PM PST 23
Peak memory 200948 kb
Host smart-c8985ee7-e036-4beb-a82f-10d76cdc743e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929869991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3929869991
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3317301590
Short name T17
Test name
Test status
Simulation time 328330178757 ps
CPU time 683.85 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:25:33 PM PST 23
Peak memory 200888 kb
Host smart-6c85cc45-2ada-449c-8e06-65264d08d56b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317301590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3317301590
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.13350786
Short name T588
Test name
Test status
Simulation time 167115423216 ps
CPU time 93.18 seconds
Started Dec 24 01:13:57 PM PST 23
Finished Dec 24 01:15:36 PM PST 23
Peak memory 200892 kb
Host smart-6252d82a-53e9-4998-a82e-f0043ddba63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13350786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.13350786
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1726199139
Short name T847
Test name
Test status
Simulation time 168261430535 ps
CPU time 91.43 seconds
Started Dec 24 01:14:09 PM PST 23
Finished Dec 24 01:15:56 PM PST 23
Peak memory 200888 kb
Host smart-fb5e53d8-6f80-4bb0-bacc-ac474b964cb2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726199139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1726199139
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3117971312
Short name T145
Test name
Test status
Simulation time 500810477611 ps
CPU time 1133.43 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:33:03 PM PST 23
Peak memory 200876 kb
Host smart-9c22978e-2aa1-46e9-9ae1-e3fb046b3541
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117971312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3117971312
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.595846896
Short name T531
Test name
Test status
Simulation time 490481732435 ps
CPU time 572.66 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:23:37 PM PST 23
Peak memory 200992 kb
Host smart-d32434fc-3f41-460e-9ecc-9dd0c743efb5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595846896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.595846896
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.4059570653
Short name T512
Test name
Test status
Simulation time 144473575097 ps
CPU time 766.03 seconds
Started Dec 24 01:13:55 PM PST 23
Finished Dec 24 01:26:44 PM PST 23
Peak memory 201324 kb
Host smart-710b4b19-37e8-4bce-8860-1993a5d0f083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059570653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.4059570653
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2300387944
Short name T462
Test name
Test status
Simulation time 24190382639 ps
CPU time 58.65 seconds
Started Dec 24 01:14:07 PM PST 23
Finished Dec 24 01:15:26 PM PST 23
Peak memory 200744 kb
Host smart-6b91b02c-4bb2-432e-8bd7-4165700ae87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300387944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2300387944
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3791269827
Short name T765
Test name
Test status
Simulation time 3045405344 ps
CPU time 7.4 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:14:24 PM PST 23
Peak memory 200748 kb
Host smart-55bf2f11-900e-44a4-b625-bc809a6f8381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791269827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3791269827
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2717602261
Short name T50
Test name
Test status
Simulation time 4160952402 ps
CPU time 3.15 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:14:07 PM PST 23
Peak memory 216132 kb
Host smart-2606492a-2735-46fb-ab2e-122091fb6268
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717602261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2717602261
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3388660629
Short name T759
Test name
Test status
Simulation time 5526404839 ps
CPU time 11.44 seconds
Started Dec 24 01:14:05 PM PST 23
Finished Dec 24 01:14:32 PM PST 23
Peak memory 200736 kb
Host smart-8a8bde37-7053-4e9f-a914-98517a7a692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388660629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3388660629
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.952079573
Short name T217
Test name
Test status
Simulation time 54516060583 ps
CPU time 56.3 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:15:08 PM PST 23
Peak memory 200944 kb
Host smart-c439ebae-2c6e-4d26-8efc-30da8cb416c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952079573 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.952079573
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2201585170
Short name T180
Test name
Test status
Simulation time 362608516 ps
CPU time 0.8 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:15:04 PM PST 23
Peak memory 200684 kb
Host smart-4089605f-5eb6-4f22-b8a7-ec6b7ddbc50e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201585170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2201585170
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2288494077
Short name T728
Test name
Test status
Simulation time 168379664375 ps
CPU time 394.59 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:21:34 PM PST 23
Peak memory 200892 kb
Host smart-6da29462-c790-45e6-af05-21245bbe08b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288494077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2288494077
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2779026771
Short name T128
Test name
Test status
Simulation time 165428081226 ps
CPU time 288.37 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:20:02 PM PST 23
Peak memory 200932 kb
Host smart-ec0747ca-46e4-4c3c-a9e7-6cdb0adda747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779026771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2779026771
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3395553578
Short name T593
Test name
Test status
Simulation time 331832104340 ps
CPU time 371.42 seconds
Started Dec 24 01:14:55 PM PST 23
Finished Dec 24 01:21:32 PM PST 23
Peak memory 200880 kb
Host smart-453a0fa2-963b-466f-94a0-a0568889c0e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395553578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3395553578
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1042497854
Short name T95
Test name
Test status
Simulation time 325390151815 ps
CPU time 188.38 seconds
Started Dec 24 01:14:42 PM PST 23
Finished Dec 24 01:17:56 PM PST 23
Peak memory 200900 kb
Host smart-93d22786-5ea5-4148-ae6a-782575586454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042497854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1042497854
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3572217953
Short name T458
Test name
Test status
Simulation time 501932929983 ps
CPU time 1146.8 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:34:34 PM PST 23
Peak memory 200976 kb
Host smart-ede7b3a3-f752-42e7-8218-dbbebcacffa1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572217953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3572217953
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2592383550
Short name T119
Test name
Test status
Simulation time 496779667014 ps
CPU time 381.26 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:21:29 PM PST 23
Peak memory 200900 kb
Host smart-3a12c34b-69a0-4fc8-8a5b-dc6384a1c77f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592383550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2592383550
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3677961410
Short name T169
Test name
Test status
Simulation time 165010244026 ps
CPU time 200.77 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:18:18 PM PST 23
Peak memory 200848 kb
Host smart-7eac892f-97ec-4425-a00d-282b525cf510
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677961410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3677961410
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.356396823
Short name T359
Test name
Test status
Simulation time 128343674769 ps
CPU time 689.54 seconds
Started Dec 24 01:14:39 PM PST 23
Finished Dec 24 01:26:15 PM PST 23
Peak memory 201376 kb
Host smart-eb9b5364-45eb-4302-a7d8-f228bbad666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356396823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.356396823
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.213312019
Short name T637
Test name
Test status
Simulation time 24736553076 ps
CPU time 16.89 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:15:02 PM PST 23
Peak memory 200768 kb
Host smart-4a3c6601-2cae-4bcf-9aca-7458daa6c5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213312019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.213312019
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1831179123
Short name T722
Test name
Test status
Simulation time 3443683555 ps
CPU time 8.59 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:15:06 PM PST 23
Peak memory 200760 kb
Host smart-e24aa61d-c39f-4020-976e-86697ec4ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831179123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1831179123
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3334784990
Short name T769
Test name
Test status
Simulation time 6095915431 ps
CPU time 6.26 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:15:05 PM PST 23
Peak memory 200720 kb
Host smart-22fbab14-11e9-4d45-8f21-ee21f839de02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334784990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3334784990
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1419075144
Short name T106
Test name
Test status
Simulation time 73514948644 ps
CPU time 162.35 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:17:45 PM PST 23
Peak memory 217828 kb
Host smart-06231920-1c07-47f6-8ef3-2e597588ec70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419075144 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1419075144
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1024194478
Short name T779
Test name
Test status
Simulation time 521318428 ps
CPU time 0.87 seconds
Started Dec 24 01:14:45 PM PST 23
Finished Dec 24 01:14:55 PM PST 23
Peak memory 200624 kb
Host smart-16d9e0dc-114f-400d-9c4e-2709784c5055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024194478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1024194478
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.510555854
Short name T334
Test name
Test status
Simulation time 334735583311 ps
CPU time 407.88 seconds
Started Dec 24 01:14:44 PM PST 23
Finished Dec 24 01:21:39 PM PST 23
Peak memory 200940 kb
Host smart-49179351-df37-42b8-b741-ce23aee276dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510555854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.510555854
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1987259528
Short name T650
Test name
Test status
Simulation time 316714923322 ps
CPU time 708.95 seconds
Started Dec 24 01:15:06 PM PST 23
Finished Dec 24 01:27:19 PM PST 23
Peak memory 200952 kb
Host smart-1038ec82-a14a-478f-8676-230cc78b4c1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987259528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1987259528
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3192210290
Short name T746
Test name
Test status
Simulation time 328767497421 ps
CPU time 401.27 seconds
Started Dec 24 01:14:37 PM PST 23
Finished Dec 24 01:21:26 PM PST 23
Peak memory 200888 kb
Host smart-291b6ce3-1b20-4b94-a1ea-7f10c4964352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192210290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3192210290
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.63165909
Short name T757
Test name
Test status
Simulation time 337416792043 ps
CPU time 382.39 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:21:17 PM PST 23
Peak memory 200892 kb
Host smart-2043e779-7b10-4324-8235-d251983fc591
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=63165909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed
.63165909
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3120309908
Short name T812
Test name
Test status
Simulation time 332667976814 ps
CPU time 402.71 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:22:06 PM PST 23
Peak memory 200872 kb
Host smart-332a32a3-2697-4740-8b81-58addb487300
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120309908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3120309908
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2624687581
Short name T595
Test name
Test status
Simulation time 328573596435 ps
CPU time 199.68 seconds
Started Dec 24 01:14:55 PM PST 23
Finished Dec 24 01:18:40 PM PST 23
Peak memory 200932 kb
Host smart-e041630d-e0df-49cb-a88f-f42cef7c0504
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624687581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2624687581
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2863757707
Short name T198
Test name
Test status
Simulation time 84248626569 ps
CPU time 437.94 seconds
Started Dec 24 01:14:40 PM PST 23
Finished Dec 24 01:22:05 PM PST 23
Peak memory 201276 kb
Host smart-1eb719d3-5760-490e-b6b1-bbe2f56c38c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863757707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2863757707
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3845133725
Short name T529
Test name
Test status
Simulation time 23238405997 ps
CPU time 26.34 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:15:44 PM PST 23
Peak memory 200752 kb
Host smart-016491cf-cd91-4a8f-bcc9-855d017328f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845133725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3845133725
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3330339717
Short name T750
Test name
Test status
Simulation time 5414185387 ps
CPU time 12.15 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:15:49 PM PST 23
Peak memory 200724 kb
Host smart-a0ef3255-fc00-4ef0-b176-a5d9de877320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330339717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3330339717
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1579280224
Short name T536
Test name
Test status
Simulation time 6081050067 ps
CPU time 15.18 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:15:12 PM PST 23
Peak memory 200688 kb
Host smart-b59631b5-f639-4831-8e6e-6a48b6bda5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579280224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1579280224
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.713061158
Short name T685
Test name
Test status
Simulation time 656120493548 ps
CPU time 1421.61 seconds
Started Dec 24 01:14:53 PM PST 23
Finished Dec 24 01:38:58 PM PST 23
Peak memory 200888 kb
Host smart-469e8a65-2dd9-4e0c-a256-509205f86dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713061158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
713061158
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.740563666
Short name T774
Test name
Test status
Simulation time 77755104584 ps
CPU time 179.36 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:18:10 PM PST 23
Peak memory 217656 kb
Host smart-e1cce1ea-c548-4e1d-a9d0-907291cc905a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740563666 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.740563666
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1518535425
Short name T42
Test name
Test status
Simulation time 484536097 ps
CPU time 1.79 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:14:45 PM PST 23
Peak memory 200744 kb
Host smart-83f1af83-5e9a-4d5e-92a0-5fea18b5429f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518535425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1518535425
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4226506925
Short name T222
Test name
Test status
Simulation time 345101612418 ps
CPU time 512.53 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:23:47 PM PST 23
Peak memory 200816 kb
Host smart-50cc578e-9d56-4237-9b3c-86f7ac183584
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226506925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4226506925
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2396710382
Short name T717
Test name
Test status
Simulation time 325973388386 ps
CPU time 66.61 seconds
Started Dec 24 01:14:58 PM PST 23
Finished Dec 24 01:16:31 PM PST 23
Peak memory 200972 kb
Host smart-dedaffc7-0197-464e-8b16-7cabbe6ca230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396710382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2396710382
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2199251902
Short name T167
Test name
Test status
Simulation time 164364277570 ps
CPU time 99.61 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:16:37 PM PST 23
Peak memory 200924 kb
Host smart-95c11847-b546-4660-9b53-ce6ae1234808
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199251902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2199251902
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3287121948
Short name T260
Test name
Test status
Simulation time 330011400783 ps
CPU time 326.86 seconds
Started Dec 24 01:14:34 PM PST 23
Finished Dec 24 01:20:09 PM PST 23
Peak memory 200740 kb
Host smart-4036d7bd-22b2-449b-ab23-7c2be461007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287121948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3287121948
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1347871938
Short name T143
Test name
Test status
Simulation time 162429068928 ps
CPU time 22.42 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:15:46 PM PST 23
Peak memory 200888 kb
Host smart-73b525dd-9de7-47eb-98eb-06f5f7272f59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347871938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1347871938
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3520974406
Short name T238
Test name
Test status
Simulation time 165538706366 ps
CPU time 106.13 seconds
Started Dec 24 01:14:58 PM PST 23
Finished Dec 24 01:17:10 PM PST 23
Peak memory 200824 kb
Host smart-d039a5fc-89c9-44ea-a09a-072b508b1fe4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520974406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3520974406
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.210679919
Short name T459
Test name
Test status
Simulation time 163533797873 ps
CPU time 60.88 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:16:10 PM PST 23
Peak memory 200880 kb
Host smart-601ab2a8-8dec-4bdf-99e6-8e7d781bad90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210679919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.210679919
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2418696720
Short name T803
Test name
Test status
Simulation time 83001293346 ps
CPU time 314.1 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:19:53 PM PST 23
Peak memory 201284 kb
Host smart-6e406757-db93-46f0-8a3b-7dcf8a3965f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418696720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2418696720
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3163974993
Short name T495
Test name
Test status
Simulation time 39451443991 ps
CPU time 88.57 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:16:43 PM PST 23
Peak memory 200736 kb
Host smart-006b8691-6284-4b75-840b-e33cc480b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163974993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3163974993
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1571452099
Short name T809
Test name
Test status
Simulation time 3737450776 ps
CPU time 2.96 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:14:42 PM PST 23
Peak memory 200752 kb
Host smart-498988be-e098-4ffb-8755-8b4edf016c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571452099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1571452099
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3872259798
Short name T506
Test name
Test status
Simulation time 5934601216 ps
CPU time 15.67 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:15:29 PM PST 23
Peak memory 200664 kb
Host smart-3f0158f0-2944-4c54-b7ea-2fcf779ef96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872259798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3872259798
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1189894500
Short name T606
Test name
Test status
Simulation time 421728216 ps
CPU time 0.83 seconds
Started Dec 24 01:14:34 PM PST 23
Finished Dec 24 01:14:43 PM PST 23
Peak memory 200660 kb
Host smart-62ee0454-c665-4fd6-9192-6c43342c0ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189894500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1189894500
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2486882108
Short name T292
Test name
Test status
Simulation time 161523765547 ps
CPU time 167.9 seconds
Started Dec 24 01:14:42 PM PST 23
Finished Dec 24 01:17:36 PM PST 23
Peak memory 200936 kb
Host smart-4f76e88a-92a3-4ec3-8418-26808e27bf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486882108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2486882108
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3332064097
Short name T104
Test name
Test status
Simulation time 334905483068 ps
CPU time 348.12 seconds
Started Dec 24 01:14:33 PM PST 23
Finished Dec 24 01:20:28 PM PST 23
Peak memory 200840 kb
Host smart-2f9ef0f4-a1df-42b8-b019-1faf3aa8b705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332064097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3332064097
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1171098732
Short name T555
Test name
Test status
Simulation time 487743232775 ps
CPU time 627.55 seconds
Started Dec 24 01:14:45 PM PST 23
Finished Dec 24 01:25:20 PM PST 23
Peak memory 200876 kb
Host smart-9feef216-c422-4073-9119-a61ff59c9cbc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171098732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1171098732
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3115764797
Short name T275
Test name
Test status
Simulation time 164827865187 ps
CPU time 393.97 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:21:33 PM PST 23
Peak memory 200860 kb
Host smart-eeae5bc1-b2f0-4e73-b32e-75ec03c3ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115764797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3115764797
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1830586880
Short name T705
Test name
Test status
Simulation time 337517522711 ps
CPU time 389.58 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:21:32 PM PST 23
Peak memory 200924 kb
Host smart-56b21118-fdd3-4d19-be37-e7b7b51116ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830586880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1830586880
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.4031476584
Short name T277
Test name
Test status
Simulation time 166799035877 ps
CPU time 328.26 seconds
Started Dec 24 01:14:34 PM PST 23
Finished Dec 24 01:20:10 PM PST 23
Peak memory 200876 kb
Host smart-2f0ffed1-98f0-42be-9499-7511d0aaa2fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031476584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.4031476584
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1992588012
Short name T56
Test name
Test status
Simulation time 331732753962 ps
CPU time 780.27 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:27:55 PM PST 23
Peak memory 200900 kb
Host smart-204377a8-c3b7-4093-a762-de755dfdc43c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992588012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1992588012
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3435881206
Short name T199
Test name
Test status
Simulation time 88084445794 ps
CPU time 388.79 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:21:08 PM PST 23
Peak memory 201380 kb
Host smart-d1dfb53a-0af2-4bd9-8ca6-37cea84fd4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435881206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3435881206
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.468263133
Short name T460
Test name
Test status
Simulation time 39018624000 ps
CPU time 49.76 seconds
Started Dec 24 01:14:45 PM PST 23
Finished Dec 24 01:15:43 PM PST 23
Peak memory 200748 kb
Host smart-8703da08-6c3a-4398-99cb-014e3399ec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468263133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.468263133
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3298138692
Short name T558
Test name
Test status
Simulation time 4496950215 ps
CPU time 4 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:15:17 PM PST 23
Peak memory 200668 kb
Host smart-d99d3d26-3bb5-49c8-b61b-cf69b7be358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298138692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3298138692
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3884265165
Short name T587
Test name
Test status
Simulation time 6078103973 ps
CPU time 14.22 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:15:13 PM PST 23
Peak memory 200756 kb
Host smart-be773d14-82b5-4676-9e56-cdf7d091e471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884265165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3884265165
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2252796347
Short name T165
Test name
Test status
Simulation time 173721446308 ps
CPU time 132.39 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:17:27 PM PST 23
Peak memory 200824 kb
Host smart-b8e84e31-459f-42b9-8764-377b0768ea26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252796347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2252796347
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.27709525
Short name T738
Test name
Test status
Simulation time 82135886141 ps
CPU time 251.97 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:18:51 PM PST 23
Peak memory 217572 kb
Host smart-6dc29a6c-cef2-4cd7-a06e-9e0f9622814c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27709525 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.27709525
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3359793439
Short name T498
Test name
Test status
Simulation time 524956438 ps
CPU time 1.23 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:14:50 PM PST 23
Peak memory 200548 kb
Host smart-b62c0f28-8496-44df-8bc1-ce10f3eeb0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359793439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3359793439
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1954397178
Short name T616
Test name
Test status
Simulation time 159669888878 ps
CPU time 48.26 seconds
Started Dec 24 01:14:37 PM PST 23
Finished Dec 24 01:15:33 PM PST 23
Peak memory 200924 kb
Host smart-72cf1302-c47b-4fd5-b6f8-1688e3bdd091
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954397178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1954397178
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2050313630
Short name T764
Test name
Test status
Simulation time 162119341361 ps
CPU time 380.6 seconds
Started Dec 24 01:14:37 PM PST 23
Finished Dec 24 01:21:05 PM PST 23
Peak memory 200832 kb
Host smart-4afa4c78-1d5d-4cb9-84d3-f7fc53f0ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050313630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2050313630
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1593301389
Short name T730
Test name
Test status
Simulation time 165318366896 ps
CPU time 30.71 seconds
Started Dec 24 01:14:36 PM PST 23
Finished Dec 24 01:15:14 PM PST 23
Peak memory 200944 kb
Host smart-6150a326-d9ee-4800-8897-31e5ac423598
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593301389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1593301389
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.4055390942
Short name T819
Test name
Test status
Simulation time 161937314595 ps
CPU time 92.02 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:16:17 PM PST 23
Peak memory 200888 kb
Host smart-f0cd87f3-0778-4313-b5ae-c63f6f990822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055390942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.4055390942
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1006137131
Short name T756
Test name
Test status
Simulation time 328590593575 ps
CPU time 762.8 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:27:41 PM PST 23
Peak memory 200832 kb
Host smart-a4858e9a-a1b1-4acc-ae59-e732c922b7b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006137131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1006137131
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1055047241
Short name T127
Test name
Test status
Simulation time 160739989746 ps
CPU time 65.61 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:16:14 PM PST 23
Peak memory 200888 kb
Host smart-bcde62a0-789e-40aa-86d0-b14d0416254e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055047241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1055047241
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3849324064
Short name T548
Test name
Test status
Simulation time 169544330031 ps
CPU time 379.81 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:21:19 PM PST 23
Peak memory 200940 kb
Host smart-b18c2b98-ca26-41f2-9ce9-9e7778212a30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849324064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3849324064
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2094650134
Short name T491
Test name
Test status
Simulation time 128246608245 ps
CPU time 502.83 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:23:20 PM PST 23
Peak memory 201260 kb
Host smart-4ed72731-48f1-42c0-9e0e-8178d90a3704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094650134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2094650134
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3184758020
Short name T445
Test name
Test status
Simulation time 31358072007 ps
CPU time 25.38 seconds
Started Dec 24 01:14:45 PM PST 23
Finished Dec 24 01:15:18 PM PST 23
Peak memory 200752 kb
Host smart-8f744b7b-6421-4f38-b83d-53786bd635ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184758020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3184758020
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.349734095
Short name T736
Test name
Test status
Simulation time 3162602269 ps
CPU time 6.31 seconds
Started Dec 24 01:14:40 PM PST 23
Finished Dec 24 01:14:53 PM PST 23
Peak memory 200664 kb
Host smart-71616e18-a80c-4b8f-aacc-7fed112f6c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349734095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.349734095
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1362245717
Short name T702
Test name
Test status
Simulation time 5790870307 ps
CPU time 13.67 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:15:09 PM PST 23
Peak memory 200568 kb
Host smart-e03f2c1a-13f0-47d5-9084-866c3f5068b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362245717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1362245717
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2058813179
Short name T544
Test name
Test status
Simulation time 475889660380 ps
CPU time 658.2 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:25:53 PM PST 23
Peak memory 217684 kb
Host smart-9008063e-f956-441a-a162-7b5dd236de45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058813179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2058813179
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2017464833
Short name T294
Test name
Test status
Simulation time 134042403109 ps
CPU time 97.69 seconds
Started Dec 24 01:14:38 PM PST 23
Finished Dec 24 01:16:23 PM PST 23
Peak memory 209572 kb
Host smart-86e44f07-bdbc-4bb3-943b-66bbab9d8679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017464833 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2017464833
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2488814773
Short name T642
Test name
Test status
Simulation time 476077886 ps
CPU time 0.85 seconds
Started Dec 24 01:14:53 PM PST 23
Finished Dec 24 01:15:18 PM PST 23
Peak memory 200560 kb
Host smart-ac0d92d1-1e73-4950-b424-9c7996602d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488814773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2488814773
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3097595344
Short name T149
Test name
Test status
Simulation time 490268284512 ps
CPU time 166.44 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:17:45 PM PST 23
Peak memory 200948 kb
Host smart-f439f7cf-b6b2-4b30-8374-f8e1fb534d78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097595344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3097595344
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3198883480
Short name T53
Test name
Test status
Simulation time 162289697992 ps
CPU time 385.31 seconds
Started Dec 24 01:14:40 PM PST 23
Finished Dec 24 01:21:12 PM PST 23
Peak memory 200892 kb
Host smart-eb97d0b5-3209-4db5-a8de-31d2b562aa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198883480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3198883480
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2849702138
Short name T617
Test name
Test status
Simulation time 495426010415 ps
CPU time 531.43 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:24:05 PM PST 23
Peak memory 201008 kb
Host smart-cef47151-61b5-4d50-88bc-5c32bb03b691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849702138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2849702138
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2068590781
Short name T599
Test name
Test status
Simulation time 163180463235 ps
CPU time 106.75 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:16:42 PM PST 23
Peak memory 200356 kb
Host smart-03030682-b41d-4da1-9f03-9c6454bbdde0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068590781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2068590781
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1057453292
Short name T784
Test name
Test status
Simulation time 498171604541 ps
CPU time 302.26 seconds
Started Dec 24 01:14:33 PM PST 23
Finished Dec 24 01:19:42 PM PST 23
Peak memory 200884 kb
Host smart-1680cd6a-27c0-43cc-9d2c-f7feffca6355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057453292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1057453292
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3251741622
Short name T496
Test name
Test status
Simulation time 167065898685 ps
CPU time 53.07 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:16:02 PM PST 23
Peak memory 200896 kb
Host smart-443515c2-ec4a-4a6e-8eed-1a494a04a14e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251741622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3251741622
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4028777834
Short name T309
Test name
Test status
Simulation time 327953062177 ps
CPU time 670.41 seconds
Started Dec 24 01:14:37 PM PST 23
Finished Dec 24 01:25:55 PM PST 23
Peak memory 200884 kb
Host smart-7d5f929c-0b70-42fb-9841-6eed6ee8e348
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028777834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4028777834
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.661830959
Short name T131
Test name
Test status
Simulation time 329835620667 ps
CPU time 206.63 seconds
Started Dec 24 01:14:53 PM PST 23
Finished Dec 24 01:18:42 PM PST 23
Peak memory 200940 kb
Host smart-80ebf358-8468-4584-b57e-c156e9447b62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661830959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.661830959
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2602943907
Short name T170
Test name
Test status
Simulation time 69886433147 ps
CPU time 396.28 seconds
Started Dec 24 01:14:33 PM PST 23
Finished Dec 24 01:21:16 PM PST 23
Peak memory 201324 kb
Host smart-d0305e67-6dd8-41a6-af50-b8c88c5089bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602943907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2602943907
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2298010006
Short name T465
Test name
Test status
Simulation time 32426139628 ps
CPU time 39.41 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:15:34 PM PST 23
Peak memory 200720 kb
Host smart-5da7f16b-ce2a-4c71-a693-001efacd88a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298010006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2298010006
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.392399666
Short name T741
Test name
Test status
Simulation time 4597551487 ps
CPU time 2.6 seconds
Started Dec 24 01:14:42 PM PST 23
Finished Dec 24 01:14:51 PM PST 23
Peak memory 200764 kb
Host smart-624dcc71-6d01-495d-a921-26c0a0500074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392399666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.392399666
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2315130953
Short name T752
Test name
Test status
Simulation time 5763592389 ps
CPU time 4.06 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:15:14 PM PST 23
Peak memory 200636 kb
Host smart-da16401a-1175-4077-bb0f-209869141554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315130953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2315130953
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2591039730
Short name T351
Test name
Test status
Simulation time 37983678276 ps
CPU time 42.16 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:15:55 PM PST 23
Peak memory 200912 kb
Host smart-f004a2d9-dbbb-4d00-a1d8-51b997ef8fef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591039730 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2591039730
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.681750157
Short name T494
Test name
Test status
Simulation time 464186757 ps
CPU time 1.12 seconds
Started Dec 24 01:14:41 PM PST 23
Finished Dec 24 01:14:49 PM PST 23
Peak memory 200692 kb
Host smart-69ba86ca-5197-4342-8383-898f7033663f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681750157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.681750157
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.214426717
Short name T144
Test name
Test status
Simulation time 329628969708 ps
CPU time 178.67 seconds
Started Dec 24 01:14:55 PM PST 23
Finished Dec 24 01:18:18 PM PST 23
Peak memory 200884 kb
Host smart-2ddf6aeb-b54c-4e89-b0c6-b0ad4777d6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214426717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.214426717
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.443915039
Short name T126
Test name
Test status
Simulation time 329103585720 ps
CPU time 214.66 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:18:23 PM PST 23
Peak memory 200904 kb
Host smart-a76cba53-075d-4933-81b7-17f1ddc1433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443915039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.443915039
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.641971777
Short name T540
Test name
Test status
Simulation time 327569403260 ps
CPU time 215.12 seconds
Started Dec 24 01:14:37 PM PST 23
Finished Dec 24 01:18:20 PM PST 23
Peak memory 200824 kb
Host smart-44bcaddf-90dd-40bd-aef2-17affeda97a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=641971777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.641971777
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.146118120
Short name T693
Test name
Test status
Simulation time 491907714099 ps
CPU time 1116.6 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:33:45 PM PST 23
Peak memory 200832 kb
Host smart-4d93bdf7-83b0-47b5-ab45-4c6845953304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146118120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.146118120
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2667906760
Short name T679
Test name
Test status
Simulation time 493969608416 ps
CPU time 320.73 seconds
Started Dec 24 01:14:53 PM PST 23
Finished Dec 24 01:20:36 PM PST 23
Peak memory 200828 kb
Host smart-9503e218-ca1b-4f25-8133-b1c161b7309a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667906760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2667906760
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3305213118
Short name T146
Test name
Test status
Simulation time 494762383839 ps
CPU time 86.05 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:16:39 PM PST 23
Peak memory 200860 kb
Host smart-01b30425-4ad0-4901-a0c2-eb84de7f5fa2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305213118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3305213118
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3214065193
Short name T760
Test name
Test status
Simulation time 160660815484 ps
CPU time 196.99 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:18:25 PM PST 23
Peak memory 200840 kb
Host smart-274c17c7-d404-4197-8130-e747ffc266e7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214065193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3214065193
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1938249775
Short name T742
Test name
Test status
Simulation time 119287198107 ps
CPU time 382.09 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:21:21 PM PST 23
Peak memory 201340 kb
Host smart-6b5a7fa3-950e-4ecc-a6d3-be8f390f0c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938249775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1938249775
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3466578586
Short name T177
Test name
Test status
Simulation time 29231973786 ps
CPU time 16.05 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:15:29 PM PST 23
Peak memory 200728 kb
Host smart-6a0e1435-2d81-4971-a374-2da02071c492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466578586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3466578586
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2317385685
Short name T672
Test name
Test status
Simulation time 3691396627 ps
CPU time 8.09 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:15:26 PM PST 23
Peak memory 200752 kb
Host smart-f176c2c9-8eda-4454-b247-34cca263ee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317385685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2317385685
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1711965866
Short name T88
Test name
Test status
Simulation time 5771581476 ps
CPU time 7.13 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:15:02 PM PST 23
Peak memory 200740 kb
Host smart-babd904a-5fcd-4488-9590-d4a5254c12e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711965866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1711965866
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3067220109
Short name T545
Test name
Test status
Simulation time 36486347715 ps
CPU time 21.81 seconds
Started Dec 24 01:14:45 PM PST 23
Finished Dec 24 01:15:14 PM PST 23
Peak memory 200740 kb
Host smart-036f6082-c7ea-4855-9572-bd786666a398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067220109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3067220109
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1569383850
Short name T255
Test name
Test status
Simulation time 90034996730 ps
CPU time 204.54 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:18:04 PM PST 23
Peak memory 208912 kb
Host smart-d9791eb4-8789-4040-b9e6-8cc798af468b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569383850 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1569383850
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.590691489
Short name T671
Test name
Test status
Simulation time 399758508 ps
CPU time 1.47 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:15:01 PM PST 23
Peak memory 200568 kb
Host smart-2255caf5-388c-4e02-91a4-7cb36d51f503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590691489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.590691489
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.85224718
Short name T592
Test name
Test status
Simulation time 172228273624 ps
CPU time 123.6 seconds
Started Dec 24 01:14:33 PM PST 23
Finished Dec 24 01:16:44 PM PST 23
Peak memory 200936 kb
Host smart-ec77b184-f677-4efe-804d-a7eed91df5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85224718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.85224718
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1541320641
Short name T434
Test name
Test status
Simulation time 158990815842 ps
CPU time 99.36 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:16:39 PM PST 23
Peak memory 200888 kb
Host smart-3b0d9401-bb13-4ac5-93ab-dabe7a58acfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541320641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1541320641
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1606474457
Short name T661
Test name
Test status
Simulation time 489433817951 ps
CPU time 535.17 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:23:59 PM PST 23
Peak memory 200888 kb
Host smart-394bd55a-fe4e-40b2-8029-5da1916c4e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606474457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1606474457
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.506936082
Short name T770
Test name
Test status
Simulation time 163605254729 ps
CPU time 80.62 seconds
Started Dec 24 01:14:45 PM PST 23
Finished Dec 24 01:16:14 PM PST 23
Peak memory 200720 kb
Host smart-d1c6da34-f160-480b-9754-1eb66fb20336
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=506936082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.506936082
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3543005421
Short name T700
Test name
Test status
Simulation time 333475195674 ps
CPU time 456.19 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:22:35 PM PST 23
Peak memory 200872 kb
Host smart-c8fda61d-6320-40b3-a62e-592234c69f7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543005421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3543005421
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.548799485
Short name T527
Test name
Test status
Simulation time 71832157762 ps
CPU time 324.58 seconds
Started Dec 24 01:14:37 PM PST 23
Finished Dec 24 01:20:09 PM PST 23
Peak memory 201232 kb
Host smart-0873801f-c33e-4bc2-b3eb-2fd8473bc2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548799485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.548799485
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.4156484030
Short name T813
Test name
Test status
Simulation time 44924243037 ps
CPU time 97.94 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:16:46 PM PST 23
Peak memory 200696 kb
Host smart-78bfb1cd-caa2-45b0-b20c-ba7b60167bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156484030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.4156484030
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.833350190
Short name T799
Test name
Test status
Simulation time 4990776181 ps
CPU time 4.16 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:14:59 PM PST 23
Peak memory 200704 kb
Host smart-0b141676-0600-4ac8-a56f-acaa62e76b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833350190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.833350190
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4039945134
Short name T712
Test name
Test status
Simulation time 5959773418 ps
CPU time 14 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:15:31 PM PST 23
Peak memory 200688 kb
Host smart-daa474ad-a4a6-4c9f-9d60-bc67f3ce39c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039945134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4039945134
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3937087760
Short name T284
Test name
Test status
Simulation time 40860051213 ps
CPU time 103.79 seconds
Started Dec 24 01:14:33 PM PST 23
Finished Dec 24 01:16:25 PM PST 23
Peak memory 209652 kb
Host smart-18a5ce59-4cc0-49df-ac7f-1debba1ad6a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937087760 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3937087760
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.320964797
Short name T820
Test name
Test status
Simulation time 459297831 ps
CPU time 0.87 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:15:09 PM PST 23
Peak memory 200632 kb
Host smart-082fb7b1-8f89-4246-bd02-eeda89a9275e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320964797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.320964797
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.672671357
Short name T861
Test name
Test status
Simulation time 501612619423 ps
CPU time 936.09 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:30:44 PM PST 23
Peak memory 200852 kb
Host smart-6bb36033-d733-4571-bc8d-e9eb6315e90a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672671357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.672671357
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.855140632
Short name T655
Test name
Test status
Simulation time 329380350121 ps
CPU time 350.38 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:21:04 PM PST 23
Peak memory 200884 kb
Host smart-9ebf9655-8f4f-48b8-bb4f-08c60ebea7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855140632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.855140632
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1655555802
Short name T304
Test name
Test status
Simulation time 163369741414 ps
CPU time 207.08 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:18:23 PM PST 23
Peak memory 200988 kb
Host smart-a1e4093a-23e8-4f16-9d23-840f546dc67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655555802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1655555802
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3266997517
Short name T618
Test name
Test status
Simulation time 169163824253 ps
CPU time 101.11 seconds
Started Dec 24 01:14:45 PM PST 23
Finished Dec 24 01:16:34 PM PST 23
Peak memory 200892 kb
Host smart-614a2fbb-028c-4514-909a-a5b4f20e1e18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266997517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3266997517
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1427518390
Short name T221
Test name
Test status
Simulation time 327470104465 ps
CPU time 699.08 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:26:22 PM PST 23
Peak memory 200928 kb
Host smart-0a82159a-c779-40df-b777-0fd8743c8848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427518390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1427518390
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3042038842
Short name T849
Test name
Test status
Simulation time 494524246824 ps
CPU time 1097.9 seconds
Started Dec 24 01:14:53 PM PST 23
Finished Dec 24 01:33:34 PM PST 23
Peak memory 200864 kb
Host smart-bde21a54-57b3-447d-889b-02af22685573
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042038842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3042038842
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2026389815
Short name T338
Test name
Test status
Simulation time 161907242881 ps
CPU time 94.8 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:16:30 PM PST 23
Peak memory 200840 kb
Host smart-502b645b-7362-463d-96d8-d85fc21ebb1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026389815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2026389815
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.864117632
Short name T800
Test name
Test status
Simulation time 326879188952 ps
CPU time 795.55 seconds
Started Dec 24 01:14:39 PM PST 23
Finished Dec 24 01:28:02 PM PST 23
Peak memory 200740 kb
Host smart-83a31016-6759-4cad-8a68-6ae489358f63
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864117632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.864117632
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.4027644097
Short name T745
Test name
Test status
Simulation time 103997335632 ps
CPU time 545.63 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:23:55 PM PST 23
Peak memory 201340 kb
Host smart-c222f51f-25bf-47e5-8216-b0adc939844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027644097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.4027644097
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1214411309
Short name T763
Test name
Test status
Simulation time 43502201078 ps
CPU time 28.43 seconds
Started Dec 24 01:14:55 PM PST 23
Finished Dec 24 01:15:49 PM PST 23
Peak memory 200672 kb
Host smart-db634c74-59cd-49a1-b1c6-60ba79cc29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214411309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1214411309
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2342885469
Short name T795
Test name
Test status
Simulation time 3841818231 ps
CPU time 2.77 seconds
Started Dec 24 01:14:40 PM PST 23
Finished Dec 24 01:14:50 PM PST 23
Peak memory 200764 kb
Host smart-1bea9a8e-a709-40a3-9fce-9896462f4074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342885469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2342885469
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2644190334
Short name T662
Test name
Test status
Simulation time 5528871187 ps
CPU time 14.98 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:15:37 PM PST 23
Peak memory 200692 kb
Host smart-4057a94d-7564-47be-a249-6aba62015a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644190334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2644190334
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1362928072
Short name T680
Test name
Test status
Simulation time 9968204651 ps
CPU time 26.72 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:15:40 PM PST 23
Peak memory 200932 kb
Host smart-f06af036-9e55-4b70-9ca6-8afc88555229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362928072 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1362928072
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4051697015
Short name T476
Test name
Test status
Simulation time 351687738 ps
CPU time 0.85 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:15:11 PM PST 23
Peak memory 200596 kb
Host smart-e3417299-1ea5-4640-8225-380699f65e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051697015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4051697015
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.691459177
Short name T258
Test name
Test status
Simulation time 350763231839 ps
CPU time 756.73 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:27:45 PM PST 23
Peak memory 200948 kb
Host smart-eea14e38-9dc6-4ed0-960a-cb50481b54c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691459177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.691459177
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2211995200
Short name T699
Test name
Test status
Simulation time 486097684229 ps
CPU time 234.98 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:19:08 PM PST 23
Peak memory 200928 kb
Host smart-d5fdcde7-81c7-4a4f-9a20-19a26a4cb28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211995200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2211995200
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1588851347
Short name T342
Test name
Test status
Simulation time 163807684499 ps
CPU time 127.85 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:17:22 PM PST 23
Peak memory 200844 kb
Host smart-cf0d0d20-c7c9-43b8-a05c-c849c11ee9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588851347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1588851347
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2249246851
Short name T747
Test name
Test status
Simulation time 325807485400 ps
CPU time 236.02 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:18:54 PM PST 23
Peak memory 200824 kb
Host smart-59edbf57-e57f-4fec-80b6-2f5930189ee9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249246851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2249246851
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1564443750
Short name T689
Test name
Test status
Simulation time 486872816141 ps
CPU time 327.83 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:20:27 PM PST 23
Peak memory 200916 kb
Host smart-750f3de9-da3d-4ae7-9266-9c3ac9dc9065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564443750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1564443750
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3796073993
Short name T561
Test name
Test status
Simulation time 325971722502 ps
CPU time 233.94 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:19:04 PM PST 23
Peak memory 200900 kb
Host smart-ec5f6f6a-7960-41d6-bcb9-bc6cc42ff13f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796073993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3796073993
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1810573341
Short name T320
Test name
Test status
Simulation time 327097572172 ps
CPU time 186.92 seconds
Started Dec 24 01:14:53 PM PST 23
Finished Dec 24 01:18:22 PM PST 23
Peak memory 201000 kb
Host smart-bd14344d-ad6e-4fb9-9e15-43eb9d9748fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810573341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1810573341
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1329217267
Short name T542
Test name
Test status
Simulation time 170083733222 ps
CPU time 391.21 seconds
Started Dec 24 01:14:53 PM PST 23
Finished Dec 24 01:21:47 PM PST 23
Peak memory 200860 kb
Host smart-b4bd027d-dcf7-4a87-93e3-6acda21de095
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329217267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1329217267
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2315714724
Short name T478
Test name
Test status
Simulation time 66676173445 ps
CPU time 271.75 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:19:54 PM PST 23
Peak memory 201312 kb
Host smart-15da55db-e5fc-404e-823f-3a9043e78e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315714724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2315714724
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2792256050
Short name T718
Test name
Test status
Simulation time 31133394755 ps
CPU time 73.19 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:16:10 PM PST 23
Peak memory 200748 kb
Host smart-0780ec4a-991c-46fb-a5e6-4ee2df2c9e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792256050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2792256050
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3767272932
Short name T581
Test name
Test status
Simulation time 4055353877 ps
CPU time 2.67 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:15:00 PM PST 23
Peak memory 200752 kb
Host smart-c77a03df-fa89-4cf6-9b86-09331a761ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767272932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3767272932
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1391324866
Short name T836
Test name
Test status
Simulation time 6089114078 ps
CPU time 2.82 seconds
Started Dec 24 01:14:53 PM PST 23
Finished Dec 24 01:15:19 PM PST 23
Peak memory 200612 kb
Host smart-ead110bd-dcc8-4ab4-869b-955b1f4d95cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391324866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1391324866
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.888234700
Short name T439
Test name
Test status
Simulation time 562225281 ps
CPU time 0.82 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:14:15 PM PST 23
Peak memory 200604 kb
Host smart-cc3cb154-3a88-4d08-88b0-1c12d69cdb8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888234700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.888234700
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1955924181
Short name T316
Test name
Test status
Simulation time 169215228977 ps
CPU time 287.66 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:19:04 PM PST 23
Peak memory 200560 kb
Host smart-84fac3e8-bf84-4913-966d-b2eec820217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955924181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1955924181
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.906774756
Short name T253
Test name
Test status
Simulation time 161074531966 ps
CPU time 373.05 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:20:22 PM PST 23
Peak memory 200916 kb
Host smart-fe990d2e-16a8-4d5b-aad3-b07e7f8798cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906774756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.906774756
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.989101321
Short name T835
Test name
Test status
Simulation time 327902566493 ps
CPU time 183.4 seconds
Started Dec 24 01:14:08 PM PST 23
Finished Dec 24 01:17:31 PM PST 23
Peak memory 200828 kb
Host smart-96dfbd55-0248-4db3-a122-41862ac2281e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=989101321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.989101321
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3888955280
Short name T677
Test name
Test status
Simulation time 330229952562 ps
CPU time 691.93 seconds
Started Dec 24 01:14:07 PM PST 23
Finished Dec 24 01:25:56 PM PST 23
Peak memory 200936 kb
Host smart-e20f658a-2ab8-4dc3-a142-c1b64f19f482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888955280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3888955280
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.743594394
Short name T431
Test name
Test status
Simulation time 325989614827 ps
CPU time 707.01 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:25:53 PM PST 23
Peak memory 200708 kb
Host smart-e995f27f-2f76-478c-bff9-87b2cd21ce7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=743594394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.743594394
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3505326805
Short name T136
Test name
Test status
Simulation time 163344669081 ps
CPU time 383.58 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:20:29 PM PST 23
Peak memory 200900 kb
Host smart-0847dc43-5edf-49eb-a10d-f734a5c9cf2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505326805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3505326805
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.59761051
Short name T636
Test name
Test status
Simulation time 160172365784 ps
CPU time 156.74 seconds
Started Dec 24 01:14:05 PM PST 23
Finished Dec 24 01:16:58 PM PST 23
Peak memory 200776 kb
Host smart-10b610f2-1431-49df-8894-545713e26835
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59761051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.ad
c_ctrl_filters_wakeup_fixed.59761051
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3536830684
Short name T154
Test name
Test status
Simulation time 78359297476 ps
CPU time 288.36 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:19:04 PM PST 23
Peak memory 201376 kb
Host smart-3d804d60-52ff-421d-9dea-71a53f797cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536830684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3536830684
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.204858199
Short name T855
Test name
Test status
Simulation time 24898940037 ps
CPU time 14.93 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:14:25 PM PST 23
Peak memory 200708 kb
Host smart-90eb1b38-c526-4305-bb42-c2c91a8103bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204858199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.204858199
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.4293298839
Short name T457
Test name
Test status
Simulation time 3172658975 ps
CPU time 2.79 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:14:13 PM PST 23
Peak memory 200736 kb
Host smart-443d63ca-8455-4dab-bea9-968a499e7596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293298839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.4293298839
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2899480309
Short name T49
Test name
Test status
Simulation time 4270844999 ps
CPU time 2.78 seconds
Started Dec 24 01:13:55 PM PST 23
Finished Dec 24 01:14:01 PM PST 23
Peak memory 216012 kb
Host smart-53286d04-60fd-4eb9-ae01-868d9ea87161
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899480309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2899480309
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3548473202
Short name T635
Test name
Test status
Simulation time 5788946572 ps
CPU time 1.79 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:14:16 PM PST 23
Peak memory 200652 kb
Host smart-d1fdb3bd-c94b-4e51-87c5-46d0623014dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548473202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3548473202
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.62003078
Short name T231
Test name
Test status
Simulation time 60567469804 ps
CPU time 120.69 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:16:15 PM PST 23
Peak memory 200964 kb
Host smart-a6c15e0b-d0f6-42cc-8443-ea7038969c84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62003078 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.62003078
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1202105969
Short name T754
Test name
Test status
Simulation time 409219782 ps
CPU time 0.89 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:14:56 PM PST 23
Peak memory 200640 kb
Host smart-658a6cf1-864e-4f12-8054-701cc302859d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202105969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1202105969
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.338125083
Short name T853
Test name
Test status
Simulation time 161483872699 ps
CPU time 17.79 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:15:22 PM PST 23
Peak memory 200900 kb
Host smart-be3c6f36-cfd5-40b6-a6b0-d7b74f2ed0b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338125083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.338125083
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2073326189
Short name T843
Test name
Test status
Simulation time 165448875011 ps
CPU time 80.83 seconds
Started Dec 24 01:14:42 PM PST 23
Finished Dec 24 01:16:09 PM PST 23
Peak memory 200804 kb
Host smart-72c5181f-6450-4baf-ba8a-1551a6e10ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073326189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2073326189
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3676848610
Short name T597
Test name
Test status
Simulation time 328184234531 ps
CPU time 709.09 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:26:59 PM PST 23
Peak memory 200880 kb
Host smart-d686f96a-eb32-4bea-bda8-da2fa8da5f8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676848610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3676848610
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.899530908
Short name T298
Test name
Test status
Simulation time 330096295766 ps
CPU time 196.51 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:18:25 PM PST 23
Peak memory 200948 kb
Host smart-2157084e-8cd9-4eb5-89e7-b6c3a1546548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899530908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.899530908
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1421868554
Short name T594
Test name
Test status
Simulation time 160158992258 ps
CPU time 101.32 seconds
Started Dec 24 01:14:45 PM PST 23
Finished Dec 24 01:16:34 PM PST 23
Peak memory 200668 kb
Host smart-d7042275-8fbf-43ae-a8d9-ceedb7982643
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421868554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1421868554
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1310261120
Short name T341
Test name
Test status
Simulation time 323543290536 ps
CPU time 226.87 seconds
Started Dec 24 01:15:01 PM PST 23
Finished Dec 24 01:19:14 PM PST 23
Peak memory 200832 kb
Host smart-576c41bd-5a5c-4227-bc5f-24a1ae8ce350
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310261120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1310261120
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2618080544
Short name T692
Test name
Test status
Simulation time 165756960075 ps
CPU time 229.73 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:18:45 PM PST 23
Peak memory 200928 kb
Host smart-f14d8268-589a-47af-97e4-6d6b960e7550
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618080544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2618080544
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2115073643
Short name T361
Test name
Test status
Simulation time 143596574285 ps
CPU time 483.19 seconds
Started Dec 24 01:14:43 PM PST 23
Finished Dec 24 01:22:52 PM PST 23
Peak memory 201324 kb
Host smart-082a357e-9251-4a2b-ad5e-a85df4a9b258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115073643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2115073643
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.545879996
Short name T552
Test name
Test status
Simulation time 43886882020 ps
CPU time 51 seconds
Started Dec 24 01:14:48 PM PST 23
Finished Dec 24 01:15:49 PM PST 23
Peak memory 200704 kb
Host smart-0462b29f-f2cd-4fb0-9dcb-5a96e8bbc2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545879996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.545879996
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.14543263
Short name T440
Test name
Test status
Simulation time 4682416868 ps
CPU time 11.61 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:15:33 PM PST 23
Peak memory 200616 kb
Host smart-eeb144b2-8187-4856-9d81-a785a2a60468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14543263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.14543263
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2843156023
Short name T523
Test name
Test status
Simulation time 5725784173 ps
CPU time 13.51 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:15:27 PM PST 23
Peak memory 200684 kb
Host smart-19c47825-5177-4de0-8a0a-5b78083c32ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843156023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2843156023
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2444780156
Short name T610
Test name
Test status
Simulation time 52064734702 ps
CPU time 131.69 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:17:21 PM PST 23
Peak memory 209568 kb
Host smart-23d2ad98-df20-4dbb-baa3-36473dfd6afc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444780156 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2444780156
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3172575625
Short name T520
Test name
Test status
Simulation time 464987248 ps
CPU time 0.86 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:15:00 PM PST 23
Peak memory 200620 kb
Host smart-9692a554-d904-48f1-8d15-07f940304197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172575625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3172575625
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3410931636
Short name T796
Test name
Test status
Simulation time 326126604360 ps
CPU time 186.22 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:18:20 PM PST 23
Peak memory 200892 kb
Host smart-c0f01745-c2df-4b87-88f3-f61627f04f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410931636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3410931636
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2572636650
Short name T801
Test name
Test status
Simulation time 495570422596 ps
CPU time 136.06 seconds
Started Dec 24 01:14:46 PM PST 23
Finished Dec 24 01:17:11 PM PST 23
Peak memory 200944 kb
Host smart-5ca140d4-a686-4e64-bb51-ee93f8abf8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572636650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2572636650
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1739123650
Short name T758
Test name
Test status
Simulation time 489481778396 ps
CPU time 699.05 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:26:53 PM PST 23
Peak memory 200952 kb
Host smart-97778e52-7821-40ca-b4c6-14d23fd57055
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739123650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1739123650
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.945656463
Short name T519
Test name
Test status
Simulation time 336270927608 ps
CPU time 770.91 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:28:05 PM PST 23
Peak memory 200880 kb
Host smart-521c9e8f-0c94-4da2-8440-ca3c7034cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945656463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.945656463
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4159806996
Short name T772
Test name
Test status
Simulation time 164743780651 ps
CPU time 154.22 seconds
Started Dec 24 01:14:53 PM PST 23
Finished Dec 24 01:17:51 PM PST 23
Peak memory 200888 kb
Host smart-46db4d70-8d17-404d-9c24-3d0edf2932d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159806996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4159806996
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3352857437
Short name T162
Test name
Test status
Simulation time 500065278060 ps
CPU time 1175.95 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:34:39 PM PST 23
Peak memory 200868 kb
Host smart-e705987e-20d4-46ed-8865-d5bf29ffa3be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352857437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3352857437
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1617341613
Short name T577
Test name
Test status
Simulation time 492352595881 ps
CPU time 980.12 seconds
Started Dec 24 01:14:47 PM PST 23
Finished Dec 24 01:31:16 PM PST 23
Peak memory 200852 kb
Host smart-0fc0e2dc-fd91-42a8-86fd-5b6ef06768a5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617341613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1617341613
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2177971712
Short name T113
Test name
Test status
Simulation time 104174808607 ps
CPU time 368.98 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:21:19 PM PST 23
Peak memory 201360 kb
Host smart-1d623be7-5781-45e2-b7af-d6baf4674231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177971712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2177971712
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3461573026
Short name T830
Test name
Test status
Simulation time 44106546676 ps
CPU time 53.23 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:16:04 PM PST 23
Peak memory 200696 kb
Host smart-89ca0898-7e47-4a13-b604-494165fe6150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461573026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3461573026
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.359718615
Short name T449
Test name
Test status
Simulation time 2987652980 ps
CPU time 8.38 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:15:07 PM PST 23
Peak memory 200700 kb
Host smart-9994e88d-649e-4e9f-942f-1de1006aa328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359718615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.359718615
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2535794692
Short name T829
Test name
Test status
Simulation time 5960075779 ps
CPU time 1.46 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:15:15 PM PST 23
Peak memory 200736 kb
Host smart-c9b14269-cb20-4370-8744-ba437e5a80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535794692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2535794692
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.556365543
Short name T442
Test name
Test status
Simulation time 16274884394 ps
CPU time 38.12 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:15:37 PM PST 23
Peak memory 200684 kb
Host smart-cd25aff0-cd43-4172-a5c1-c1ab214cf04d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556365543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
556365543
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.526648096
Short name T538
Test name
Test status
Simulation time 147396361047 ps
CPU time 81.51 seconds
Started Dec 24 01:14:49 PM PST 23
Finished Dec 24 01:16:25 PM PST 23
Peak memory 209656 kb
Host smart-40e11f9b-2c63-4456-99c7-c11176e79343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526648096 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.526648096
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3282331753
Short name T706
Test name
Test status
Simulation time 400506262 ps
CPU time 0.85 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:15:24 PM PST 23
Peak memory 200676 kb
Host smart-6f3e4b6b-c123-4d85-9a08-68dd23604648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282331753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3282331753
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.445320723
Short name T771
Test name
Test status
Simulation time 162537151855 ps
CPU time 46.97 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:16:09 PM PST 23
Peak memory 200868 kb
Host smart-f2c86785-7a12-41af-93f1-5e3c73e016e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445320723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.445320723
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.764032771
Short name T247
Test name
Test status
Simulation time 164638283205 ps
CPU time 145.06 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:17:52 PM PST 23
Peak memory 200892 kb
Host smart-6e165b95-f5c2-4421-9402-dee1ce31a999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764032771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.764032771
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2115435767
Short name T621
Test name
Test status
Simulation time 161375205922 ps
CPU time 374.39 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:21:37 PM PST 23
Peak memory 200868 kb
Host smart-441e5fa8-48bf-4d92-93d2-2b167892097a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115435767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2115435767
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2694029917
Short name T726
Test name
Test status
Simulation time 497769238789 ps
CPU time 535.85 seconds
Started Dec 24 01:15:13 PM PST 23
Finished Dec 24 01:24:33 PM PST 23
Peak memory 200796 kb
Host smart-0f156757-fc3a-45c7-bf6d-ee679a7644fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694029917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2694029917
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.438106925
Short name T554
Test name
Test status
Simulation time 486869802303 ps
CPU time 1114 seconds
Started Dec 24 01:15:19 PM PST 23
Finished Dec 24 01:34:18 PM PST 23
Peak memory 200776 kb
Host smart-2ebccb50-1ae6-4396-a4f3-b13ae61a7e1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=438106925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.438106925
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3861533464
Short name T791
Test name
Test status
Simulation time 160457397422 ps
CPU time 203.75 seconds
Started Dec 24 01:15:01 PM PST 23
Finished Dec 24 01:18:51 PM PST 23
Peak memory 200936 kb
Host smart-53ddf7c9-0e69-4eaa-8c28-1f6a980dfb21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861533464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3861533464
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.863846460
Short name T481
Test name
Test status
Simulation time 322415515525 ps
CPU time 798.51 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:28:46 PM PST 23
Peak memory 200880 kb
Host smart-01a095a8-dcf9-4ddd-9573-eaf6877ccc83
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863846460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.863846460
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4022661047
Short name T668
Test name
Test status
Simulation time 88545906197 ps
CPU time 390.82 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:21:53 PM PST 23
Peak memory 201392 kb
Host smart-4fe04036-9fdb-4389-86d0-a89e2a40c90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022661047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4022661047
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3560301387
Short name T468
Test name
Test status
Simulation time 38660123454 ps
CPU time 87.43 seconds
Started Dec 24 01:14:58 PM PST 23
Finished Dec 24 01:16:51 PM PST 23
Peak memory 200820 kb
Host smart-9c772316-dac1-4664-a3b9-f01857c67eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560301387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3560301387
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4040529974
Short name T793
Test name
Test status
Simulation time 4186948629 ps
CPU time 9.79 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:15:33 PM PST 23
Peak memory 200676 kb
Host smart-0241c181-d163-4bc0-bae6-93b5983ec961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040529974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4040529974
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2846293686
Short name T729
Test name
Test status
Simulation time 5714776156 ps
CPU time 4.17 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:15:12 PM PST 23
Peak memory 200620 kb
Host smart-a7e6d7bb-1fa2-4bb8-92f1-ff017f9aa7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846293686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2846293686
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.201262439
Short name T58
Test name
Test status
Simulation time 40691790785 ps
CPU time 83.86 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:16:51 PM PST 23
Peak memory 200680 kb
Host smart-ae1254b9-9bcc-40e9-aee4-e07cc67b0867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201262439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
201262439
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2385563288
Short name T43
Test name
Test status
Simulation time 337679648 ps
CPU time 1.42 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:15:28 PM PST 23
Peak memory 200676 kb
Host smart-6918fdf5-e792-44d2-bdd5-7679e1671d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385563288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2385563288
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4019258781
Short name T183
Test name
Test status
Simulation time 336903831170 ps
CPU time 194.27 seconds
Started Dec 24 01:14:55 PM PST 23
Finished Dec 24 01:18:34 PM PST 23
Peak memory 200912 kb
Host smart-59dc0728-0548-49b8-ae30-25618a0e733c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019258781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4019258781
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3596209589
Short name T329
Test name
Test status
Simulation time 492889614326 ps
CPU time 1156.76 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:34:35 PM PST 23
Peak memory 200784 kb
Host smart-585047fe-1ed4-43d7-aa38-54caefacbfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596209589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3596209589
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3387284549
Short name T654
Test name
Test status
Simulation time 492744732888 ps
CPU time 308.84 seconds
Started Dec 24 01:15:03 PM PST 23
Finished Dec 24 01:20:36 PM PST 23
Peak memory 200932 kb
Host smart-fbbe2d48-9d59-4818-b500-50afb734d991
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387284549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3387284549
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1662435676
Short name T768
Test name
Test status
Simulation time 487545154958 ps
CPU time 274.1 seconds
Started Dec 24 01:14:58 PM PST 23
Finished Dec 24 01:19:58 PM PST 23
Peak memory 200808 kb
Host smart-21d12296-28a9-477b-95cb-3088e99ec5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662435676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1662435676
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1323317217
Short name T446
Test name
Test status
Simulation time 162945469897 ps
CPU time 345.11 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:21:12 PM PST 23
Peak memory 200864 kb
Host smart-cc86b29a-061d-49cf-b2fc-f29fde54d27f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323317217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1323317217
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.321851996
Short name T271
Test name
Test status
Simulation time 169694859884 ps
CPU time 405.83 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:21:59 PM PST 23
Peak memory 200844 kb
Host smart-957aba4c-d14e-4cb9-ae92-7a6ce599d853
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321851996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.321851996
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1196827415
Short name T818
Test name
Test status
Simulation time 337094693059 ps
CPU time 756.31 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:28:03 PM PST 23
Peak memory 200820 kb
Host smart-9068ad14-528f-40c1-80a4-2b560b4c79c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196827415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1196827415
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.649069323
Short name T210
Test name
Test status
Simulation time 100080737109 ps
CPU time 411.52 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:22:15 PM PST 23
Peak memory 201396 kb
Host smart-997f5d64-c6e6-4d73-97bd-ee8604596832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649069323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.649069323
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1665396982
Short name T502
Test name
Test status
Simulation time 41185678646 ps
CPU time 22.71 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:15:50 PM PST 23
Peak memory 200692 kb
Host smart-231b0cb9-37fd-444c-aea0-49112078d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665396982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1665396982
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1357162072
Short name T572
Test name
Test status
Simulation time 4383365730 ps
CPU time 2.91 seconds
Started Dec 24 01:15:18 PM PST 23
Finished Dec 24 01:15:46 PM PST 23
Peak memory 200688 kb
Host smart-5581a414-bcdb-4541-864c-de468d1d5ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357162072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1357162072
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1397771850
Short name T639
Test name
Test status
Simulation time 5920573941 ps
CPU time 14.65 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:15:38 PM PST 23
Peak memory 200636 kb
Host smart-240a8b32-9223-45bb-8e5a-e473c303c7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397771850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1397771850
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1362801506
Short name T300
Test name
Test status
Simulation time 467264092355 ps
CPU time 433.49 seconds
Started Dec 24 01:15:02 PM PST 23
Finished Dec 24 01:22:41 PM PST 23
Peak memory 201240 kb
Host smart-643ccd1a-a2ab-4ce4-a589-717ff6e80a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362801506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1362801506
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1383461314
Short name T627
Test name
Test status
Simulation time 296572407 ps
CPU time 1.32 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:15:20 PM PST 23
Peak memory 200556 kb
Host smart-00f82fc0-7d83-4d96-a3b1-9e42de5a9414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383461314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1383461314
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1606891427
Short name T246
Test name
Test status
Simulation time 166703688069 ps
CPU time 344.74 seconds
Started Dec 24 01:14:59 PM PST 23
Finished Dec 24 01:21:11 PM PST 23
Peak memory 200964 kb
Host smart-c6a06968-041d-4532-baff-03004969fe9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606891427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1606891427
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4075223871
Short name T846
Test name
Test status
Simulation time 496019416119 ps
CPU time 1199.44 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:35:23 PM PST 23
Peak memory 200900 kb
Host smart-973c3a40-626b-4e20-a6aa-be536b14808c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075223871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.4075223871
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.321403616
Short name T515
Test name
Test status
Simulation time 166041996925 ps
CPU time 93.62 seconds
Started Dec 24 01:15:06 PM PST 23
Finished Dec 24 01:17:03 PM PST 23
Peak memory 200776 kb
Host smart-99c5ff3e-3d6c-418e-bf41-dfecdcd7d667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321403616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.321403616
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.427556123
Short name T737
Test name
Test status
Simulation time 496381569745 ps
CPU time 222.41 seconds
Started Dec 24 01:15:01 PM PST 23
Finished Dec 24 01:19:09 PM PST 23
Peak memory 200804 kb
Host smart-2474565a-a65d-41dd-9671-75f19ec85ba3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=427556123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.427556123
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2106104919
Short name T612
Test name
Test status
Simulation time 167586551340 ps
CPU time 208.93 seconds
Started Dec 24 01:15:07 PM PST 23
Finished Dec 24 01:18:59 PM PST 23
Peak memory 200876 kb
Host smart-de91e439-cf3c-4628-9b9a-e525b83d4806
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106104919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2106104919
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3470274595
Short name T161
Test name
Test status
Simulation time 496288296725 ps
CPU time 273.76 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:19:55 PM PST 23
Peak memory 200792 kb
Host smart-1ad8c721-cf2c-48cc-8fef-04e64c0db1aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470274595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3470274595
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3234757573
Short name T200
Test name
Test status
Simulation time 70176817556 ps
CPU time 278.65 seconds
Started Dec 24 01:15:11 PM PST 23
Finished Dec 24 01:20:15 PM PST 23
Peak memory 201228 kb
Host smart-6aada06e-15ff-4bb2-942d-4f706d19e3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234757573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3234757573
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1229230914
Short name T139
Test name
Test status
Simulation time 41974596026 ps
CPU time 96.19 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:17:03 PM PST 23
Peak memory 200756 kb
Host smart-d0f1f756-25b0-46cf-a0c1-8baf1103f54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229230914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1229230914
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2057106312
Short name T479
Test name
Test status
Simulation time 4172067768 ps
CPU time 10.99 seconds
Started Dec 24 01:14:55 PM PST 23
Finished Dec 24 01:15:32 PM PST 23
Peak memory 200732 kb
Host smart-7baec067-32cb-428a-97da-53dc42104588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057106312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2057106312
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4126332242
Short name T421
Test name
Test status
Simulation time 6017432309 ps
CPU time 3.15 seconds
Started Dec 24 01:15:10 PM PST 23
Finished Dec 24 01:15:35 PM PST 23
Peak memory 200728 kb
Host smart-c5b258b4-0e6c-4c19-8994-0c4dc1353d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126332242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4126332242
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3934694143
Short name T714
Test name
Test status
Simulation time 352372929301 ps
CPU time 800.14 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:28:33 PM PST 23
Peak memory 209624 kb
Host smart-0652049c-6bb7-4116-96b2-12d255dc183c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934694143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3934694143
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.266325179
Short name T604
Test name
Test status
Simulation time 22627871420 ps
CPU time 67.91 seconds
Started Dec 24 01:14:51 PM PST 23
Finished Dec 24 01:16:20 PM PST 23
Peak memory 209600 kb
Host smart-d48b3803-c0a2-434e-8a41-7a03b900323a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266325179 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.266325179
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1870079130
Short name T652
Test name
Test status
Simulation time 443161000 ps
CPU time 1.61 seconds
Started Dec 24 01:14:50 PM PST 23
Finished Dec 24 01:15:11 PM PST 23
Peak memory 200628 kb
Host smart-1eefecc4-943a-4952-b0e3-3e3eef10e100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870079130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1870079130
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.686302739
Short name T273
Test name
Test status
Simulation time 513574066188 ps
CPU time 276.1 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:20:03 PM PST 23
Peak memory 200800 kb
Host smart-0b5e6da5-50fe-4dab-bd3c-ba2fc51aec2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686302739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.686302739
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.86151786
Short name T225
Test name
Test status
Simulation time 339068417677 ps
CPU time 87.82 seconds
Started Dec 24 01:15:13 PM PST 23
Finished Dec 24 01:17:05 PM PST 23
Peak memory 200844 kb
Host smart-2683f183-5f3d-4f51-b159-c5b14d7758f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86151786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.86151786
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3704263601
Short name T482
Test name
Test status
Simulation time 326948305989 ps
CPU time 213.15 seconds
Started Dec 24 01:14:58 PM PST 23
Finished Dec 24 01:18:57 PM PST 23
Peak memory 200948 kb
Host smart-1cb8e1d5-c6ca-4fcc-82bc-4e304dbc2670
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704263601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3704263601
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2820696599
Short name T24
Test name
Test status
Simulation time 326377157516 ps
CPU time 719.18 seconds
Started Dec 24 01:14:58 PM PST 23
Finished Dec 24 01:27:23 PM PST 23
Peak memory 200948 kb
Host smart-e09fb124-7033-4747-92cf-f15c227ca25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820696599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2820696599
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2724086466
Short name T517
Test name
Test status
Simulation time 324234756323 ps
CPU time 389.34 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:21:44 PM PST 23
Peak memory 200956 kb
Host smart-750f657f-c2d4-44f3-99b0-08b79bc502a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724086466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2724086466
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3511006753
Short name T580
Test name
Test status
Simulation time 501838215257 ps
CPU time 307.26 seconds
Started Dec 24 01:15:01 PM PST 23
Finished Dec 24 01:20:34 PM PST 23
Peak memory 200896 kb
Host smart-317a2e18-b592-4d52-8aa3-d7653bfb1a90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511006753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3511006753
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1873250402
Short name T601
Test name
Test status
Simulation time 84864654048 ps
CPU time 481.82 seconds
Started Dec 24 01:15:08 PM PST 23
Finished Dec 24 01:23:32 PM PST 23
Peak memory 201272 kb
Host smart-ed6b86fd-b420-4212-81a5-e34206ef8523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873250402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1873250402
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2838596008
Short name T783
Test name
Test status
Simulation time 30921114365 ps
CPU time 12.13 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:15:36 PM PST 23
Peak memory 200684 kb
Host smart-9e1a7198-3868-45e0-8a9a-f58ff3bf34e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838596008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2838596008
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2276613089
Short name T563
Test name
Test status
Simulation time 5283544888 ps
CPU time 6.79 seconds
Started Dec 24 01:15:01 PM PST 23
Finished Dec 24 01:15:34 PM PST 23
Peak memory 200680 kb
Host smart-1092761b-9828-4a51-9ec5-640094c1ba1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276613089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2276613089
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3092637767
Short name T568
Test name
Test status
Simulation time 5685555775 ps
CPU time 4.36 seconds
Started Dec 24 01:14:59 PM PST 23
Finished Dec 24 01:15:30 PM PST 23
Peak memory 200692 kb
Host smart-8e972b9e-1b3c-457d-ad5a-94fa0cfa5530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092637767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3092637767
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2071252493
Short name T626
Test name
Test status
Simulation time 27820038999 ps
CPU time 108.34 seconds
Started Dec 24 01:15:08 PM PST 23
Finished Dec 24 01:17:20 PM PST 23
Peak memory 201352 kb
Host smart-cfc57e59-9c6d-43cf-8893-b3b90db2eee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071252493 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2071252493
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2957217049
Short name T437
Test name
Test status
Simulation time 444069751 ps
CPU time 1.55 seconds
Started Dec 24 01:14:59 PM PST 23
Finished Dec 24 01:15:28 PM PST 23
Peak memory 200680 kb
Host smart-5b2d3a8e-43b9-45d0-8298-64035bda4ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957217049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2957217049
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.230213919
Short name T269
Test name
Test status
Simulation time 498071057473 ps
CPU time 529.93 seconds
Started Dec 24 01:14:59 PM PST 23
Finished Dec 24 01:24:15 PM PST 23
Peak memory 200900 kb
Host smart-bea59f30-c302-4902-bd36-e5f3c5f02d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230213919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.230213919
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3675529071
Short name T418
Test name
Test status
Simulation time 159202872660 ps
CPU time 376.51 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:21:43 PM PST 23
Peak memory 200760 kb
Host smart-1ff8adae-998d-4d63-8ca5-c49e6c34cf38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675529071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3675529071
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.700982738
Short name T175
Test name
Test status
Simulation time 332573570704 ps
CPU time 168.62 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:18:10 PM PST 23
Peak memory 200988 kb
Host smart-a94af260-1171-4328-8ced-b6dee5ad2c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700982738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.700982738
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1396344358
Short name T130
Test name
Test status
Simulation time 166837823364 ps
CPU time 393.28 seconds
Started Dec 24 01:15:03 PM PST 23
Finished Dec 24 01:22:02 PM PST 23
Peak memory 200900 kb
Host smart-2098e10a-4c78-4828-a158-0ea50fe2c219
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396344358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1396344358
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1223002296
Short name T256
Test name
Test status
Simulation time 496986591857 ps
CPU time 1137.55 seconds
Started Dec 24 01:15:03 PM PST 23
Finished Dec 24 01:34:25 PM PST 23
Peak memory 200904 kb
Host smart-9387faca-b729-4433-b737-2369210a42f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223002296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1223002296
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.38870655
Short name T716
Test name
Test status
Simulation time 169374101416 ps
CPU time 184.15 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:18:26 PM PST 23
Peak memory 200936 kb
Host smart-a2c14de7-5d89-4707-9605-63a9c6aebf4e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38870655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.a
dc_ctrl_filters_wakeup_fixed.38870655
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.819672077
Short name T551
Test name
Test status
Simulation time 138360638430 ps
CPU time 679.76 seconds
Started Dec 24 01:15:03 PM PST 23
Finished Dec 24 01:26:49 PM PST 23
Peak memory 201336 kb
Host smart-8275107c-ed33-4e39-a114-c3abc5be79f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819672077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.819672077
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.714859092
Short name T657
Test name
Test status
Simulation time 41614437687 ps
CPU time 89.14 seconds
Started Dec 24 01:14:59 PM PST 23
Finished Dec 24 01:16:54 PM PST 23
Peak memory 200752 kb
Host smart-3c4a9648-63b3-4c2c-9365-96d224cbf696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714859092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.714859092
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1293599517
Short name T486
Test name
Test status
Simulation time 2918837642 ps
CPU time 1.98 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:15:24 PM PST 23
Peak memory 200748 kb
Host smart-5b8b7991-b102-45dc-a4b4-72231aa90687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293599517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1293599517
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.4117734104
Short name T651
Test name
Test status
Simulation time 5681385575 ps
CPU time 4.72 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:15:27 PM PST 23
Peak memory 200640 kb
Host smart-e4094262-d486-4be8-92dc-2723f98cff53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117734104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4117734104
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.939977455
Short name T858
Test name
Test status
Simulation time 329868545854 ps
CPU time 395.51 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:21:59 PM PST 23
Peak memory 200856 kb
Host smart-1370bf87-34b8-47fe-9dac-7085fa7eb5da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939977455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
939977455
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2486060177
Short name T213
Test name
Test status
Simulation time 10891321010 ps
CPU time 18.08 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:15:45 PM PST 23
Peak memory 201556 kb
Host smart-3d9b938a-42b0-4505-b610-79075cef13fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486060177 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2486060177
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2755480758
Short name T511
Test name
Test status
Simulation time 426420807 ps
CPU time 1.59 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:15:20 PM PST 23
Peak memory 200648 kb
Host smart-07d96bf2-03b0-4c53-910c-0d933bd282f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755480758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2755480758
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1379312919
Short name T20
Test name
Test status
Simulation time 160832400925 ps
CPU time 319.21 seconds
Started Dec 24 01:14:57 PM PST 23
Finished Dec 24 01:20:43 PM PST 23
Peak memory 200936 kb
Host smart-1e70fa27-7d2b-48b5-b204-c035f76936b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379312919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1379312919
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2579431764
Short name T499
Test name
Test status
Simulation time 162602347416 ps
CPU time 377.72 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:21:39 PM PST 23
Peak memory 200872 kb
Host smart-8ed22bd4-6d00-41d1-baaf-1deb9977ee18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579431764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2579431764
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2691813285
Short name T559
Test name
Test status
Simulation time 162421820016 ps
CPU time 90.94 seconds
Started Dec 24 01:15:18 PM PST 23
Finished Dec 24 01:17:14 PM PST 23
Peak memory 200828 kb
Host smart-bb706353-c5ac-4369-8d88-b14d446a8003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691813285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2691813285
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.711166005
Short name T789
Test name
Test status
Simulation time 500767446776 ps
CPU time 91.2 seconds
Started Dec 24 01:15:07 PM PST 23
Finished Dec 24 01:17:01 PM PST 23
Peak memory 200952 kb
Host smart-22d07e57-1093-43c2-ac48-be518a1b5042
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=711166005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.711166005
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1967328428
Short name T709
Test name
Test status
Simulation time 325366076202 ps
CPU time 400.12 seconds
Started Dec 24 01:14:55 PM PST 23
Finished Dec 24 01:21:59 PM PST 23
Peak memory 200896 kb
Host smart-7227652b-f19c-4105-b37d-0e202f964f37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967328428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1967328428
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3761593690
Short name T632
Test name
Test status
Simulation time 487673887337 ps
CPU time 1163.62 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:34:46 PM PST 23
Peak memory 200844 kb
Host smart-6e0d4d62-3f23-468a-a444-256ec7fd466a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761593690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3761593690
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3185018510
Short name T644
Test name
Test status
Simulation time 83114867190 ps
CPU time 251.95 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:19:39 PM PST 23
Peak memory 201256 kb
Host smart-65ed49e0-56dc-464a-8717-5b0f08685a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185018510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3185018510
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1322387276
Short name T455
Test name
Test status
Simulation time 40172994073 ps
CPU time 13.22 seconds
Started Dec 24 01:14:54 PM PST 23
Finished Dec 24 01:15:31 PM PST 23
Peak memory 200688 kb
Host smart-49b5c2c3-987c-4195-ab42-b84e20cefb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322387276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1322387276
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1736942127
Short name T571
Test name
Test status
Simulation time 4127602026 ps
CPU time 8.79 seconds
Started Dec 24 01:15:01 PM PST 23
Finished Dec 24 01:15:36 PM PST 23
Peak memory 200676 kb
Host smart-2c7c52e4-1661-41c7-bccd-71f92f83e569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736942127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1736942127
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3284155895
Short name T625
Test name
Test status
Simulation time 5681830522 ps
CPU time 15.66 seconds
Started Dec 24 01:15:09 PM PST 23
Finished Dec 24 01:15:47 PM PST 23
Peak memory 200732 kb
Host smart-b7b37c58-1482-4415-ba1f-788ed77065c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284155895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3284155895
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3934214480
Short name T336
Test name
Test status
Simulation time 46511463862 ps
CPU time 99.06 seconds
Started Dec 24 01:15:02 PM PST 23
Finished Dec 24 01:17:06 PM PST 23
Peak memory 209540 kb
Host smart-8e9fa2cd-5cd8-493f-b9e9-932bc312c2ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934214480 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3934214480
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.74915009
Short name T428
Test name
Test status
Simulation time 294093184 ps
CPU time 1.26 seconds
Started Dec 24 01:15:02 PM PST 23
Finished Dec 24 01:15:28 PM PST 23
Peak memory 200680 kb
Host smart-68668ad5-cd75-48ac-818f-d37d351aaea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74915009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.74915009
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.809607638
Short name T220
Test name
Test status
Simulation time 165984952962 ps
CPU time 381.24 seconds
Started Dec 24 01:14:52 PM PST 23
Finished Dec 24 01:21:36 PM PST 23
Peak memory 200844 kb
Host smart-4f9d16c3-6bd0-4f7b-98f4-abb965b1983f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809607638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.809607638
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2631124091
Short name T631
Test name
Test status
Simulation time 167932104366 ps
CPU time 209.53 seconds
Started Dec 24 01:15:00 PM PST 23
Finished Dec 24 01:18:56 PM PST 23
Peak memory 200768 kb
Host smart-c372217e-e752-498d-bf79-0080fa7de797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631124091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2631124091
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1818307696
Short name T583
Test name
Test status
Simulation time 326636471666 ps
CPU time 791.3 seconds
Started Dec 24 01:14:59 PM PST 23
Finished Dec 24 01:28:37 PM PST 23
Peak memory 200880 kb
Host smart-20f4a3b6-aa19-457e-8768-6fa40b37623f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818307696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1818307696
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3811170802
Short name T488
Test name
Test status
Simulation time 494338086375 ps
CPU time 160.59 seconds
Started Dec 24 01:15:08 PM PST 23
Finished Dec 24 01:18:11 PM PST 23
Peak memory 200940 kb
Host smart-a3b32d78-7c05-4973-8fa4-35f6f8728b8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811170802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3811170802
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1842109426
Short name T549
Test name
Test status
Simulation time 486321700680 ps
CPU time 275.06 seconds
Started Dec 24 01:15:07 PM PST 23
Finished Dec 24 01:20:05 PM PST 23
Peak memory 200776 kb
Host smart-10b04f85-ceff-4c42-8c53-8b88e3df93a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842109426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1842109426
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2719656030
Short name T826
Test name
Test status
Simulation time 135512612550 ps
CPU time 515.98 seconds
Started Dec 24 01:15:09 PM PST 23
Finished Dec 24 01:24:07 PM PST 23
Peak memory 201380 kb
Host smart-ace3bea7-35de-451a-8197-8bdfbde03d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719656030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2719656030
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1789519905
Short name T513
Test name
Test status
Simulation time 34266285851 ps
CPU time 12.32 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:15:49 PM PST 23
Peak memory 200656 kb
Host smart-36668cbd-7f46-41a9-8807-48f79a922913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789519905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1789519905
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3514705645
Short name T57
Test name
Test status
Simulation time 4725235285 ps
CPU time 3.71 seconds
Started Dec 24 01:15:13 PM PST 23
Finished Dec 24 01:15:41 PM PST 23
Peak memory 200668 kb
Host smart-5215ae64-db38-46f2-a7ab-0f5245f67b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514705645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3514705645
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2983979126
Short name T670
Test name
Test status
Simulation time 5767105963 ps
CPU time 14.04 seconds
Started Dec 24 01:14:56 PM PST 23
Finished Dec 24 01:15:36 PM PST 23
Peak memory 200632 kb
Host smart-f00b3c80-2332-49ff-bb63-98c4d987861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983979126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2983979126
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2847568395
Short name T767
Test name
Test status
Simulation time 178889713623 ps
CPU time 49.7 seconds
Started Dec 24 01:14:59 PM PST 23
Finished Dec 24 01:16:15 PM PST 23
Peak memory 200776 kb
Host smart-1ccb4d08-b685-4a78-903f-22d4605b5769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847568395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2847568395
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1881470497
Short name T86
Test name
Test status
Simulation time 68851854670 ps
CPU time 170.76 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:18:27 PM PST 23
Peak memory 209188 kb
Host smart-774a4aa1-cb5a-4be4-a28b-2ecafe0d5434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881470497 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1881470497
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1111754875
Short name T567
Test name
Test status
Simulation time 448775673 ps
CPU time 0.88 seconds
Started Dec 24 01:15:08 PM PST 23
Finished Dec 24 01:15:31 PM PST 23
Peak memory 200572 kb
Host smart-90334898-96f5-40d9-9d23-df7a10c4d2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111754875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1111754875
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2962513206
Short name T532
Test name
Test status
Simulation time 158298349063 ps
CPU time 345.95 seconds
Started Dec 24 01:15:18 PM PST 23
Finished Dec 24 01:21:29 PM PST 23
Peak memory 200968 kb
Host smart-3c2815ee-af8f-4cc3-a9bb-35016296a9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962513206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2962513206
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.699366140
Short name T280
Test name
Test status
Simulation time 493342493488 ps
CPU time 1198.47 seconds
Started Dec 24 01:15:14 PM PST 23
Finished Dec 24 01:35:39 PM PST 23
Peak memory 200752 kb
Host smart-fd8fe39b-2ce8-4739-b846-6aecf8f9fba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699366140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.699366140
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.711060442
Short name T735
Test name
Test status
Simulation time 171749159596 ps
CPU time 412.46 seconds
Started Dec 24 01:15:25 PM PST 23
Finished Dec 24 01:22:42 PM PST 23
Peak memory 200776 kb
Host smart-900da072-2f6b-4765-b02e-ac2b8b97dedf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=711060442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.711060442
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1831562189
Short name T327
Test name
Test status
Simulation time 327826810811 ps
CPU time 719.87 seconds
Started Dec 24 01:15:15 PM PST 23
Finished Dec 24 01:27:41 PM PST 23
Peak memory 200876 kb
Host smart-3be76ee9-a9b8-4f7a-9555-7c82798147ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831562189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1831562189
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1556788401
Short name T673
Test name
Test status
Simulation time 326447770728 ps
CPU time 149.62 seconds
Started Dec 24 01:15:19 PM PST 23
Finished Dec 24 01:18:13 PM PST 23
Peak memory 200828 kb
Host smart-b1f81f60-80e0-470c-a60e-6aa469c5ac90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556788401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1556788401
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2370019056
Short name T611
Test name
Test status
Simulation time 164274773181 ps
CPU time 201.29 seconds
Started Dec 24 01:15:18 PM PST 23
Finished Dec 24 01:19:04 PM PST 23
Peak memory 200892 kb
Host smart-5415b756-e3bc-4c32-a02d-911d404a047f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370019056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2370019056
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.913767304
Short name T550
Test name
Test status
Simulation time 168023609139 ps
CPU time 378.31 seconds
Started Dec 24 01:15:24 PM PST 23
Finished Dec 24 01:22:06 PM PST 23
Peak memory 200832 kb
Host smart-ac34b7b7-0b7a-4417-b681-8dadfc576aa8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913767304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.913767304
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.4068856270
Short name T195
Test name
Test status
Simulation time 110349796960 ps
CPU time 559.47 seconds
Started Dec 24 01:15:21 PM PST 23
Finished Dec 24 01:25:04 PM PST 23
Peak memory 201332 kb
Host smart-d01587c8-710b-4ad0-9c27-fac5c341dc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068856270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.4068856270
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2016195489
Short name T158
Test name
Test status
Simulation time 46419723140 ps
CPU time 101.34 seconds
Started Dec 24 01:15:09 PM PST 23
Finished Dec 24 01:17:13 PM PST 23
Peak memory 199792 kb
Host smart-2393cd67-663b-413f-a4dd-df6366567547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016195489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2016195489
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1535975792
Short name T420
Test name
Test status
Simulation time 3478179756 ps
CPU time 8.38 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:15:45 PM PST 23
Peak memory 200712 kb
Host smart-03484573-f815-473f-8b4c-48656266e8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535975792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1535975792
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.730443379
Short name T129
Test name
Test status
Simulation time 5740622969 ps
CPU time 3.55 seconds
Started Dec 24 01:15:05 PM PST 23
Finished Dec 24 01:15:33 PM PST 23
Peak memory 200640 kb
Host smart-dffc66c6-013e-4894-ba8d-5ffe410d927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730443379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.730443379
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2653297389
Short name T674
Test name
Test status
Simulation time 88278521510 ps
CPU time 169.47 seconds
Started Dec 24 01:15:14 PM PST 23
Finished Dec 24 01:18:30 PM PST 23
Peak memory 212632 kb
Host smart-7712a067-ed11-4bd1-a588-cf69be9a7589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653297389 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2653297389
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1758232702
Short name T510
Test name
Test status
Simulation time 401146507 ps
CPU time 0.74 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:14:14 PM PST 23
Peak memory 200620 kb
Host smart-9fe5b6b2-2d7a-4a25-a61a-5a26e88379e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758232702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1758232702
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2193328243
Short name T647
Test name
Test status
Simulation time 486762622823 ps
CPU time 772.75 seconds
Started Dec 24 01:14:21 PM PST 23
Finished Dec 24 01:27:26 PM PST 23
Peak memory 200892 kb
Host smart-d455675d-3c5c-43db-8e35-245d27762737
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193328243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2193328243
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2133234586
Short name T293
Test name
Test status
Simulation time 527636821453 ps
CPU time 294.23 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:19:21 PM PST 23
Peak memory 200992 kb
Host smart-9a8c29df-fbdb-4513-a27d-19905d3fa97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133234586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2133234586
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2053271520
Short name T303
Test name
Test status
Simulation time 326982670643 ps
CPU time 766.95 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:27:07 PM PST 23
Peak memory 200956 kb
Host smart-11b00fe4-9632-4d48-a51e-150d322bc678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053271520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2053271520
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2920345545
Short name T665
Test name
Test status
Simulation time 328383140094 ps
CPU time 789.15 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:27:13 PM PST 23
Peak memory 200892 kb
Host smart-0c827e5f-1ab8-4286-b114-b6f1bf6862c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920345545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2920345545
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4066069804
Short name T132
Test name
Test status
Simulation time 487126426847 ps
CPU time 355.24 seconds
Started Dec 24 01:14:19 PM PST 23
Finished Dec 24 01:20:27 PM PST 23
Peak memory 200884 kb
Host smart-e26f058d-f1b0-465c-9e0f-d7a8efd11b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066069804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4066069804
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2779737793
Short name T802
Test name
Test status
Simulation time 162357109219 ps
CPU time 67.38 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:15:21 PM PST 23
Peak memory 200776 kb
Host smart-4a15803e-54d1-4cc5-ba64-a986f2c9d149
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779737793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2779737793
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.4051264256
Short name T173
Test name
Test status
Simulation time 485171333375 ps
CPU time 214.23 seconds
Started Dec 24 01:14:05 PM PST 23
Finished Dec 24 01:17:55 PM PST 23
Peak memory 200968 kb
Host smart-91e07604-98d6-4169-8ed2-08b51fc99bd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051264256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.4051264256
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.809605104
Short name T524
Test name
Test status
Simulation time 495592703558 ps
CPU time 1211.6 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:34:38 PM PST 23
Peak memory 200872 kb
Host smart-4abea3df-c5f7-446f-9ffc-0b83e186e689
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809605104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.809605104
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.945520083
Short name T360
Test name
Test status
Simulation time 138412563733 ps
CPU time 464.46 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:22:03 PM PST 23
Peak memory 201312 kb
Host smart-76fafa60-2aab-4cce-98e5-38f9ef0f5af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945520083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.945520083
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2900452047
Short name T521
Test name
Test status
Simulation time 26486960724 ps
CPU time 63.73 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:15:19 PM PST 23
Peak memory 200748 kb
Host smart-e9f41354-d8c9-4ff0-882f-9678a1e48155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900452047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2900452047
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1989419057
Short name T708
Test name
Test status
Simulation time 4754969092 ps
CPU time 12.21 seconds
Started Dec 24 01:14:07 PM PST 23
Finished Dec 24 01:14:35 PM PST 23
Peak memory 200744 kb
Host smart-a81abd10-60d5-4809-b732-b6e47fa85210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989419057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1989419057
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.388581835
Short name T450
Test name
Test status
Simulation time 5938676979 ps
CPU time 1.72 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:14:08 PM PST 23
Peak memory 200660 kb
Host smart-c67ee9f5-1532-4031-9119-1f69a30518de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388581835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.388581835
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2097341928
Short name T471
Test name
Test status
Simulation time 12461018557 ps
CPU time 30.53 seconds
Started Dec 24 01:14:13 PM PST 23
Finished Dec 24 01:14:59 PM PST 23
Peak memory 200868 kb
Host smart-22d1f8ff-9896-4366-b352-88cb3caa9736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097341928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2097341928
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.982691250
Short name T690
Test name
Test status
Simulation time 58528457437 ps
CPU time 135.85 seconds
Started Dec 24 01:14:23 PM PST 23
Finished Dec 24 01:16:49 PM PST 23
Peak memory 209572 kb
Host smart-19cbf96d-03b6-4d9a-99c1-8463d168a020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982691250 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.982691250
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3076785751
Short name T575
Test name
Test status
Simulation time 503021048 ps
CPU time 0.67 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:15:48 PM PST 23
Peak memory 200668 kb
Host smart-5ece4f83-a531-42cc-884d-9d75b96b709a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076785751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3076785751
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1122427810
Short name T534
Test name
Test status
Simulation time 331846721812 ps
CPU time 196.37 seconds
Started Dec 24 01:15:19 PM PST 23
Finished Dec 24 01:19:00 PM PST 23
Peak memory 200872 kb
Host smart-40769bc5-3056-49be-b105-f70acdd26190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122427810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1122427810
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2085388672
Short name T857
Test name
Test status
Simulation time 489536781618 ps
CPU time 253.06 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:20:00 PM PST 23
Peak memory 200948 kb
Host smart-5b1153f3-72f7-4a5e-951b-5ef27b67ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085388672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2085388672
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.417733016
Short name T546
Test name
Test status
Simulation time 489065427351 ps
CPU time 1181.48 seconds
Started Dec 24 01:15:20 PM PST 23
Finished Dec 24 01:35:26 PM PST 23
Peak memory 200916 kb
Host smart-2cc13247-bbca-4873-8b7e-453d2ae5f310
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=417733016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.417733016
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2437674113
Short name T266
Test name
Test status
Simulation time 166423501735 ps
CPU time 371.11 seconds
Started Dec 24 01:15:08 PM PST 23
Finished Dec 24 01:21:43 PM PST 23
Peak memory 200800 kb
Host smart-7bd92297-895c-4ad2-b40c-440adaca1617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437674113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2437674113
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2852916760
Short name T114
Test name
Test status
Simulation time 329917530032 ps
CPU time 54.43 seconds
Started Dec 24 01:15:07 PM PST 23
Finished Dec 24 01:16:24 PM PST 23
Peak memory 200852 kb
Host smart-87504a2e-e4f3-49f0-9589-1c01939f9756
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852916760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2852916760
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1153815864
Short name T135
Test name
Test status
Simulation time 495721495797 ps
CPU time 182.54 seconds
Started Dec 24 01:15:08 PM PST 23
Finished Dec 24 01:18:33 PM PST 23
Peak memory 200968 kb
Host smart-609d529a-7db6-4df0-8859-8613c91e334d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153815864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1153815864
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2434608555
Short name T751
Test name
Test status
Simulation time 488121562500 ps
CPU time 597.11 seconds
Started Dec 24 01:15:07 PM PST 23
Finished Dec 24 01:25:27 PM PST 23
Peak memory 201012 kb
Host smart-3e67beb1-20c5-4ecb-8494-eb678934f9e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434608555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2434608555
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.266529708
Short name T38
Test name
Test status
Simulation time 75780376807 ps
CPU time 242.11 seconds
Started Dec 24 01:15:16 PM PST 23
Finished Dec 24 01:19:44 PM PST 23
Peak memory 201344 kb
Host smart-7ff8ac66-593e-475f-b696-2dde199e4112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266529708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.266529708
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3218657570
Short name T687
Test name
Test status
Simulation time 40811150529 ps
CPU time 23.65 seconds
Started Dec 24 01:15:16 PM PST 23
Finished Dec 24 01:16:05 PM PST 23
Peak memory 200728 kb
Host smart-6d0943f7-3321-46d4-a350-ad1fb06fff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218657570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3218657570
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1138595612
Short name T698
Test name
Test status
Simulation time 5096782414 ps
CPU time 3.97 seconds
Started Dec 24 01:15:22 PM PST 23
Finished Dec 24 01:15:50 PM PST 23
Peak memory 200668 kb
Host smart-bd9907d5-5423-47d2-bca7-f1a630e1083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138595612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1138595612
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2212960931
Short name T436
Test name
Test status
Simulation time 6075873811 ps
CPU time 1.68 seconds
Started Dec 24 01:15:19 PM PST 23
Finished Dec 24 01:15:45 PM PST 23
Peak memory 200572 kb
Host smart-6592c769-221f-4b75-8e0c-0986e48d18b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212960931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2212960931
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2696853032
Short name T236
Test name
Test status
Simulation time 345140686154 ps
CPU time 167.02 seconds
Started Dec 24 01:15:19 PM PST 23
Finished Dec 24 01:18:31 PM PST 23
Peak memory 209048 kb
Host smart-a0c3c586-1d7a-4989-9084-e01dff4cd3fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696853032 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2696853032
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1140817033
Short name T844
Test name
Test status
Simulation time 324429542 ps
CPU time 0.8 seconds
Started Dec 24 01:15:17 PM PST 23
Finished Dec 24 01:15:43 PM PST 23
Peak memory 200620 kb
Host smart-305587ae-c96f-47c8-9cbb-4e529aaa33ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140817033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1140817033
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3306875128
Short name T312
Test name
Test status
Simulation time 486609916167 ps
CPU time 1213 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:36:00 PM PST 23
Peak memory 200828 kb
Host smart-86884a34-a134-49db-a665-4ac980aa39b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306875128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3306875128
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3459080042
Short name T229
Test name
Test status
Simulation time 332948322759 ps
CPU time 397.22 seconds
Started Dec 24 01:15:08 PM PST 23
Finished Dec 24 01:22:07 PM PST 23
Peak memory 200896 kb
Host smart-ff9deb40-8625-44e3-bf42-a5d0de8201ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459080042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3459080042
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1829593651
Short name T276
Test name
Test status
Simulation time 479035726998 ps
CPU time 1139.55 seconds
Started Dec 24 01:15:07 PM PST 23
Finished Dec 24 01:34:30 PM PST 23
Peak memory 200900 kb
Host smart-b95ae27f-79ac-4086-9258-64b1f02baa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829593651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1829593651
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2904885520
Short name T678
Test name
Test status
Simulation time 163778884123 ps
CPU time 39.68 seconds
Started Dec 24 01:15:13 PM PST 23
Finished Dec 24 01:16:17 PM PST 23
Peak memory 200856 kb
Host smart-8067c35b-8fe2-4ce1-b5a8-45147f3fb77a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904885520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2904885520
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1715766951
Short name T118
Test name
Test status
Simulation time 492195317178 ps
CPU time 1095.18 seconds
Started Dec 24 01:15:10 PM PST 23
Finished Dec 24 01:33:47 PM PST 23
Peak memory 200880 kb
Host smart-bdcde8e4-58c6-41b2-975a-a10565082c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715766951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1715766951
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.4211877722
Short name T463
Test name
Test status
Simulation time 496598782458 ps
CPU time 110.35 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:17:37 PM PST 23
Peak memory 200860 kb
Host smart-5d3f43ef-aefc-4655-861a-384fcf5a1565
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211877722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.4211877722
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1971261469
Short name T108
Test name
Test status
Simulation time 329581245675 ps
CPU time 691.63 seconds
Started Dec 24 01:15:08 PM PST 23
Finished Dec 24 01:27:02 PM PST 23
Peak memory 200932 kb
Host smart-733d9059-ce2f-4f3a-bfa8-7db716791acf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971261469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1971261469
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2560288765
Short name T851
Test name
Test status
Simulation time 320042923204 ps
CPU time 313.38 seconds
Started Dec 24 01:15:20 PM PST 23
Finished Dec 24 01:20:58 PM PST 23
Peak memory 200756 kb
Host smart-ffe066bb-94f8-4890-87d1-9eeef1067092
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560288765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2560288765
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.547201342
Short name T202
Test name
Test status
Simulation time 118538165168 ps
CPU time 612.31 seconds
Started Dec 24 01:15:19 PM PST 23
Finished Dec 24 01:25:56 PM PST 23
Peak memory 201328 kb
Host smart-3fc08881-1539-42ec-a852-1070a73d0d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547201342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.547201342
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3737083376
Short name T701
Test name
Test status
Simulation time 39287915283 ps
CPU time 16.1 seconds
Started Dec 24 01:15:18 PM PST 23
Finished Dec 24 01:16:00 PM PST 23
Peak memory 200636 kb
Host smart-60c32e71-c361-4ec7-9a88-44e74a3f5ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737083376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3737083376
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1675969625
Short name T633
Test name
Test status
Simulation time 5191535315 ps
CPU time 8.6 seconds
Started Dec 24 01:15:13 PM PST 23
Finished Dec 24 01:15:46 PM PST 23
Peak memory 200732 kb
Host smart-5969a4a3-0c17-49ec-82cf-65ce146dd3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675969625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1675969625
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.181895733
Short name T658
Test name
Test status
Simulation time 5879080800 ps
CPU time 3.76 seconds
Started Dec 24 01:15:21 PM PST 23
Finished Dec 24 01:15:49 PM PST 23
Peak memory 200712 kb
Host smart-5cf4672e-2020-4605-bff7-396779faa648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181895733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.181895733
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2864409599
Short name T274
Test name
Test status
Simulation time 162241793192 ps
CPU time 31.25 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:16:18 PM PST 23
Peak memory 200812 kb
Host smart-61889df8-ea5c-4922-956f-cd16e086c82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864409599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2864409599
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1478620890
Short name T55
Test name
Test status
Simulation time 431504488 ps
CPU time 1.52 seconds
Started Dec 24 01:15:11 PM PST 23
Finished Dec 24 01:15:34 PM PST 23
Peak memory 200688 kb
Host smart-b95ab986-b2e4-4331-a7b2-d7f6871dba26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478620890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1478620890
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3254543723
Short name T326
Test name
Test status
Simulation time 488214748429 ps
CPU time 724.38 seconds
Started Dec 24 01:15:22 PM PST 23
Finished Dec 24 01:27:50 PM PST 23
Peak memory 200952 kb
Host smart-6d72ca7e-5099-4565-ba62-451aae076bbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254543723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3254543723
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.592319934
Short name T831
Test name
Test status
Simulation time 487342546822 ps
CPU time 534.5 seconds
Started Dec 24 01:15:08 PM PST 23
Finished Dec 24 01:24:25 PM PST 23
Peak memory 200900 kb
Host smart-7f6fc6ed-a2c5-47e3-9a80-2e30f15bcb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592319934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.592319934
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2013826544
Short name T576
Test name
Test status
Simulation time 165138719099 ps
CPU time 386.34 seconds
Started Dec 24 01:15:10 PM PST 23
Finished Dec 24 01:21:58 PM PST 23
Peak memory 200892 kb
Host smart-0c59f976-6145-4608-b059-eb6599c1ebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013826544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2013826544
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3563918829
Short name T168
Test name
Test status
Simulation time 321638243725 ps
CPU time 433.55 seconds
Started Dec 24 01:15:18 PM PST 23
Finished Dec 24 01:22:56 PM PST 23
Peak memory 200856 kb
Host smart-995dccf0-3413-479e-bbf5-e21463dba3ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563918829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3563918829
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3935549977
Short name T295
Test name
Test status
Simulation time 164263776446 ps
CPU time 100.78 seconds
Started Dec 24 01:15:07 PM PST 23
Finished Dec 24 01:17:11 PM PST 23
Peak memory 200980 kb
Host smart-29191d34-c968-458f-b342-3aaf27630fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935549977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3935549977
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1681441018
Short name T518
Test name
Test status
Simulation time 327274495676 ps
CPU time 788.91 seconds
Started Dec 24 01:15:21 PM PST 23
Finished Dec 24 01:28:54 PM PST 23
Peak memory 200876 kb
Host smart-2b37b8e2-8508-4242-bf4b-2a1c55178262
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681441018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1681441018
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3850333182
Short name T330
Test name
Test status
Simulation time 494890785854 ps
CPU time 797.48 seconds
Started Dec 24 01:15:14 PM PST 23
Finished Dec 24 01:28:58 PM PST 23
Peak memory 200860 kb
Host smart-c8673599-8533-4c0a-a487-62ce8f72410e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850333182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3850333182
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1526810485
Short name T638
Test name
Test status
Simulation time 493152591404 ps
CPU time 1149.81 seconds
Started Dec 24 01:15:16 PM PST 23
Finished Dec 24 01:34:51 PM PST 23
Peak memory 200908 kb
Host smart-d0cf2f0a-6aa5-4e6b-b366-f9b6294b589e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526810485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1526810485
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2300437164
Short name T725
Test name
Test status
Simulation time 116312680772 ps
CPU time 414.39 seconds
Started Dec 24 01:15:19 PM PST 23
Finished Dec 24 01:22:39 PM PST 23
Peak memory 201132 kb
Host smart-34e91171-324f-4a39-9562-9070a10943f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300437164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2300437164
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.481348927
Short name T419
Test name
Test status
Simulation time 42533356710 ps
CPU time 107.98 seconds
Started Dec 24 01:15:21 PM PST 23
Finished Dec 24 01:17:33 PM PST 23
Peak memory 200680 kb
Host smart-24124552-72ee-4462-9121-bab383bfd0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481348927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.481348927
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2938833876
Short name T52
Test name
Test status
Simulation time 3591477494 ps
CPU time 9.13 seconds
Started Dec 24 01:15:09 PM PST 23
Finished Dec 24 01:15:40 PM PST 23
Peak memory 200704 kb
Host smart-8dd05dd1-0ef9-44b8-a27a-7a21b187cf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938833876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2938833876
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2926037845
Short name T806
Test name
Test status
Simulation time 5865855352 ps
CPU time 4.67 seconds
Started Dec 24 01:15:20 PM PST 23
Finished Dec 24 01:15:49 PM PST 23
Peak memory 200740 kb
Host smart-8ffd9157-28e9-47ae-a234-68e4968604cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926037845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2926037845
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2365647367
Short name T302
Test name
Test status
Simulation time 191975445684 ps
CPU time 99.07 seconds
Started Dec 24 01:15:20 PM PST 23
Finished Dec 24 01:17:24 PM PST 23
Peak memory 200728 kb
Host smart-7c11bb14-1d76-40d5-b9a9-38569979653a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365647367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2365647367
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.620811022
Short name T110
Test name
Test status
Simulation time 78257023608 ps
CPU time 101.68 seconds
Started Dec 24 01:15:20 PM PST 23
Finished Dec 24 01:17:26 PM PST 23
Peak memory 209536 kb
Host smart-86a4a461-83e5-4bd6-9228-d368fc3d8de5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620811022 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.620811022
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3223061210
Short name T697
Test name
Test status
Simulation time 536602879 ps
CPU time 0.9 seconds
Started Dec 24 01:15:21 PM PST 23
Finished Dec 24 01:15:46 PM PST 23
Peak memory 200620 kb
Host smart-6ed0c53a-37bb-44e1-8b9b-1aa192151428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223061210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3223061210
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2930341851
Short name T97
Test name
Test status
Simulation time 162280681962 ps
CPU time 98.88 seconds
Started Dec 24 01:15:10 PM PST 23
Finished Dec 24 01:17:11 PM PST 23
Peak memory 200940 kb
Host smart-b8d97612-f5c8-45f7-8544-ddecc7bb5229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930341851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2930341851
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1136413987
Short name T115
Test name
Test status
Simulation time 486371424209 ps
CPU time 73.8 seconds
Started Dec 24 01:15:19 PM PST 23
Finished Dec 24 01:16:58 PM PST 23
Peak memory 200896 kb
Host smart-86976944-ffd7-492e-bce5-153cba5ea5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136413987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1136413987
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.899955151
Short name T142
Test name
Test status
Simulation time 158621983256 ps
CPU time 238.75 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:19:46 PM PST 23
Peak memory 200896 kb
Host smart-e538c932-44cb-421b-adf5-e28dea6fb524
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=899955151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.899955151
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3659518210
Short name T453
Test name
Test status
Simulation time 325256283738 ps
CPU time 776.52 seconds
Started Dec 24 01:15:21 PM PST 23
Finished Dec 24 01:28:42 PM PST 23
Peak memory 200716 kb
Host smart-7719d22f-c116-40d5-87d7-8a7edeb6f3bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659518210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3659518210
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4117340391
Short name T306
Test name
Test status
Simulation time 492050662586 ps
CPU time 255.83 seconds
Started Dec 24 01:15:19 PM PST 23
Finished Dec 24 01:19:59 PM PST 23
Peak memory 200932 kb
Host smart-74c85fed-e468-4754-9f23-d1733e76e35d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117340391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4117340391
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.91004328
Short name T749
Test name
Test status
Simulation time 328600124569 ps
CPU time 814.89 seconds
Started Dec 24 01:15:28 PM PST 23
Finished Dec 24 01:29:26 PM PST 23
Peak memory 200948 kb
Host smart-8b83f6fc-2f1d-487f-89ec-8fa3fdc6ed0c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91004328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
dc_ctrl_filters_wakeup_fixed.91004328
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.647803151
Short name T667
Test name
Test status
Simulation time 76431080451 ps
CPU time 274.6 seconds
Started Dec 24 01:15:24 PM PST 23
Finished Dec 24 01:20:22 PM PST 23
Peak memory 201312 kb
Host smart-20f5acc1-9527-450c-b2f0-f8d5f01f5cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647803151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.647803151
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1202101379
Short name T425
Test name
Test status
Simulation time 27867615227 ps
CPU time 32.31 seconds
Started Dec 24 01:15:26 PM PST 23
Finished Dec 24 01:16:21 PM PST 23
Peak memory 200720 kb
Host smart-1cd5cd61-914c-4832-8faa-d61e7a952251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202101379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1202101379
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3686222205
Short name T845
Test name
Test status
Simulation time 4348891667 ps
CPU time 3.22 seconds
Started Dec 24 01:15:11 PM PST 23
Finished Dec 24 01:15:36 PM PST 23
Peak memory 200772 kb
Host smart-d233778a-4b39-4f23-98ee-eff853f78ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686222205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3686222205
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2871687679
Short name T663
Test name
Test status
Simulation time 5921732293 ps
CPU time 3.21 seconds
Started Dec 24 01:15:16 PM PST 23
Finished Dec 24 01:15:45 PM PST 23
Peak memory 200644 kb
Host smart-109da446-8de8-49d6-9a9f-f427c39267ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871687679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2871687679
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1047866899
Short name T157
Test name
Test status
Simulation time 252969131550 ps
CPU time 253.97 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:19:51 PM PST 23
Peak memory 209468 kb
Host smart-077569bc-21f9-48c1-80ea-89734d8bea2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047866899 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1047866899
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.568976820
Short name T432
Test name
Test status
Simulation time 294289021 ps
CPU time 0.93 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:15:38 PM PST 23
Peak memory 200684 kb
Host smart-62d484ec-9417-481f-adbb-9c9d834e0be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568976820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.568976820
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3677527544
Short name T703
Test name
Test status
Simulation time 327105574365 ps
CPU time 679.31 seconds
Started Dec 24 01:15:14 PM PST 23
Finished Dec 24 01:27:00 PM PST 23
Peak memory 200824 kb
Host smart-ddcd6aa9-ed5f-479f-bf41-809ae686859c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677527544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3677527544
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1169458284
Short name T842
Test name
Test status
Simulation time 325964948351 ps
CPU time 588.39 seconds
Started Dec 24 01:15:26 PM PST 23
Finished Dec 24 01:25:38 PM PST 23
Peak memory 200960 kb
Host smart-9858c9c8-f57d-4d03-a001-1267dddb6f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169458284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1169458284
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2309574019
Short name T833
Test name
Test status
Simulation time 337689428064 ps
CPU time 203.95 seconds
Started Dec 24 01:15:22 PM PST 23
Finished Dec 24 01:19:09 PM PST 23
Peak memory 200900 kb
Host smart-6b1b27bc-7000-4661-9980-c7facb6c2822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309574019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2309574019
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2614514463
Short name T487
Test name
Test status
Simulation time 167029497214 ps
CPU time 145.71 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:18:13 PM PST 23
Peak memory 200856 kb
Host smart-1908d0b4-3bce-483d-9379-90eae044b05b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614514463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2614514463
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2107976724
Short name T94
Test name
Test status
Simulation time 161111395025 ps
CPU time 356.93 seconds
Started Dec 24 01:15:26 PM PST 23
Finished Dec 24 01:21:46 PM PST 23
Peak memory 200868 kb
Host smart-535ba677-861a-41f8-b77e-9f2101a504b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107976724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2107976724
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4166924420
Short name T825
Test name
Test status
Simulation time 160528938720 ps
CPU time 88.19 seconds
Started Dec 24 01:15:26 PM PST 23
Finished Dec 24 01:17:18 PM PST 23
Peak memory 200900 kb
Host smart-90baadf2-87a7-4c85-afb9-2f8fcfada513
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166924420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4166924420
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1416716857
Short name T322
Test name
Test status
Simulation time 165198644958 ps
CPU time 399.03 seconds
Started Dec 24 01:15:24 PM PST 23
Finished Dec 24 01:22:27 PM PST 23
Peak memory 200976 kb
Host smart-0e25394f-e371-4c2c-8b65-4b09203c88ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416716857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1416716857
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1405741669
Short name T473
Test name
Test status
Simulation time 167026092731 ps
CPU time 193.69 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:19:01 PM PST 23
Peak memory 200868 kb
Host smart-3487c464-84e7-452b-a529-70edc5d687ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405741669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1405741669
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.274704283
Short name T503
Test name
Test status
Simulation time 78434607465 ps
CPU time 407.44 seconds
Started Dec 24 01:15:14 PM PST 23
Finished Dec 24 01:22:26 PM PST 23
Peak memory 201324 kb
Host smart-dc56449a-f602-4b24-be9d-67239877cd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274704283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.274704283
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4193899868
Short name T516
Test name
Test status
Simulation time 43646322736 ps
CPU time 6.06 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:15:43 PM PST 23
Peak memory 200748 kb
Host smart-eef9fede-1a0a-4d06-bcb0-b31522057fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193899868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4193899868
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2874946046
Short name T109
Test name
Test status
Simulation time 5343870562 ps
CPU time 2.88 seconds
Started Dec 24 01:15:25 PM PST 23
Finished Dec 24 01:15:51 PM PST 23
Peak memory 200712 kb
Host smart-0e535eae-e2b4-48e0-ac1b-c0f23aaabdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874946046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2874946046
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.154318826
Short name T489
Test name
Test status
Simulation time 5877008596 ps
CPU time 14.54 seconds
Started Dec 24 01:15:14 PM PST 23
Finished Dec 24 01:15:55 PM PST 23
Peak memory 200684 kb
Host smart-0489f3b8-168b-40f6-84ee-88cf7833ba94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154318826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.154318826
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1137386896
Short name T125
Test name
Test status
Simulation time 170193085625 ps
CPU time 60.84 seconds
Started Dec 24 01:15:21 PM PST 23
Finished Dec 24 01:16:46 PM PST 23
Peak memory 200964 kb
Host smart-bf835730-f83a-4d65-921a-394b5a97b555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137386896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1137386896
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2351928785
Short name T155
Test name
Test status
Simulation time 309306360 ps
CPU time 0.79 seconds
Started Dec 24 01:15:25 PM PST 23
Finished Dec 24 01:15:49 PM PST 23
Peak memory 200628 kb
Host smart-59fcf54b-874d-45a1-be92-88a2ed902179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351928785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2351928785
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3517176028
Short name T92
Test name
Test status
Simulation time 165553459712 ps
CPU time 373.11 seconds
Started Dec 24 01:15:21 PM PST 23
Finished Dec 24 01:21:58 PM PST 23
Peak memory 200852 kb
Host smart-1c872c58-570e-4b27-87ae-6c6e7e476bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517176028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3517176028
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1872226824
Short name T268
Test name
Test status
Simulation time 327046886773 ps
CPU time 704.24 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:27:31 PM PST 23
Peak memory 200944 kb
Host smart-b5d99fa3-d064-4784-b4fb-df08caa378d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872226824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1872226824
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3459998946
Short name T694
Test name
Test status
Simulation time 165492848884 ps
CPU time 83.39 seconds
Started Dec 24 01:15:28 PM PST 23
Finished Dec 24 01:17:15 PM PST 23
Peak memory 200800 kb
Host smart-8b2f376f-f887-4c29-a49e-3d5358023739
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459998946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3459998946
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2139992309
Short name T467
Test name
Test status
Simulation time 166134992496 ps
CPU time 375.67 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:22:03 PM PST 23
Peak memory 200876 kb
Host smart-448f237f-5660-41a0-90ab-f30cd42ccff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139992309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2139992309
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2657631798
Short name T433
Test name
Test status
Simulation time 326318548841 ps
CPU time 763.88 seconds
Started Dec 24 01:15:13 PM PST 23
Finished Dec 24 01:28:21 PM PST 23
Peak memory 200880 kb
Host smart-bc1ab879-406a-4079-9828-e0150dd12caf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657631798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2657631798
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.463776132
Short name T239
Test name
Test status
Simulation time 167487023648 ps
CPU time 84.45 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:17:01 PM PST 23
Peak memory 200868 kb
Host smart-35b470ce-5d5b-4c9d-84f4-632c0de655fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463776132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.463776132
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.280341912
Short name T317
Test name
Test status
Simulation time 326510546075 ps
CPU time 187.02 seconds
Started Dec 24 01:15:34 PM PST 23
Finished Dec 24 01:19:01 PM PST 23
Peak memory 200852 kb
Host smart-2813ac13-16f5-457a-94e6-4804c3f7b3ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280341912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.280341912
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3935651434
Short name T203
Test name
Test status
Simulation time 116999352999 ps
CPU time 466.96 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:23:24 PM PST 23
Peak memory 201352 kb
Host smart-c6e9f18b-6c8d-45b8-85ea-526ea4baea0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935651434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3935651434
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3386569050
Short name T539
Test name
Test status
Simulation time 28220839208 ps
CPU time 68.41 seconds
Started Dec 24 01:15:13 PM PST 23
Finished Dec 24 01:16:46 PM PST 23
Peak memory 200748 kb
Host smart-5f7a2a5a-1d0f-47cc-856f-3d62b9b0dce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386569050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3386569050
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2203737167
Short name T87
Test name
Test status
Simulation time 4825737049 ps
CPU time 3.6 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:15:40 PM PST 23
Peak memory 200748 kb
Host smart-baaa5596-8b2b-496c-8022-36314347272c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203737167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2203737167
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3768180545
Short name T16
Test name
Test status
Simulation time 5965931465 ps
CPU time 14.14 seconds
Started Dec 24 01:15:14 PM PST 23
Finished Dec 24 01:15:54 PM PST 23
Peak memory 200696 kb
Host smart-8695ec9a-3391-49c2-9506-13660bb5ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768180545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3768180545
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2139926271
Short name T328
Test name
Test status
Simulation time 159600507352 ps
CPU time 317.7 seconds
Started Dec 24 01:15:13 PM PST 23
Finished Dec 24 01:20:56 PM PST 23
Peak memory 209496 kb
Host smart-2397f22e-2360-4834-bdce-9d68e4f556cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139926271 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2139926271
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1290964567
Short name T824
Test name
Test status
Simulation time 427711152 ps
CPU time 1.61 seconds
Started Dec 24 01:15:20 PM PST 23
Finished Dec 24 01:15:46 PM PST 23
Peak memory 200680 kb
Host smart-2654654b-4815-4ed2-8222-0c1f21ee8f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290964567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1290964567
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.4212145644
Short name T807
Test name
Test status
Simulation time 162025210066 ps
CPU time 82.81 seconds
Started Dec 24 01:15:25 PM PST 23
Finished Dec 24 01:17:11 PM PST 23
Peak memory 200888 kb
Host smart-c9b1ad5e-9ed0-4592-91a9-4db85427710c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212145644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.4212145644
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2456398305
Short name T285
Test name
Test status
Simulation time 335493635931 ps
CPU time 748.58 seconds
Started Dec 24 01:15:24 PM PST 23
Finished Dec 24 01:28:17 PM PST 23
Peak memory 200908 kb
Host smart-9f908b30-aed3-44ee-b483-8d5f9d88a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456398305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2456398305
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2598517474
Short name T319
Test name
Test status
Simulation time 326562671044 ps
CPU time 768.83 seconds
Started Dec 24 01:15:16 PM PST 23
Finished Dec 24 01:28:31 PM PST 23
Peak memory 200888 kb
Host smart-c7f9aec1-b4a1-4659-85a1-4f1e305ed10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598517474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2598517474
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2853988423
Short name T816
Test name
Test status
Simulation time 164109420065 ps
CPU time 375.11 seconds
Started Dec 24 01:15:25 PM PST 23
Finished Dec 24 01:22:03 PM PST 23
Peak memory 200784 kb
Host smart-aed220a2-a30c-430a-8e1b-fef805eaa548
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853988423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2853988423
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3748934350
Short name T782
Test name
Test status
Simulation time 324273374673 ps
CPU time 195.61 seconds
Started Dec 24 01:15:20 PM PST 23
Finished Dec 24 01:19:00 PM PST 23
Peak memory 200824 kb
Host smart-612acf2e-59f7-4e4e-ba21-0eb5c2af3ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748934350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3748934350
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3151690202
Short name T748
Test name
Test status
Simulation time 163037211780 ps
CPU time 96.58 seconds
Started Dec 24 01:15:24 PM PST 23
Finished Dec 24 01:17:25 PM PST 23
Peak memory 200868 kb
Host smart-24d7628b-ec0f-4c52-891b-e807b58f353a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151690202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3151690202
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3766270610
Short name T263
Test name
Test status
Simulation time 499052883012 ps
CPU time 1159.69 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:34:56 PM PST 23
Peak memory 200864 kb
Host smart-f114654b-657b-4e7f-bf88-941e294c258f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766270610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3766270610
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1813000451
Short name T242
Test name
Test status
Simulation time 154809009743 ps
CPU time 89.22 seconds
Started Dec 24 01:15:11 PM PST 23
Finished Dec 24 01:17:02 PM PST 23
Peak memory 200816 kb
Host smart-d9c8cdbb-34e5-4b83-a9f7-4e7ee4a164b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813000451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1813000451
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1004265429
Short name T159
Test name
Test status
Simulation time 70740505273 ps
CPU time 217.16 seconds
Started Dec 24 01:15:24 PM PST 23
Finished Dec 24 01:19:25 PM PST 23
Peak memory 201428 kb
Host smart-b72b3b02-409e-4654-8956-c08b047c743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004265429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1004265429
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3091733785
Short name T603
Test name
Test status
Simulation time 23976478496 ps
CPU time 3.32 seconds
Started Dec 24 01:15:23 PM PST 23
Finished Dec 24 01:15:50 PM PST 23
Peak memory 200672 kb
Host smart-fed08179-9c41-4e66-826e-5f26f3161f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091733785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3091733785
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.487966155
Short name T13
Test name
Test status
Simulation time 5055725769 ps
CPU time 2.16 seconds
Started Dec 24 01:15:24 PM PST 23
Finished Dec 24 01:15:50 PM PST 23
Peak memory 200760 kb
Host smart-c52f95bc-1ff4-4ee5-92fb-0c32265306d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487966155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.487966155
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3351049800
Short name T622
Test name
Test status
Simulation time 5658256863 ps
CPU time 4.18 seconds
Started Dec 24 01:15:17 PM PST 23
Finished Dec 24 01:15:46 PM PST 23
Peak memory 200740 kb
Host smart-299b4b7b-7b7c-43d8-8b62-b756540adcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351049800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3351049800
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.260802772
Short name T739
Test name
Test status
Simulation time 1186568683 ps
CPU time 1.43 seconds
Started Dec 24 01:15:25 PM PST 23
Finished Dec 24 01:15:50 PM PST 23
Peak memory 200664 kb
Host smart-8b5ca529-c122-4177-a6a2-b0a2ff442ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260802772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
260802772
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.299251674
Short name T257
Test name
Test status
Simulation time 70854735861 ps
CPU time 91.05 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:17:08 PM PST 23
Peak memory 209660 kb
Host smart-8e0155a6-b734-4aae-8af4-31f8aa74c168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299251674 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.299251674
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.882806877
Short name T619
Test name
Test status
Simulation time 543408342 ps
CPU time 0.92 seconds
Started Dec 24 01:15:26 PM PST 23
Finished Dec 24 01:15:51 PM PST 23
Peak memory 200672 kb
Host smart-0de6d9ec-fe28-41a5-9e87-362e95ad23b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882806877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.882806877
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1875069544
Short name T237
Test name
Test status
Simulation time 495172530640 ps
CPU time 1143.52 seconds
Started Dec 24 01:15:26 PM PST 23
Finished Dec 24 01:34:53 PM PST 23
Peak memory 200928 kb
Host smart-ab5f119a-2a8c-4aba-a0be-15ffb39feecf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875069544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1875069544
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.4087676179
Short name T740
Test name
Test status
Simulation time 502898387273 ps
CPU time 1092.45 seconds
Started Dec 24 01:15:32 PM PST 23
Finished Dec 24 01:34:06 PM PST 23
Peak memory 200888 kb
Host smart-aef0a6f7-d8fe-4a65-a429-69c1ad752c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087676179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.4087676179
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2945440142
Short name T152
Test name
Test status
Simulation time 505782232474 ps
CPU time 170.7 seconds
Started Dec 24 01:15:29 PM PST 23
Finished Dec 24 01:18:42 PM PST 23
Peak memory 200852 kb
Host smart-3bd03261-cda7-4a76-8938-a9c8d836e900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945440142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2945440142
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3129723219
Short name T788
Test name
Test status
Simulation time 169517699766 ps
CPU time 35.57 seconds
Started Dec 24 01:15:28 PM PST 23
Finished Dec 24 01:16:27 PM PST 23
Peak memory 200960 kb
Host smart-c1d47ca5-e2ff-47e2-96cd-d9d9907e955c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129723219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3129723219
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.4095520291
Short name T288
Test name
Test status
Simulation time 325139789107 ps
CPU time 201.13 seconds
Started Dec 24 01:15:38 PM PST 23
Finished Dec 24 01:19:16 PM PST 23
Peak memory 200780 kb
Host smart-cf897180-f2a5-47c4-a38c-2e88907f1bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095520291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.4095520291
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2510013215
Short name T711
Test name
Test status
Simulation time 324063708827 ps
CPU time 369.78 seconds
Started Dec 24 01:15:29 PM PST 23
Finished Dec 24 01:22:01 PM PST 23
Peak memory 200872 kb
Host smart-d8f967be-7393-4777-b806-65a6814f9acb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510013215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2510013215
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.59865220
Short name T218
Test name
Test status
Simulation time 161894325309 ps
CPU time 378.4 seconds
Started Dec 24 01:15:27 PM PST 23
Finished Dec 24 01:22:09 PM PST 23
Peak memory 200856 kb
Host smart-904c3025-7d72-4b11-886d-8f3c3c6c1cda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59865220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_w
akeup.59865220
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1956331872
Short name T451
Test name
Test status
Simulation time 323338209147 ps
CPU time 714.36 seconds
Started Dec 24 01:15:31 PM PST 23
Finished Dec 24 01:27:48 PM PST 23
Peak memory 200860 kb
Host smart-c13df299-57d2-493d-90e6-45b2d8fd65f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956331872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1956331872
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1583119072
Short name T209
Test name
Test status
Simulation time 125222225298 ps
CPU time 402.78 seconds
Started Dec 24 01:15:33 PM PST 23
Finished Dec 24 01:22:36 PM PST 23
Peak memory 201436 kb
Host smart-c577c7ad-bbc0-4cb7-bcc8-354f483b484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583119072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1583119072
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3858826650
Short name T707
Test name
Test status
Simulation time 43988711332 ps
CPU time 50.52 seconds
Started Dec 24 01:15:36 PM PST 23
Finished Dec 24 01:16:44 PM PST 23
Peak memory 200708 kb
Host smart-c745febb-eabe-419e-b9f9-25fc0d8d1cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858826650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3858826650
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1219311734
Short name T755
Test name
Test status
Simulation time 3289315201 ps
CPU time 3.91 seconds
Started Dec 24 01:15:27 PM PST 23
Finished Dec 24 01:15:54 PM PST 23
Peak memory 200768 kb
Host smart-27e63bb5-9c1f-4a8f-a902-1ce48563b6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219311734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1219311734
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3310562920
Short name T569
Test name
Test status
Simulation time 5893411395 ps
CPU time 14.81 seconds
Started Dec 24 01:15:12 PM PST 23
Finished Dec 24 01:15:52 PM PST 23
Peak memory 200676 kb
Host smart-2607e179-887e-4226-ad95-7294341489dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310562920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3310562920
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.304739507
Short name T817
Test name
Test status
Simulation time 170963074260 ps
CPU time 399.66 seconds
Started Dec 24 01:15:25 PM PST 23
Finished Dec 24 01:22:28 PM PST 23
Peak memory 200908 kb
Host smart-903a1feb-b4bc-4af7-9645-e0695f47b375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304739507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
304739507
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2024146119
Short name T777
Test name
Test status
Simulation time 348402013 ps
CPU time 1 seconds
Started Dec 24 01:15:26 PM PST 23
Finished Dec 24 01:15:51 PM PST 23
Peak memory 200552 kb
Host smart-5058fe17-181c-4d8e-a610-a48b8c62b1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024146119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2024146119
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.100363552
Short name T352
Test name
Test status
Simulation time 329074469681 ps
CPU time 238.28 seconds
Started Dec 24 01:15:36 PM PST 23
Finished Dec 24 01:19:52 PM PST 23
Peak memory 200980 kb
Host smart-6ec4c6c6-486c-42a0-bed7-e76fb7051fac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100363552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.100363552
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2029326465
Short name T141
Test name
Test status
Simulation time 165333440392 ps
CPU time 424.89 seconds
Started Dec 24 01:15:39 PM PST 23
Finished Dec 24 01:23:01 PM PST 23
Peak memory 200856 kb
Host smart-0b08f256-dc09-4eac-b985-ea74ac52e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029326465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2029326465
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2058570543
Short name T348
Test name
Test status
Simulation time 497385297033 ps
CPU time 616.81 seconds
Started Dec 24 01:15:30 PM PST 23
Finished Dec 24 01:26:09 PM PST 23
Peak memory 200944 kb
Host smart-525e3f18-32dd-4ebb-b208-10d2a02eff50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058570543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2058570543
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1315231822
Short name T99
Test name
Test status
Simulation time 327501239796 ps
CPU time 98.5 seconds
Started Dec 24 01:15:24 PM PST 23
Finished Dec 24 01:17:27 PM PST 23
Peak memory 200868 kb
Host smart-0f2e69c3-0d63-4203-8d27-0554df1d43d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315231822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1315231822
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.649638429
Short name T148
Test name
Test status
Simulation time 498534840950 ps
CPU time 64.72 seconds
Started Dec 24 01:15:30 PM PST 23
Finished Dec 24 01:16:57 PM PST 23
Peak memory 200908 kb
Host smart-5fcd4f63-ecfc-4011-8a6d-3323a4d05ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649638429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.649638429
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1854230716
Short name T629
Test name
Test status
Simulation time 327208885346 ps
CPU time 719.69 seconds
Started Dec 24 01:15:37 PM PST 23
Finished Dec 24 01:27:54 PM PST 23
Peak memory 200876 kb
Host smart-ef6b65c7-76cc-43e9-be3f-6e5b19f3e454
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854230716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1854230716
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.621948679
Short name T174
Test name
Test status
Simulation time 496540232963 ps
CPU time 290.73 seconds
Started Dec 24 01:15:34 PM PST 23
Finished Dec 24 01:20:44 PM PST 23
Peak memory 200964 kb
Host smart-8faee0c5-55d5-4e92-b127-235a70175d69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621948679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.621948679
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.579454420
Short name T530
Test name
Test status
Simulation time 323084087453 ps
CPU time 193.26 seconds
Started Dec 24 01:15:28 PM PST 23
Finished Dec 24 01:19:04 PM PST 23
Peak memory 200740 kb
Host smart-deb5e14c-f898-4eb4-9187-b5ca3a5f3e4f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579454420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.579454420
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4171107058
Short name T469
Test name
Test status
Simulation time 37715898901 ps
CPU time 11.16 seconds
Started Dec 24 01:15:32 PM PST 23
Finished Dec 24 01:16:04 PM PST 23
Peak memory 200616 kb
Host smart-6ef37f1b-cb4a-4add-a118-b21b8ded2c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171107058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.4171107058
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.468542476
Short name T466
Test name
Test status
Simulation time 3833836134 ps
CPU time 5.26 seconds
Started Dec 24 01:15:34 PM PST 23
Finished Dec 24 01:15:59 PM PST 23
Peak memory 200664 kb
Host smart-477552cc-8b0f-481c-b5ce-f5028c315762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468542476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.468542476
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.445066049
Short name T423
Test name
Test status
Simulation time 5921209792 ps
CPU time 14.22 seconds
Started Dec 24 01:15:31 PM PST 23
Finished Dec 24 01:16:07 PM PST 23
Peak memory 200656 kb
Host smart-ee1270d6-270c-42a3-b249-6c357b556455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445066049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.445066049
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2779796553
Short name T362
Test name
Test status
Simulation time 144684473666 ps
CPU time 497.92 seconds
Started Dec 24 01:15:28 PM PST 23
Finished Dec 24 01:24:09 PM PST 23
Peak memory 209604 kb
Host smart-1aa52b76-2768-4905-8fd3-ee924150df40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779796553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2779796553
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.741905992
Short name T240
Test name
Test status
Simulation time 42471299972 ps
CPU time 87.09 seconds
Started Dec 24 01:15:30 PM PST 23
Finished Dec 24 01:17:20 PM PST 23
Peak memory 209208 kb
Host smart-0aaa6fd3-1eb9-47fa-8f02-a19b6d0dca6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741905992 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.741905992
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.58744117
Short name T648
Test name
Test status
Simulation time 377762011 ps
CPU time 0.72 seconds
Started Dec 24 01:15:26 PM PST 23
Finished Dec 24 01:15:51 PM PST 23
Peak memory 200680 kb
Host smart-2787a792-1a69-46e6-b779-03f39aa71b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58744117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.58744117
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2564132000
Short name T691
Test name
Test status
Simulation time 161792523580 ps
CPU time 101.89 seconds
Started Dec 24 01:15:28 PM PST 23
Finished Dec 24 01:17:33 PM PST 23
Peak memory 200936 kb
Host smart-6e26d463-2fa1-4a52-be9e-aefa99ce67c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564132000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2564132000
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1062955796
Short name T533
Test name
Test status
Simulation time 328682717802 ps
CPU time 217.93 seconds
Started Dec 24 01:15:26 PM PST 23
Finished Dec 24 01:19:28 PM PST 23
Peak memory 200852 kb
Host smart-987b17dc-5c4f-436a-ad39-7d466100457e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062955796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1062955796
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.910683182
Short name T804
Test name
Test status
Simulation time 331730243736 ps
CPU time 69.03 seconds
Started Dec 24 01:15:27 PM PST 23
Finished Dec 24 01:16:59 PM PST 23
Peak memory 200956 kb
Host smart-c69187e9-5f39-4e39-a2b9-31e5ea0d626b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=910683182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.910683182
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1164320073
Short name T163
Test name
Test status
Simulation time 499181628481 ps
CPU time 198.7 seconds
Started Dec 24 01:15:28 PM PST 23
Finished Dec 24 01:19:10 PM PST 23
Peak memory 200844 kb
Host smart-be179937-57eb-4951-89ee-4f0eeaf3e902
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164320073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1164320073
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.580338615
Short name T526
Test name
Test status
Simulation time 169696359709 ps
CPU time 387.79 seconds
Started Dec 24 01:15:27 PM PST 23
Finished Dec 24 01:22:18 PM PST 23
Peak memory 200784 kb
Host smart-7aa7b3d3-467c-43e6-b6f6-fdce54c61901
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580338615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.580338615
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2664993563
Short name T208
Test name
Test status
Simulation time 91593064289 ps
CPU time 527.33 seconds
Started Dec 24 01:15:31 PM PST 23
Finished Dec 24 01:24:41 PM PST 23
Peak memory 201348 kb
Host smart-470fe80a-d1b5-4421-aa0a-3836f645188c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664993563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2664993563
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1063621711
Short name T447
Test name
Test status
Simulation time 32691756399 ps
CPU time 73.06 seconds
Started Dec 24 01:15:32 PM PST 23
Finished Dec 24 01:17:06 PM PST 23
Peak memory 200744 kb
Host smart-d4e2bc12-5c86-4744-8a2c-d58f203d3220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063621711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1063621711
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.4155218581
Short name T643
Test name
Test status
Simulation time 3471627850 ps
CPU time 1.74 seconds
Started Dec 24 01:15:30 PM PST 23
Finished Dec 24 01:15:54 PM PST 23
Peak memory 200680 kb
Host smart-d0d5814c-1908-484e-b67b-995410d58eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155218581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.4155218581
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3067866034
Short name T653
Test name
Test status
Simulation time 5995904938 ps
CPU time 10.65 seconds
Started Dec 24 01:15:25 PM PST 23
Finished Dec 24 01:15:59 PM PST 23
Peak memory 200696 kb
Host smart-707a5c8b-1194-4ef1-a2e4-ab5dc86bb264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067866034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3067866034
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.244667467
Short name T226
Test name
Test status
Simulation time 228126673217 ps
CPU time 477.05 seconds
Started Dec 24 01:15:27 PM PST 23
Finished Dec 24 01:23:48 PM PST 23
Peak memory 209520 kb
Host smart-d710e323-67b6-4001-9e2e-ed0b7a851076
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244667467 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.244667467
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2117363009
Short name T630
Test name
Test status
Simulation time 521698294 ps
CPU time 0.71 seconds
Started Dec 24 01:14:40 PM PST 23
Finished Dec 24 01:14:48 PM PST 23
Peak memory 200628 kb
Host smart-0b342bb9-e015-4297-8832-ef0c3d4eefa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117363009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2117363009
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2041244219
Short name T349
Test name
Test status
Simulation time 493145418451 ps
CPU time 768.26 seconds
Started Dec 24 01:14:19 PM PST 23
Finished Dec 24 01:27:20 PM PST 23
Peak memory 200880 kb
Host smart-b58936c7-99e3-4120-b3c0-779e9b6b0c28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041244219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2041244219
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2974687122
Short name T786
Test name
Test status
Simulation time 500588962667 ps
CPU time 653.39 seconds
Started Dec 24 01:14:32 PM PST 23
Finished Dec 24 01:25:32 PM PST 23
Peak memory 200768 kb
Host smart-758f5e80-11f3-4f5a-9d68-d80c4cae799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974687122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2974687122
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3093476975
Short name T773
Test name
Test status
Simulation time 487313549247 ps
CPU time 1105.47 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:32:47 PM PST 23
Peak memory 200944 kb
Host smart-1e4b1652-2689-49a6-afe2-02f021ad5ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093476975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3093476975
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1919570857
Short name T761
Test name
Test status
Simulation time 327159183163 ps
CPU time 783.85 seconds
Started Dec 24 01:14:21 PM PST 23
Finished Dec 24 01:27:37 PM PST 23
Peak memory 200876 kb
Host smart-b013d2ad-1a8c-4649-8e4e-35738d80eea3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919570857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1919570857
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1662889957
Short name T646
Test name
Test status
Simulation time 319446866680 ps
CPU time 696.16 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:25:51 PM PST 23
Peak memory 200840 kb
Host smart-35b1d905-4cdc-45d8-b2a1-2dcc6f7f4f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662889957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1662889957
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2499139701
Short name T427
Test name
Test status
Simulation time 481599616030 ps
CPU time 283.55 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:19:10 PM PST 23
Peak memory 200920 kb
Host smart-ba844b2e-4d81-4543-bb01-77ef359b1c31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499139701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2499139701
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2189510390
Short name T438
Test name
Test status
Simulation time 164703321178 ps
CPU time 370.15 seconds
Started Dec 24 01:14:13 PM PST 23
Finished Dec 24 01:20:39 PM PST 23
Peak memory 200788 kb
Host smart-ef39f27e-1622-41ec-bada-0ba314b2835f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189510390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2189510390
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3216177120
Short name T363
Test name
Test status
Simulation time 126870545227 ps
CPU time 715.02 seconds
Started Dec 24 01:14:29 PM PST 23
Finished Dec 24 01:26:31 PM PST 23
Peak memory 201348 kb
Host smart-686841fa-abdc-48e6-b18b-e17d73cc19bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216177120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3216177120
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.68157911
Short name T140
Test name
Test status
Simulation time 36502964588 ps
CPU time 21.54 seconds
Started Dec 24 01:14:40 PM PST 23
Finished Dec 24 01:15:09 PM PST 23
Peak memory 200676 kb
Host smart-64dd65fd-8fce-4b8e-a838-16a0ff9a5315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68157911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.68157911
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2809639448
Short name T564
Test name
Test status
Simulation time 3834242608 ps
CPU time 9.53 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:14:52 PM PST 23
Peak memory 200712 kb
Host smart-0eca7272-b8f9-4e63-9eb8-e39ad7b705d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809639448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2809639448
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2428148436
Short name T461
Test name
Test status
Simulation time 5827260410 ps
CPU time 7.59 seconds
Started Dec 24 01:14:26 PM PST 23
Finished Dec 24 01:14:43 PM PST 23
Peak memory 200672 kb
Host smart-24cb3cb6-920c-4b31-a8ab-b40018999f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428148436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2428148436
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2448355020
Short name T261
Test name
Test status
Simulation time 163030153365 ps
CPU time 103.14 seconds
Started Dec 24 01:14:13 PM PST 23
Finished Dec 24 01:16:12 PM PST 23
Peak memory 201092 kb
Host smart-e809c34c-f233-497f-9040-d5b99843d7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448355020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2448355020
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3999575793
Short name T259
Test name
Test status
Simulation time 92065476728 ps
CPU time 219.76 seconds
Started Dec 24 01:14:21 PM PST 23
Finished Dec 24 01:18:13 PM PST 23
Peak memory 209628 kb
Host smart-2bd74510-8746-4dbd-920c-8410eb188962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999575793 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3999575793
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2015105252
Short name T615
Test name
Test status
Simulation time 501390999 ps
CPU time 1.73 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:14:07 PM PST 23
Peak memory 200656 kb
Host smart-1edb7aa3-1851-426f-9ce0-f891645e7b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015105252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2015105252
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.4085295560
Short name T122
Test name
Test status
Simulation time 164610175156 ps
CPU time 5.29 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:14:08 PM PST 23
Peak memory 200876 kb
Host smart-b4cc7f06-5dc0-40b0-9964-7deba18c41fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085295560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.4085295560
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2749278197
Short name T792
Test name
Test status
Simulation time 492463720661 ps
CPU time 529.9 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:22:59 PM PST 23
Peak memory 200976 kb
Host smart-9ff58804-805a-4990-923b-54c715c44436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749278197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2749278197
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.984259863
Short name T585
Test name
Test status
Simulation time 328825065487 ps
CPU time 392.25 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:20:54 PM PST 23
Peak memory 200912 kb
Host smart-06cb22aa-455a-4eda-aed5-1bdfdae2158e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984259863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.984259863
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.474898325
Short name T675
Test name
Test status
Simulation time 491654475287 ps
CPU time 579.57 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:23:46 PM PST 23
Peak memory 200700 kb
Host smart-d5062cc0-181f-4bef-9d43-958b499ac7d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=474898325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.474898325
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1703617442
Short name T602
Test name
Test status
Simulation time 499309583393 ps
CPU time 290.42 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:19:17 PM PST 23
Peak memory 200932 kb
Host smart-922cbf3d-77e9-45e9-a2e7-636694c7c77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703617442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1703617442
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2089298352
Short name T790
Test name
Test status
Simulation time 160721625351 ps
CPU time 372.03 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:20:32 PM PST 23
Peak memory 200936 kb
Host smart-de4138be-cd2a-4f96-bbb7-419cec79381a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089298352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2089298352
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.748419268
Short name T345
Test name
Test status
Simulation time 364237483250 ps
CPU time 765.98 seconds
Started Dec 24 01:13:57 PM PST 23
Finished Dec 24 01:26:48 PM PST 23
Peak memory 200896 kb
Host smart-39a77152-35f1-43a4-b5e1-abebd9346381
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748419268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.748419268
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3936223600
Short name T565
Test name
Test status
Simulation time 323912620644 ps
CPU time 659.51 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:25:21 PM PST 23
Peak memory 200896 kb
Host smart-0a17f869-7a34-4647-a61d-1cb4d2313e38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936223600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3936223600
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3961952524
Short name T822
Test name
Test status
Simulation time 134265903510 ps
CPU time 472.44 seconds
Started Dec 24 01:13:56 PM PST 23
Finished Dec 24 01:21:53 PM PST 23
Peak memory 201280 kb
Host smart-92943f1d-d792-4f11-843b-32fae8b709b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961952524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3961952524
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.8823529
Short name T780
Test name
Test status
Simulation time 41184185452 ps
CPU time 23.86 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:14:30 PM PST 23
Peak memory 200676 kb
Host smart-a608eac7-4f18-468d-88f5-1bce0689c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8823529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.8823529
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1551069884
Short name T832
Test name
Test status
Simulation time 3729114987 ps
CPU time 5.14 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:14:27 PM PST 23
Peak memory 200732 kb
Host smart-d6b62b31-1b0c-4763-9748-483091f34bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551069884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1551069884
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1837939999
Short name T514
Test name
Test status
Simulation time 5846052877 ps
CPU time 2.2 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:14:09 PM PST 23
Peak memory 200752 kb
Host smart-cd897348-7889-4979-a44e-abb53cb955a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837939999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1837939999
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.339731694
Short name T608
Test name
Test status
Simulation time 229108911400 ps
CPU time 551.39 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:23:33 PM PST 23
Peak memory 200892 kb
Host smart-17d52f61-80f3-4e01-8c98-f4cd512470fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339731694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.339731694
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1233525802
Short name T272
Test name
Test status
Simulation time 692899681115 ps
CPU time 741.57 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:26:30 PM PST 23
Peak memory 209592 kb
Host smart-cdda3753-45a2-4dc2-a84b-ff41fa1beb76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233525802 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1233525802
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4208782722
Short name T553
Test name
Test status
Simulation time 365147434 ps
CPU time 1.42 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:14:20 PM PST 23
Peak memory 200660 kb
Host smart-06798c94-5380-435b-beca-cb5c11e76083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208782722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4208782722
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4237840596
Short name T299
Test name
Test status
Simulation time 328658797206 ps
CPU time 338.71 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:19:54 PM PST 23
Peak memory 200788 kb
Host smart-015e7d3b-f4ef-49bd-af7f-9a8513b6d879
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237840596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4237840596
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1128756862
Short name T219
Test name
Test status
Simulation time 324137737391 ps
CPU time 344.66 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:20:01 PM PST 23
Peak memory 200852 kb
Host smart-9f803142-f802-4b8c-baa9-ce3f27c4012a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128756862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1128756862
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.937356314
Short name T683
Test name
Test status
Simulation time 169792800119 ps
CPU time 414.91 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:21:07 PM PST 23
Peak memory 200940 kb
Host smart-658b96bc-f4e9-4384-b5c1-0999beb7e4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937356314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.937356314
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3430685181
Short name T573
Test name
Test status
Simulation time 332564982809 ps
CPU time 720.47 seconds
Started Dec 24 01:14:07 PM PST 23
Finished Dec 24 01:26:24 PM PST 23
Peak memory 200884 kb
Host smart-934cf4c1-369d-40f6-afc7-cee47938d1b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430685181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3430685181
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2277623541
Short name T566
Test name
Test status
Simulation time 333815986131 ps
CPU time 811.72 seconds
Started Dec 24 01:13:57 PM PST 23
Finished Dec 24 01:27:35 PM PST 23
Peak memory 200892 kb
Host smart-d8172095-ec28-4b8b-a43e-20ae9bda2885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277623541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2277623541
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.4108679034
Short name T695
Test name
Test status
Simulation time 323210896689 ps
CPU time 183.4 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:17:07 PM PST 23
Peak memory 200868 kb
Host smart-5693e595-97f2-4a26-a467-1ce0d4ff7b0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108679034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.4108679034
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2760122151
Short name T54
Test name
Test status
Simulation time 331012619270 ps
CPU time 227.32 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:18:04 PM PST 23
Peak memory 200872 kb
Host smart-c39383a7-646f-4dcd-a7e2-f9fd599804c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760122151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2760122151
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1537553577
Short name T470
Test name
Test status
Simulation time 165581975006 ps
CPU time 185.74 seconds
Started Dec 24 01:14:07 PM PST 23
Finished Dec 24 01:17:30 PM PST 23
Peak memory 200856 kb
Host smart-933dec7c-7c90-45de-851c-520520d83563
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537553577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1537553577
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3051537526
Short name T664
Test name
Test status
Simulation time 83309944855 ps
CPU time 307.4 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:19:13 PM PST 23
Peak memory 201264 kb
Host smart-4973d1af-e57a-4d4d-94ad-e99a4065355e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051537526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3051537526
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2319972897
Short name T133
Test name
Test status
Simulation time 33741871883 ps
CPU time 16.86 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:14:33 PM PST 23
Peak memory 200700 kb
Host smart-ca3576c3-4e8d-408d-b6c2-42159d029b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319972897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2319972897
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2790212689
Short name T426
Test name
Test status
Simulation time 3409152939 ps
CPU time 2.52 seconds
Started Dec 24 01:13:58 PM PST 23
Finished Dec 24 01:14:09 PM PST 23
Peak memory 200636 kb
Host smart-ec7124ce-4672-4c1e-817d-8907d26c5b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790212689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2790212689
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4236791448
Short name T578
Test name
Test status
Simulation time 5478824161 ps
CPU time 13.43 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:14:35 PM PST 23
Peak memory 200668 kb
Host smart-88c2e048-72dc-4961-ae8b-a8517581b25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236791448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4236791448
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2112608513
Short name T522
Test name
Test status
Simulation time 104393179085 ps
CPU time 321.52 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:19:38 PM PST 23
Peak memory 201312 kb
Host smart-0a4e0196-f8e0-491b-ad33-c4b8affb49dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112608513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2112608513
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3136224670
Short name T528
Test name
Test status
Simulation time 372346522 ps
CPU time 0.84 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:14:28 PM PST 23
Peak memory 200568 kb
Host smart-43bad744-6684-4e21-93be-1e435ceef442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136224670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3136224670
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2132444299
Short name T681
Test name
Test status
Simulation time 168455012635 ps
CPU time 88.4 seconds
Started Dec 24 01:13:57 PM PST 23
Finished Dec 24 01:15:29 PM PST 23
Peak memory 200876 kb
Host smart-7eca90df-0faa-4b3d-a429-69c847c4907b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132444299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2132444299
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.554525745
Short name T492
Test name
Test status
Simulation time 162961722417 ps
CPU time 193.46 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:17:20 PM PST 23
Peak memory 200924 kb
Host smart-fe00de8c-cae9-49b8-b74a-61d0ee19fb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554525745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.554525745
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.808951364
Short name T15
Test name
Test status
Simulation time 328782084939 ps
CPU time 364.46 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:20:23 PM PST 23
Peak memory 200856 kb
Host smart-7a90c30a-ac0a-4240-aea6-0f9db25d4e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808951364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.808951364
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2009277117
Short name T860
Test name
Test status
Simulation time 484251894709 ps
CPU time 1148.49 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:33:19 PM PST 23
Peak memory 200920 kb
Host smart-7aff2efe-5c05-48dc-b2ea-cf305d5d3723
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009277117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2009277117
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.399116013
Short name T153
Test name
Test status
Simulation time 492516788091 ps
CPU time 70.54 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:15:20 PM PST 23
Peak memory 200892 kb
Host smart-776ab6a8-686f-49d6-ba59-8591bf35694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399116013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.399116013
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1943318753
Short name T586
Test name
Test status
Simulation time 326256910197 ps
CPU time 191.43 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:17:20 PM PST 23
Peak memory 200852 kb
Host smart-3e7b5129-abd1-46a6-917d-d5eaf7307235
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943318753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1943318753
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2541863896
Short name T325
Test name
Test status
Simulation time 163544657844 ps
CPU time 211.56 seconds
Started Dec 24 01:14:02 PM PST 23
Finished Dec 24 01:17:49 PM PST 23
Peak memory 200952 kb
Host smart-293bd3dd-4cdf-46d1-b1a9-f3c64a3e2346
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541863896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2541863896
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1661540376
Short name T483
Test name
Test status
Simulation time 166671144954 ps
CPU time 385.95 seconds
Started Dec 24 01:14:08 PM PST 23
Finished Dec 24 01:20:51 PM PST 23
Peak memory 200856 kb
Host smart-8a5d543f-33e6-4f45-82db-4fada9d8ebd3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661540376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1661540376
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2559543227
Short name T686
Test name
Test status
Simulation time 32575698991 ps
CPU time 20.68 seconds
Started Dec 24 01:14:09 PM PST 23
Finished Dec 24 01:14:46 PM PST 23
Peak memory 200632 kb
Host smart-deb9c22c-3d48-4635-982f-bce48dea459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559543227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2559543227
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.933914826
Short name T762
Test name
Test status
Simulation time 3480161346 ps
CPU time 4.37 seconds
Started Dec 24 01:14:00 PM PST 23
Finished Dec 24 01:14:15 PM PST 23
Peak memory 200724 kb
Host smart-01c7732f-3c90-4987-8663-719e5c7cbc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933914826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.933914826
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3911832157
Short name T570
Test name
Test status
Simulation time 5818579857 ps
CPU time 14.98 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:14:42 PM PST 23
Peak memory 200632 kb
Host smart-143b31d0-84f9-4cb0-97f2-01f10479d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911832157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3911832157
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2847523759
Short name T289
Test name
Test status
Simulation time 338744338233 ps
CPU time 755.16 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:26:58 PM PST 23
Peak memory 200796 kb
Host smart-b877e2d0-1bbb-4639-96c9-f7ee9962a473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847523759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2847523759
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1119356195
Short name T333
Test name
Test status
Simulation time 1257279587374 ps
CPU time 706.16 seconds
Started Dec 24 01:13:59 PM PST 23
Finished Dec 24 01:25:53 PM PST 23
Peak memory 209520 kb
Host smart-88f71e3b-670a-4b9e-afe2-0599fe6375f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119356195 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1119356195
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3246967650
Short name T834
Test name
Test status
Simulation time 401199245 ps
CPU time 1.48 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:14:29 PM PST 23
Peak memory 200684 kb
Host smart-8884e6b8-ea09-4e71-9435-991cc8b868bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246967650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3246967650
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1875979950
Short name T138
Test name
Test status
Simulation time 163915981054 ps
CPU time 317.46 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:19:36 PM PST 23
Peak memory 200932 kb
Host smart-708a8289-9990-46b1-8215-bad4db531545
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875979950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1875979950
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.288028919
Short name T350
Test name
Test status
Simulation time 352871111998 ps
CPU time 739.84 seconds
Started Dec 24 01:14:01 PM PST 23
Finished Dec 24 01:26:35 PM PST 23
Peak memory 200960 kb
Host smart-58bf1bc1-1418-4b70-a951-40f8e36d120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288028919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.288028919
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1429868572
Short name T235
Test name
Test status
Simulation time 324992821099 ps
CPU time 767.78 seconds
Started Dec 24 01:14:05 PM PST 23
Finished Dec 24 01:27:09 PM PST 23
Peak memory 200952 kb
Host smart-bfb2c20b-558c-49a5-bfca-d2ac00c25cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429868572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1429868572
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2374803566
Short name T785
Test name
Test status
Simulation time 484145212955 ps
CPU time 1139.79 seconds
Started Dec 24 01:14:10 PM PST 23
Finished Dec 24 01:33:26 PM PST 23
Peak memory 200948 kb
Host smart-4d6cb324-2ff6-4f94-8a32-33f828e0bb90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374803566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2374803566
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3079511285
Short name T156
Test name
Test status
Simulation time 166157474610 ps
CPU time 129.36 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:16:31 PM PST 23
Peak memory 200900 kb
Host smart-05517886-b7b5-4f2b-a48a-50fc4815411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079511285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3079511285
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2478625330
Short name T504
Test name
Test status
Simulation time 491603018895 ps
CPU time 560.14 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:23:47 PM PST 23
Peak memory 200756 kb
Host smart-bade17a1-c5b4-41ba-9986-eee5252f17ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478625330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2478625330
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.83047356
Short name T543
Test name
Test status
Simulation time 163494433877 ps
CPU time 341.08 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:20:08 PM PST 23
Peak memory 200748 kb
Host smart-43c7941b-7ba2-4a92-b2de-7311bebd1874
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83047356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.ad
c_ctrl_filters_wakeup_fixed.83047356
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1298830309
Short name T743
Test name
Test status
Simulation time 86863266123 ps
CPU time 452.29 seconds
Started Dec 24 01:14:16 PM PST 23
Finished Dec 24 01:22:02 PM PST 23
Peak memory 201276 kb
Host smart-4d743d50-c751-4e12-90bc-76c889ccc2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298830309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1298830309
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1342765389
Short name T19
Test name
Test status
Simulation time 33481881011 ps
CPU time 76.66 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:15:36 PM PST 23
Peak memory 200732 kb
Host smart-75e79fe0-e473-4f7a-adcd-477969b98aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342765389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1342765389
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1402106515
Short name T509
Test name
Test status
Simulation time 5697777373 ps
CPU time 13.36 seconds
Started Dec 24 01:14:03 PM PST 23
Finished Dec 24 01:14:32 PM PST 23
Peak memory 200768 kb
Host smart-ec4bd214-6a23-4e75-9d82-395adc1ec5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402106515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1402106515
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1824223496
Short name T37
Test name
Test status
Simulation time 5642907499 ps
CPU time 14.61 seconds
Started Dec 24 01:14:12 PM PST 23
Finished Dec 24 01:14:42 PM PST 23
Peak memory 200684 kb
Host smart-3e2091a0-efb1-4b71-bbd2-d12e4cbda573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824223496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1824223496
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3157790372
Short name T197
Test name
Test status
Simulation time 115928028609 ps
CPU time 602.71 seconds
Started Dec 24 01:14:06 PM PST 23
Finished Dec 24 01:24:25 PM PST 23
Peak memory 201340 kb
Host smart-4b866fb4-2251-49b4-873a-d2e27601b623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157790372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3157790372
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2802952113
Short name T343
Test name
Test status
Simulation time 38626049556 ps
CPU time 94.49 seconds
Started Dec 24 01:14:35 PM PST 23
Finished Dec 24 01:16:17 PM PST 23
Peak memory 209228 kb
Host smart-e73d53a7-cfc9-4288-a729-9908561e30f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802952113 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2802952113
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%