Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1193940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1146571

1

T4

39

T5

9

T1

663

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2052324	1			T4	31		T5	11		T1	325
values[0x0]	143549	1			T4	18		T5	7		T1	165
values[0x1]	144638	1			T4	17		T5	6		T1	174

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	961577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1378934

1

T4

50

T5

12

T1

663

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6380	1			T2	4		T3	2		T27	1
valid_sources[0x01]	10990	1			T23	1		T3	4		T9	8
valid_sources[0x02]	10741	1			T3	7		T9	4		T11	9
valid_sources[0x03]	11306	1			T3	2		T6	96		T28	4
valid_sources[0x04]	6372	1			T3	1		T8	16		T9	3
valid_sources[0x05]	6785	1			T28	3		T9	1		T11	15
valid_sources[0x06]	7865	1			T3	2		T9	4		T11	9
valid_sources[0x07]	10761	1			T1	22		T23	1		T28	1
valid_sources[0x08]	14885	1			T2	4		T3	7		T27	1
valid_sources[0x09]	6918	1			T4	3		T2	7		T3	2
valid_sources[0x0a]	6449	1			T2	4		T28	1		T8	9
valid_sources[0x0b]	11033	1			T1	5		T9	11		T11	16
valid_sources[0x0c]	12361	1			T25	2		T9	5		T11	4
valid_sources[0x0d]	6991	1			T3	4		T8	9		T9	2
valid_sources[0x0e]	6829	1			T25	1		T3	4		T9	3
valid_sources[0x0f]	8908	1			T1	33		T2	4		T3	7
valid_sources[0x10]	9924	1			T4	2		T1	7		T3	1
valid_sources[0x11]	10797	1			T25	1		T3	1		T28	2
valid_sources[0x12]	11475	1			T1	10		T25	2		T6	1
valid_sources[0x13]	9213	1			T3	4		T11	7		T12	10
valid_sources[0x14]	17439	1			T1	22		T25	1		T3	5
valid_sources[0x15]	9789	1			T25	1		T27	1		T9	3
valid_sources[0x16]	10687	1			T25	1		T8	5		T9	5
valid_sources[0x17]	10680	1			T1	5		T28	2		T9	2
valid_sources[0x18]	7785	1			T1	4		T25	3		T3	16
valid_sources[0x19]	6433	1			T23	1		T2	7		T25	1
valid_sources[0x1a]	6372	1			T9	4		T11	10		T12	16
valid_sources[0x1b]	19829	1			T25	2		T3	2		T6	7
valid_sources[0x1c]	22683	1			T4	1		T3	4		T6	2
valid_sources[0x1d]	6618	1			T2	2		T6	12		T8	36
valid_sources[0x1e]	14387	1			T25	2		T9	6		T11	10
valid_sources[0x1f]	8226	1			T2	41		T25	1		T9	4
valid_sources[0x20]	6861	1			T3	1		T9	10		T11	12
valid_sources[0x21]	6752	1			T1	9		T6	13		T9	3
valid_sources[0x22]	11556	1			T4	1		T2	12		T12	3
valid_sources[0x23]	13786	1			T2	10		T25	1		T3	8
valid_sources[0x24]	6272	1			T2	9		T9	2		T11	2
valid_sources[0x25]	6485	1			T3	7		T28	1		T9	3
valid_sources[0x26]	9678	1			T3	5		T6	1		T27	1
valid_sources[0x27]	15929	1			T1	15		T8	3		T11	14
valid_sources[0x28]	6299	1			T3	4		T27	1		T9	1
valid_sources[0x29]	7224	1			T3	4		T26	40		T9	2
valid_sources[0x2a]	6601	1			T27	1		T9	3		T11	7
valid_sources[0x2b]	6490	1			T27	1		T28	1		T9	3
valid_sources[0x2c]	9321	1			T27	2		T28	1		T8	14
valid_sources[0x2d]	7556	1			T1	29		T2	6		T27	1
valid_sources[0x2e]	7688	1			T2	4		T3	3		T9	1
valid_sources[0x2f]	6584	1			T1	4		T3	1		T9	1
valid_sources[0x30]	9592	1			T3	14		T8	13		T9	1
valid_sources[0x31]	20780	1			T28	1		T11	8		T12	6
valid_sources[0x32]	7446	1			T1	5		T3	16		T8	3
valid_sources[0x33]	6475	1			T27	1		T11	10		T12	10
valid_sources[0x34]	11195	1			T2	30		T3	10		T27	1
valid_sources[0x35]	6878	1			T1	46		T28	1		T8	20
valid_sources[0x36]	7202	1			T25	1		T6	3		T28	1
valid_sources[0x37]	6507	1			T3	2		T8	26		T9	3
valid_sources[0x38]	8497	1			T3	2		T9	2		T11	10
valid_sources[0x39]	8562	1			T5	1		T28	1		T9	1
valid_sources[0x3a]	11660	1			T3	10		T9	5		T11	12
valid_sources[0x3b]	6556	1			T3	2		T6	7		T9	2
valid_sources[0x3c]	9170	1			T9	2		T11	22		T12	8
valid_sources[0x3d]	6478	1			T2	40		T3	1		T9	1
valid_sources[0x3e]	7552	1			T25	1		T9	4		T11	5
valid_sources[0x3f]	10770	1			T9	4		T11	17		T12	9
valid_sources[0x40]	6883	1			T1	8		T3	3		T27	2
valid_sources[0x41]	11207	1			T4	1		T5	1		T3	4
valid_sources[0x42]	13619	1			T4	1		T6	43		T28	1
valid_sources[0x43]	7349	1			T5	1		T2	27		T7	13
valid_sources[0x44]	18860	1			T23	4		T25	3		T3	17
valid_sources[0x45]	6498	1			T2	16		T9	4		T11	9
valid_sources[0x46]	9508	1			T5	1		T28	1		T9	2
valid_sources[0x47]	12120	1			T4	3		T3	2		T9	3
valid_sources[0x48]	10925	1			T3	1		T6	59		T8	3
valid_sources[0x49]	6816	1			T2	47		T25	1		T9	3
valid_sources[0x4a]	6452	1			T2	9		T3	7		T27	1
valid_sources[0x4b]	9684	1			T25	1		T27	1		T28	2
valid_sources[0x4c]	6414	1			T2	37		T6	22		T28	1
valid_sources[0x4d]	7608	1			T1	16		T28	2		T8	10
valid_sources[0x4e]	11136	1			T3	2		T27	1		T9	2
valid_sources[0x4f]	7576	1			T9	2		T10	25		T11	9
valid_sources[0x50]	9266	1			T3	7		T27	1		T28	1
valid_sources[0x51]	8642	1			T5	1		T3	6		T27	1
valid_sources[0x52]	10717	1			T1	10		T25	1		T28	2
valid_sources[0x53]	6489	1			T25	3		T3	4		T28	1
valid_sources[0x54]	6629	1			T25	2		T28	3		T9	2
valid_sources[0x55]	6664	1			T6	31		T8	21		T9	1
valid_sources[0x56]	10974	1			T9	1		T11	4		T12	9
valid_sources[0x57]	16019	1			T1	10		T3	2		T28	1
valid_sources[0x58]	7033	1			T5	1		T1	23		T6	9
valid_sources[0x59]	6733	1			T28	1		T9	2		T11	6
valid_sources[0x5a]	6756	1			T9	3		T10	11		T11	8
valid_sources[0x5b]	7362	1			T3	8		T28	1		T9	3
valid_sources[0x5c]	6461	1			T3	4		T9	2		T11	6
valid_sources[0x5d]	6287	1			T6	38		T9	2		T11	2
valid_sources[0x5e]	11619	1			T25	2		T9	3		T11	5
valid_sources[0x5f]	13554	1			T8	9		T9	2		T11	10
valid_sources[0x60]	6588	1			T23	1		T2	38		T3	11
valid_sources[0x61]	6871	1			T28	2		T9	3		T10	7
valid_sources[0x62]	6813	1			T3	7		T27	1		T28	2
valid_sources[0x63]	7843	1			T6	7		T27	1		T28	1
valid_sources[0x64]	10769	1			T8	55		T9	3		T11	9
valid_sources[0x65]	6568	1			T2	6		T9	1		T11	15
valid_sources[0x66]	6262	1			T4	1		T5	1		T1	10
valid_sources[0x67]	16361	1			T3	5		T9	1		T11	12
valid_sources[0x68]	6750	1			T2	19		T25	1		T28	2
valid_sources[0x69]	7923	1			T6	19		T9	6		T11	3
valid_sources[0x6a]	7770	1			T5	1		T8	7		T9	7
valid_sources[0x6b]	15153	1			T6	1		T9	3		T11	13
valid_sources[0x6c]	6878	1			T8	6		T9	3		T11	14
valid_sources[0x6d]	6915	1			T25	1		T28	1		T9	2
valid_sources[0x6e]	10745	1			T4	3		T2	14		T3	2
valid_sources[0x6f]	21553	1			T1	12		T2	9		T27	1
valid_sources[0x70]	7978	1			T1	5		T2	9		T3	1
valid_sources[0x71]	14200	1			T3	4		T27	1		T9	4
valid_sources[0x72]	17797	1			T1	7		T27	2		T8	1
valid_sources[0x73]	11697	1			T1	4		T23	1		T25	2
valid_sources[0x74]	6782	1			T25	2		T3	11		T9	4
valid_sources[0x75]	15257	1			T1	5		T23	1		T3	5
valid_sources[0x76]	9354	1			T27	1		T8	12		T9	1
valid_sources[0x77]	10571	1			T23	1		T27	1		T28	5
valid_sources[0x78]	6637	1			T3	4		T6	18		T9	3
valid_sources[0x79]	11189	1			T2	17		T9	4		T11	15
valid_sources[0x7a]	9358	1			T4	2		T25	1		T3	4
valid_sources[0x7b]	6940	1			T2	3		T3	11		T9	6
valid_sources[0x7c]	7741	1			T9	1		T11	18		T12	4
valid_sources[0x7d]	7604	1			T2	38		T3	9		T27	1
valid_sources[0x7e]	6919	1			T28	1		T8	10		T9	4
valid_sources[0x7f]	7667	1			T27	2		T8	12		T9	3
valid_sources[0x80]	11021	1			T1	11		T9	5		T11	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1022133

1

T4

13

T5

6

T1

325

values[0x0]

all_enables

biggest_size

72321

1

T4

15

T5

3

T1

165

values[0x1]

all_enables

biggest_size

52117

1

T4

11

T1

173

T23

2