Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29798	1			T1	314		T2	451		T3	28
auto[PWRUP]	106	1			T21	4		T97	2		T128	3
auto[ONEST_0]	57	1			T19	2		T21	3		T97	2
auto[ONEST_021]	16	1			T32	1		T163	1		T164	1
auto[ONEST_1]	65	1			T19	1		T21	1		T97	1
auto[ONEST_DONE]	4	1			T165	1		T166	1		T167	1
auto[LP_0]	109	1			T19	2		T21	1		T128	1
auto[LP_021]	22	1			T19	1		T164	2		T168	1
auto[LP_1]	133	1			T21	5		T97	2		T99	3
auto[LP_EVAL]	90	1			T19	4		T21	6		T99	1
auto[LP_SLP]	519	1			T19	4		T21	17		T97	4
auto[LP_PWRUP]	28	1			T97	1		T128	2		T32	2
auto[NP_0]	156	1			T21	5		T97	1		T99	2
auto[NP_021]	31	1			T21	1		T99	1		T33	1
auto[NP_1]	157	1			T19	1		T21	3		T97	1
auto[NP_EVAL]	29	1			T19	1		T21	1		T99	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T97

1

T164

1

T169

1

min

29261

1

T1

314

T2

451

T3

28

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29273	1			T1	314		T2	451		T3	28
pow[0x1]	11	1			T170	1		T171	1		T172	1
pow[0x2]	13	1			T21	1		T128	1		T173	1
pow[0x3]	34	1			T99	1		T32	1		T168	1
pow[0x4]	64	1			T21	2		T128	1		T33	1
pow[0x5]	134	1			T19	2		T21	6		T99	4
pow[0x6]	237	1			T19	3		T21	9		T99	4
pow[0x7]	514	1			T19	3		T21	13		T97	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

226

1

T19

1

T21

9

T97

4

min

28760

1

T1

314

T2

451

T3

28

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28760	1			T1	314		T2	451		T3	28
pow[0x4]	1	1			T174	1		-	-		-	-
pow[0x5]	2	1			T33	2		-	-		-	-
pow[0x6]	1	1			T175	1		-	-		-	-
pow[0x7]	3	1			T175	1		T176	1		T177	1
pow[0x8]	6	1			T178	1		T179	1		T180	1
pow[0x9]	9	1			T32	1		T181	1		T166	1
pow[0xa]	18	1			T19	1		T178	1		T182	1
pow[0xb]	32	1			T19	1		T181	1		T183	1
pow[0xc]	70	1			T19	2		T21	2		T97	1
pow[0xd]	146	1			T19	1		T21	6		T99	2
pow[0xe]	273	1			T19	3		T21	11		T97	3
pow[0xf]	614	1			T19	4		T21	20		T97	5