Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2244	1			T4	1		T25	1		T6	10
auto[PWRUP]	144	1			T19	1		T21	2		T97	3
auto[ONEST_0]	76	1			T19	1		T21	2		T94	1
auto[ONEST_021]	19	1			T97	1		T163	1		T348	1
auto[ONEST_1]	102	1			T19	1		T21	1		T97	2
auto[ONEST_DONE]	1	1			T171	1		-	-		-	-
auto[LP_0]	155	1			T19	1		T21	1		T97	1
auto[LP_021]	23	1			T21	1		T98	1		T33	1
auto[LP_1]	134	1			T19	1		T21	5		T34	1
auto[LP_EVAL]	55	1			T19	2		T21	3		T97	1
auto[LP_SLP]	537	1			T19	4		T21	7		T34	1
auto[LP_PWRUP]	30	1			T19	1		T164	1		T183	1
auto[NP_0]	223	1			T19	3		T21	8		T34	3
auto[NP_021]	50	1			T19	1		T21	1		T32	1
auto[NP_1]	233	1			T19	4		T21	6		T34	2
auto[NP_EVAL]	39	1			T94	1		T97	1		T98	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T128

1

T183

1

T166

1

min

1952

1

T4

1

T25

1

T6

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1961	1			T4	1		T25	1		T6	10
pow[0x1]	7	1			T349	2		T350	2		T175	1
pow[0x2]	17	1			T19	1		T140	1		T168	1
pow[0x3]	32	1			T19	1		T21	1		T97	1
pow[0x4]	67	1			T19	1		T21	1		T128	3
pow[0x5]	120	1			T19	1		T21	1		T97	1
pow[0x6]	262	1			T21	3		T34	1		T97	3
pow[0x7]	510	1			T19	6		T21	9		T97	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T21

7

T97

6

T99

10

min

1344

1

T4

1

T25

1

T6

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1348	1			T4	1		T25	1		T6	10
pow[0x1]	14	1			T19	3		T98	1		T140	2
pow[0x2]	37	1			T19	3		T21	2		T94	2
pow[0x3]	46	1			T21	2		T34	4		T101	1
pow[0x4]	48	1			T21	2		T94	1		T140	4
pow[0x6]	2	1			T351	1		T166	1		-	-
pow[0x7]	3	1			T19	1		T178	1		T352	1
pow[0x8]	3	1			T353	1		T316	1		T319	1
pow[0x9]	9	1			T163	1		T168	1		T167	1
pow[0xa]	18	1			T32	1		T164	1		T181	1
pow[0xb]	49	1			T99	1		T128	2		T33	1
pow[0xc]	69	1			T21	1		T97	2		T128	2
pow[0xd]	139	1			T19	1		T21	3		T97	2
pow[0xe]	304	1			T19	2		T21	7		T97	4
pow[0xf]	567	1			T19	5		T21	13		T97	6