Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	96.84		100.00	92.77	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmStateHwReset_A	1204	1204	0	0
FsmStateSwReset_A	29315898	6397	0	0
LpSampleCntHwReset_A	1204	1204	0	0
LpSampleCntSwReset_A	29315898	6397	0	0
NpSampleCntHwReset_A	1204	1204	0	0
NpSampleCntSwReset_A	29315898	6397	0	0
PwrupTimerCntHwReset_A	1204	1204	0	0
PwrupTimerCntSwReset_A	29315898	6397	0	0
WakeupTimerCntHwReset_A	1204	1204	0	0
WakeupTimerCntSwReset_A	29315898	6397	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1204	1204	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	6	6	0	0
T19	10	10	0	0
T20	1	1	0	0
T21	25	25	0	0
T22	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29315898	6397	0	0
T13	67272	17	0	0
T14	98250	25	0	0
T15	98349	17	0	0
T16	97780	22	0	0
T17	32671	10	0	0
T18	43265	5	0	0
T19	38940	0	0	0
T20	33195	10	0	0
T21	87673	0	0	0
T22	64536	17	0	0
T35	0	8	0	0
T53	0	9	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1204	1204	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	6	6	0	0
T19	10	10	0	0
T20	1	1	0	0
T21	25	25	0	0
T22	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29315898	6397	0	0
T13	67272	17	0	0
T14	98250	25	0	0
T15	98349	17	0	0
T16	97780	22	0	0
T17	32671	10	0	0
T18	43265	5	0	0
T19	38940	0	0	0
T20	33195	10	0	0
T21	87673	0	0	0
T22	64536	17	0	0
T35	0	8	0	0
T53	0	9	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1204	1204	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	6	6	0	0
T19	10	10	0	0
T20	1	1	0	0
T21	25	25	0	0
T22	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29315898	6397	0	0
T13	67272	17	0	0
T14	98250	25	0	0
T15	98349	17	0	0
T16	97780	22	0	0
T17	32671	10	0	0
T18	43265	5	0	0
T19	38940	0	0	0
T20	33195	10	0	0
T21	87673	0	0	0
T22	64536	17	0	0
T35	0	8	0	0
T53	0	9	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1204	1204	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	6	6	0	0
T19	10	10	0	0
T20	1	1	0	0
T21	25	25	0	0
T22	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29315898	6397	0	0
T13	67272	17	0	0
T14	98250	25	0	0
T15	98349	17	0	0
T16	97780	22	0	0
T17	32671	10	0	0
T18	43265	5	0	0
T19	38940	0	0	0
T20	33195	10	0	0
T21	87673	0	0	0
T22	64536	17	0	0
T35	0	8	0	0
T53	0	9	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1204	1204	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	6	6	0	0
T19	10	10	0	0
T20	1	1	0	0
T21	25	25	0	0
T22	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29315898	6397	0	0
T13	67272	17	0	0
T14	98250	25	0	0
T15	98349	17	0	0
T16	97780	22	0	0
T17	32671	10	0	0
T18	43265	5	0	0
T19	38940	0	0	0
T20	33195	10	0	0
T21	87673	0	0	0
T22	64536	17	0	0
T35	0	8	0	0
T53	0	9	0	0