Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T18,T19,T21

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T20
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T20
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T19,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T20
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T20
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T19,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T20
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T15,T16
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T20
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T19,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T14,T18,T19
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T14,T18,T19
1	0	Covered	T14,T18,T19

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T21
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T21
0	1	Covered	T14,T19,T21
1	0	Covered	T14,T19,T21

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T18,T19
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T14,T18,T19
1	0	Covered	T18,T19,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T14,T18,T19
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T14,T18,T19
1	0	Covered	T14,T18,T19

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T14,T18,T19
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T14,T20,T21
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T15,T16
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T20,T21
0	1	Covered	T14,T20,T21
1	0	Covered	T14,T20,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T14,T18,T19
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T14,T18,T19
1	0	Covered	T14,T18,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T20
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T15,T16
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T20
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T19,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T14,T18,T19
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T14,T18,T19
1	0	Covered	T14,T18,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T14,T19,T21
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T21
0	1	Covered	T14,T19,T21
1	0	Covered	T14,T19,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T18,T19
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T14,T18,T19
1	0	Covered	T14,T18,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T14,T18,T19
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T14,T18,T19
1	0	Covered	T14,T18,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T14,T18,T19
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T21
0	1	Covered	T13,T14,T15
0	0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T20,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T18,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T18,T19

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T18,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T19,T21

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T19,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T18,T19

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T18,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T18,T19

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T18,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	31637137	31325871	0	0
gen_filter_match[0].MatchCheck00_A	31637137	9081014	0	0
gen_filter_match[0].MatchCheck01_A	31637137	2831721	0	0
gen_filter_match[0].MatchCheck10_A	31637137	2669708	0	0
gen_filter_match[0].MatchCheck11_A	31637137	16743428	0	0
gen_filter_match[1].MatchCheck00_A	31637137	10593016	0	0
gen_filter_match[1].MatchCheck01_A	31637137	1205290	0	0
gen_filter_match[1].MatchCheck10_A	31637137	977204	0	0
gen_filter_match[1].MatchCheck11_A	31637137	18550361	0	0
gen_filter_match[2].MatchCheck00_A	31637137	11139368	0	0
gen_filter_match[2].MatchCheck01_A	31637137	410104	0	0
gen_filter_match[2].MatchCheck10_A	31637137	1008177	0	0
gen_filter_match[2].MatchCheck11_A	31637137	18768222	0	0
gen_filter_match[3].MatchCheck00_A	31637137	11012973	0	0
gen_filter_match[3].MatchCheck01_A	31637137	359307	0	0
gen_filter_match[3].MatchCheck10_A	31637137	591628	0	0
gen_filter_match[3].MatchCheck11_A	31637137	19361963	0	0
gen_filter_match[4].MatchCheck00_A	31637137	12348616	0	0
gen_filter_match[4].MatchCheck01_A	31637137	14	0	0
gen_filter_match[4].MatchCheck10_A	31637137	99654	0	0
gen_filter_match[4].MatchCheck11_A	31637137	18877587	0	0
gen_filter_match[5].MatchCheck00_A	31637137	11951952	0	0
gen_filter_match[5].MatchCheck01_A	31637137	14	0	0
gen_filter_match[5].MatchCheck10_A	31637137	101	0	0
gen_filter_match[5].MatchCheck11_A	31637137	19373804	0	0
gen_filter_match[6].MatchCheck00_A	31637137	12278280	0	0
gen_filter_match[6].MatchCheck01_A	31637137	11	0	0
gen_filter_match[6].MatchCheck10_A	31637137	104	0	0
gen_filter_match[6].MatchCheck11_A	31637137	19047476	0	0
gen_filter_match[7].MatchCheck00_A	31637137	13098620	0	0
gen_filter_match[7].MatchCheck01_A	31637137	106885	0	0
gen_filter_match[7].MatchCheck10_A	31637137	65050	0	0
gen_filter_match[7].MatchCheck11_A	31637137	18055316	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	31325871	0	0
T13	67272	67210	0	0
T14	98250	98195	0	0
T15	98349	98264	0	0
T16	97780	97719	0	0
T17	32671	32591	0	0
T18	43269	42845	0	0
T19	87552	84878	0	0
T20	33195	33109	0	0
T21	133013	127038	0	0
T22	64536	64460	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	9081014	0	0
T13	67272	3	0	0
T14	98250	4	0	0
T15	98349	4	0	0
T16	97780	4	0	0
T17	32671	4	0	0
T18	43269	42845	0	0
T19	87552	63044	0	0
T20	33195	3	0	0
T21	133013	79225	0	0
T22	64536	3	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	2831721	0	0
T14	98250	33291	0	0
T15	98349	0	0	0
T16	97780	0	0	0
T17	32671	0	0	0
T18	43269	0	0	0
T19	87552	20093	0	0
T20	33195	0	0	0
T21	133013	32846	0	0
T22	64536	0	0	0
T33	0	27866	0	0
T34	0	3023	0	0
T53	34585	0	0	0
T100	0	33119	0	0
T101	0	6062	0	0
T102	0	32269	0	0
T103	0	10534	0	0
T104	0	32569	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	2669708	0	0
T14	98250	1	0	0
T15	98349	0	0	0
T16	97780	1	0	0
T17	32671	1	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	9944	0	0
T22	64536	0	0	0
T51	0	32627	0	0
T53	34585	0	0	0
T94	0	2114	0	0
T105	0	33140	0	0
T106	0	1	0	0
T107	0	32744	0	0
T108	0	10491	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	16743428	0	0
T13	67272	67207	0	0
T14	98250	64899	0	0
T15	98349	98260	0	0
T16	97780	97714	0	0
T17	32671	32586	0	0
T18	43269	0	0	0
T19	87552	1741	0	0
T20	33195	33106	0	0
T21	133013	5023	0	0
T22	64536	64457	0	0
T53	0	34529	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	10593016	0	0
T13	67272	3	0	0
T14	98250	64903	0	0
T15	98349	4	0	0
T16	97780	4	0	0
T17	32671	4	0	0
T18	43269	10538	0	0
T19	87552	43613	0	0
T20	33195	33109	0	0
T21	133013	56535	0	0
T22	64536	3	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	1205290	0	0
T14	98250	1	0	0
T15	98349	0	0	0
T16	97780	0	0	0
T17	32671	0	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T48	0	32233	0	0
T53	34585	0	0	0
T109	0	32363	0	0
T110	0	32005	0	0
T111	0	33681	0	0
T112	0	31670	0	0
T113	0	33400	0	0
T114	0	32265	0	0
T115	0	33438	0	0
T116	0	32517	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	977204	0	0
T14	98250	1	0	0
T15	98349	0	0	0
T16	97780	1	0	0
T17	32671	1	0	0
T18	43269	0	0	0
T19	87552	41265	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T48	0	32011	0	0
T52	0	32606	0	0
T53	34585	0	0	0
T106	0	1	0	0
T107	0	33441	0	0
T117	0	33539	0	0
T118	0	1	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	18550361	0	0
T13	67272	67207	0	0
T14	98250	33290	0	0
T15	98349	98260	0	0
T16	97780	97714	0	0
T17	32671	32586	0	0
T18	43269	32307	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	70503	0	0
T22	64536	64457	0	0
T34	0	3023	0	0
T53	0	34529	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	11139368	0	0
T13	67272	3	0	0
T14	98250	65993	0	0
T15	98349	4	0	0
T16	97780	4	0	0
T17	32671	4	0	0
T18	43269	10538	0	0
T19	87552	64784	0	0
T20	33195	3	0	0
T21	133013	91977	0	0
T22	64536	3	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	410104	0	0
T38	94	0	0	0
T98	12276	11092	0	0
T99	19246	0	0	0
T100	33199	0	0	0
T105	102918	0	0	0
T106	99394	0	0	0
T117	66155	0	0	0
T118	0	38132	0	0
T119	0	32121	0	0
T120	0	32048	0	0
T121	0	1	0	0
T122	0	2730	0	0
T123	0	33286	0	0
T124	0	32165	0	0
T125	0	32978	0	0
T126	0	32703	0	0
T127	98946	0	0	0
T128	19524	0	0	0
T129	33042	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	1008177	0	0
T14	98250	1	0	0
T15	98349	0	0	0
T16	97780	1	0	0
T17	32671	1	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T35	0	1	0	0
T46	0	32662	0	0
T53	34585	1	0	0
T106	0	1	0	0
T108	0	651	0	0
T109	0	32329	0	0
T127	0	33056	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	18768222	0	0
T13	67272	67207	0	0
T14	98250	32201	0	0
T15	98349	98260	0	0
T16	97780	97714	0	0
T17	32671	32586	0	0
T18	43269	32307	0	0
T19	87552	20094	0	0
T20	33195	33106	0	0
T21	133013	35061	0	0
T22	64536	64457	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	11012973	0	0
T13	67272	3	0	0
T14	98250	4	0	0
T15	98349	4	0	0
T16	97780	4	0	0
T17	32671	4	0	0
T18	43269	42845	0	0
T19	87552	64784	0	0
T20	33195	3	0	0
T21	133013	124824	0	0
T22	64536	3	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	359307	0	0
T32	72767	0	0	0
T33	54128	0	0	0
T110	0	2	0	0
T118	0	1	0	0
T124	0	33174	0	0
T127	98946	32148	0	0
T128	19524	0	0	0
T129	33042	0	0	0
T130	0	31377	0	0
T131	0	31729	0	0
T132	0	32205	0	0
T133	0	33255	0	0
T134	0	32982	0	0
T135	0	1	0	0
T136	1187	0	0	0
T137	32001	0	0	0
T138	33164	0	0	0
T139	32711	0	0	0
T140	12145	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	591628	0	0
T14	98250	2	0	0
T15	98349	0	0	0
T16	97780	2	0	0
T17	32671	1	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T35	0	1	0	0
T53	34585	1	0	0
T106	0	1	0	0
T110	0	2	0	0
T118	0	1	0	0
T138	0	33077	0	0
T141	0	2	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	19361963	0	0
T13	67272	67207	0	0
T14	98250	98189	0	0
T15	98349	98260	0	0
T16	97780	97713	0	0
T17	32671	32586	0	0
T18	43269	0	0	0
T19	87552	20094	0	0
T20	33195	33106	0	0
T21	133013	2214	0	0
T22	64536	64457	0	0
T53	0	34528	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	12348616	0	0
T13	67272	3	0	0
T14	98250	65496	0	0
T15	98349	4	0	0
T16	97780	4	0	0
T17	32671	4	0	0
T18	43269	10538	0	0
T19	87552	64784	0	0
T20	33195	33109	0	0
T21	133013	82034	0	0
T22	64536	3	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	14	0	0
T14	98250	1	0	0
T15	98349	0	0	0
T16	97780	0	0	0
T17	32671	0	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T53	34585	0	0	0
T110	0	2	0	0
T118	0	1	0	0
T135	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	99654	0	0
T14	98250	2	0	0
T15	98349	0	0	0
T16	97780	2	0	0
T17	32671	1	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T35	0	1	0	0
T53	34585	1	0	0
T106	0	2	0	0
T109	0	1	0	0
T110	0	3	0	0
T118	0	1	0	0
T141	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	18877587	0	0
T13	67272	67207	0	0
T14	98250	32696	0	0
T15	98349	98260	0	0
T16	97780	97713	0	0
T17	32671	32586	0	0
T18	43269	32307	0	0
T19	87552	20094	0	0
T20	33195	0	0	0
T21	133013	45004	0	0
T22	64536	64457	0	0
T53	0	34528	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	11951952	0	0
T13	67272	3	0	0
T14	98250	33295	0	0
T15	98349	4	0	0
T16	97780	4	0	0
T17	32671	5	0	0
T18	43269	10538	0	0
T19	87552	64784	0	0
T20	33195	3	0	0
T21	133013	101539	0	0
T22	64536	3	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	14	0	0
T14	98250	1	0	0
T15	98349	0	0	0
T16	97780	0	0	0
T17	32671	0	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T53	34585	0	0	0
T110	0	1	0	0
T118	0	1	0	0
T121	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	101	0	0
T14	98250	3	0	0
T15	98349	0	0	0
T16	97780	2	0	0
T17	32671	0	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T53	34585	1	0	0
T106	0	1	0	0
T109	0	1	0	0
T110	0	2	0	0
T118	0	1	0	0
T147	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	19373804	0	0
T13	67272	67207	0	0
T14	98250	64896	0	0
T15	98349	98260	0	0
T16	97780	97713	0	0
T17	32671	32586	0	0
T18	43269	32307	0	0
T19	87552	20094	0	0
T20	33195	33106	0	0
T21	133013	25499	0	0
T22	64536	64457	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	12278280	0	0
T13	67272	3	0	0
T14	98250	33296	0	0
T15	98349	4	0	0
T16	97780	5	0	0
T17	32671	5	0	0
T18	43269	10538	0	0
T19	87552	43613	0	0
T20	33195	33109	0	0
T21	133013	91977	0	0
T22	64536	3	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	11	0	0
T14	98250	1	0	0
T15	98349	0	0	0
T16	97780	0	0	0
T17	32671	0	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T53	34585	0	0	0
T109	0	1	0	0
T110	0	2	0	0
T121	0	1	0	0
T133	0	1	0	0
T142	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	104	0	0
T14	98250	2	0	0
T15	98349	0	0	0
T16	97780	1	0	0
T17	32671	1	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T53	34585	1	0	0
T106	0	1	0	0
T109	0	1	0	0
T141	0	1	0	0
T156	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	19047476	0	0
T13	67272	67207	0	0
T14	98250	64896	0	0
T15	98349	98260	0	0
T16	97780	97713	0	0
T17	32671	32585	0	0
T18	43269	32307	0	0
T19	87552	41265	0	0
T20	33195	0	0	0
T21	133013	35061	0	0
T22	64536	64457	0	0
T53	0	34528	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	13098620	0	0
T13	67272	3	0	0
T14	98250	5	0	0
T15	98349	4	0	0
T16	97780	5	0	0
T17	32671	5	0	0
T18	43269	42845	0	0
T19	87552	43613	0	0
T20	33195	3	0	0
T21	133013	124824	0	0
T22	64536	3	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	106885	0	0
T38	94	0	0	0
T99	19246	0	0	0
T100	33199	0	0	0
T105	102918	1	0	0
T106	99394	0	0	0
T109	0	1	0	0
T118	0	32821	0	0
T127	98946	0	0	0
T128	19524	0	0	0
T129	33042	0	0	0
T136	1187	0	0	0
T137	32001	0	0	0
T141	0	1	0	0
T148	0	1	0	0
T157	0	1	0	0
T158	0	31978	0	0
T159	0	1	0	0
T160	0	9460	0	0
T161	0	32617	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	65050	0	0
T14	98250	1	0	0
T15	98349	1	0	0
T16	97780	1	0	0
T17	32671	1	0	0
T18	43269	0	0	0
T19	87552	0	0	0
T20	33195	0	0	0
T21	133013	0	0	0
T22	64536	0	0	0
T35	0	1	0	0
T53	34585	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T139	0	1	0	0
T156	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31637137	18055316	0	0
T13	67272	67207	0	0
T14	98250	98189	0	0
T15	98349	98259	0	0
T16	97780	97713	0	0
T17	32671	32585	0	0
T18	43269	0	0	0
T19	87552	41265	0	0
T20	33195	33106	0	0
T21	133013	2214	0	0
T22	64536	64457	0	0
T53	0	34528	0	0