Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	7145	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1961	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1952	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1942	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2006	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2155	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2048	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2023	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2131	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1839	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1927	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2044	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2083	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2044	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2079	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2059	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2038	0	0
adc_en_ctl_rd_A	2147483647	1572	0	0
adc_fsm_rst_rd_A	2147483647	1580	0	0
adc_intr_ctl_rd_A	2147483647	1723	0	0
adc_lp_sample_ctl_rd_A	2147483647	1492	0	0
adc_pd_ctl_rd_A	2147483647	1918	0	0
adc_sample_ctl_rd_A	2147483647	1541	0	0
adc_wakeup_ctl_rd_A	2147483647	1619	0	0
intr_enable_rd_A	2147483647	2018	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7145	0	0
T7	16600	7	0	0
T8	446103	0	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T11	164702	0	0	0
T12	193140	2	0	0
T36	112347	1	0	0
T54	780226	1	0	0
T55	0	142	0	0
T56	0	358	0	0
T57	0	336	0	0
T58	0	474	0	0
T59	0	1	0	0
T62	3151	0	0	0
T68	0	1	0	0
T81	11026	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1961	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	73	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	4	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	2	0	0
T31	0	92	0	0
T54	0	137	0	0
T55	0	27	0	0
T56	0	1	0	0
T59	0	137	0	0
T66	0	5	0	0
T162	0	227	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1952	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	44	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	4	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	2	0	0
T31	0	80	0	0
T54	0	185	0	0
T55	0	6	0	0
T56	0	32	0	0
T59	0	87	0	0
T66	0	16	0	0
T162	0	181	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1942	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	12	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	5	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	0	0	0
T31	0	99	0	0
T54	0	191	0	0
T55	0	9	0	0
T56	0	23	0	0
T59	0	90	0	0
T66	0	9	0	0
T84	0	67	0	0
T162	0	207	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2006	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	33	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	1	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	6	0	0
T31	0	91	0	0
T54	0	157	0	0
T55	0	24	0	0
T56	0	4	0	0
T59	0	132	0	0
T66	0	5	0	0
T162	0	205	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2155	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	57	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	1	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	0	0	0
T31	0	84	0	0
T54	0	207	0	0
T55	0	15	0	0
T56	0	12	0	0
T59	0	89	0	0
T66	0	9	0	0
T84	0	132	0	0
T162	0	223	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	32	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	5	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	0	0	0
T31	0	85	0	0
T54	0	170	0	0
T55	0	16	0	0
T56	0	18	0	0
T59	0	94	0	0
T66	0	23	0	0
T84	0	94	0	0
T162	0	232	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2023	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	74	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	3	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	12	0	0
T31	0	77	0	0
T54	0	172	0	0
T55	0	10	0	0
T56	0	12	0	0
T59	0	108	0	0
T66	0	15	0	0
T162	0	209	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2131	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	27	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	3	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	8	0	0
T31	0	96	0	0
T54	0	120	0	0
T55	0	37	0	0
T56	0	22	0	0
T59	0	160	0	0
T66	0	14	0	0
T162	0	235	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1839	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	29	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	1	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	2	0	0
T31	0	91	0	0
T54	0	149	0	0
T55	0	30	0	0
T56	0	14	0	0
T59	0	75	0	0
T66	0	2	0	0
T162	0	249	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1927	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	21	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	1	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	5	0	0
T31	0	110	0	0
T54	0	162	0	0
T55	0	15	0	0
T56	0	35	0	0
T59	0	68	0	0
T66	0	6	0	0
T162	0	217	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2044	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	18	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	4	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	0	0	0
T31	0	94	0	0
T54	0	158	0	0
T55	0	17	0	0
T56	0	30	0	0
T59	0	94	0	0
T66	0	1	0	0
T84	0	103	0	0
T162	0	273	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2083	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	51	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	5	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	4	0	0
T31	0	95	0	0
T54	0	234	0	0
T55	0	7	0	0
T56	0	4	0	0
T59	0	67	0	0
T66	0	2	0	0
T162	0	215	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2044	0	0
T7	16600	0	0	0
T8	446103	88	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T11	164702	0	0	0
T12	193140	0	0	0
T28	30106	2	0	0
T31	27461	81	0	0
T54	0	200	0	0
T55	0	23	0	0
T56	0	48	0	0
T59	0	122	0	0
T62	3151	0	0	0
T66	0	7	0	0
T81	11026	0	0	0
T84	0	92	0	0
T162	0	195	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2079	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	47	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	5	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	0	0	0
T31	0	108	0	0
T54	0	244	0	0
T55	0	12	0	0
T56	0	24	0	0
T59	0	106	0	0
T66	0	22	0	0
T84	0	73	0	0
T162	0	217	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2059	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	46	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	3	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	7	0	0
T31	0	108	0	0
T54	0	209	0	0
T55	0	15	0	0
T56	0	3	0	0
T59	0	153	0	0
T66	0	13	0	0
T162	0	191	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2038	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	43	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	3	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	8	0	0
T31	0	103	0	0
T54	0	156	0	0
T55	0	7	0	0
T56	0	17	0	0
T59	0	81	0	0
T66	0	16	0	0
T162	0	220	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1572	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	34	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	6	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	0	0	0
T31	0	135	0	0
T54	0	118	0	0
T55	0	21	0	0
T56	0	11	0	0
T59	0	55	0	0
T66	0	2	0	0
T84	0	93	0	0
T162	0	200	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1580	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	9	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	5	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	9	0	0
T31	0	97	0	0
T54	0	69	0	0
T55	0	38	0	0
T56	0	44	0	0
T59	0	40	0	0
T84	0	115	0	0
T162	0	242	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1723	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	55	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	6	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	0	0	0
T31	0	90	0	0
T54	0	58	0	0
T55	0	18	0	0
T56	0	16	0	0
T59	0	30	0	0
T66	0	4	0	0
T84	0	216	0	0
T162	0	217	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1492	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	52	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	8	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	4	0	0
T31	0	77	0	0
T54	0	92	0	0
T55	0	50	0	0
T56	0	26	0	0
T59	0	43	0	0
T66	0	4	0	0
T162	0	235	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1918	0	0
T7	16600	0	0	0
T8	446103	37	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T11	164702	0	0	0
T12	193140	0	0	0
T28	30106	2	0	0
T31	27461	89	0	0
T54	0	138	0	0
T55	0	6	0	0
T56	0	27	0	0
T59	0	81	0	0
T62	3151	0	0	0
T66	0	2	0	0
T81	11026	0	0	0
T84	0	113	0	0
T162	0	218	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1541	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	50	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	6	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	2	0	0
T31	0	92	0	0
T54	0	70	0	0
T55	0	28	0	0
T56	0	19	0	0
T59	0	61	0	0
T66	0	5	0	0
T162	0	200	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1619	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	59	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	7	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	4	0	0
T31	0	105	0	0
T54	0	73	0	0
T55	0	20	0	0
T56	0	22	0	0
T59	0	44	0	0
T66	0	9	0	0
T162	0	242	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2018	0	0
T3	418872	0	0	0
T6	317672	0	0	0
T7	16600	0	0	0
T8	446103	26	0	0
T9	107585	0	0	0
T10	57903	0	0	0
T25	20972	3	0	0
T26	6761	0	0	0
T27	13802	0	0	0
T28	30106	3	0	0
T31	0	70	0	0
T54	0	77	0	0
T62	0	12	0	0
T64	0	15	0	0
T65	0	11	0	0
T66	0	9	0	0
T81	0	5	0	0