Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1191283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1148591

1

T1

283

T4

8

T5

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2055562	1			T1	418		T4	11		T5	20
values[0x0]	142034	1			T1	137		T4	6		T5	10
values[0x1]	142278	1			T1	142		T4	7		T5	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	959939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1379935

1

T1

432

T4

9

T5

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11459	1			T4	1		T2	23		T29	94
valid_sources[0x01]	7115	1			T1	4		T26	1		T11	2
valid_sources[0x02]	11515	1			T1	1		T2	47		T25	27
valid_sources[0x03]	8190	1			T1	1		T2	22		T26	1
valid_sources[0x04]	11892	1			T1	3		T5	1		T2	5
valid_sources[0x05]	14150	1			T1	2		T26	1		T29	5
valid_sources[0x06]	7389	1			T1	2		T2	1		T26	6
valid_sources[0x07]	7516	1			T1	2		T9	4		T11	1
valid_sources[0x08]	8104	1			T1	4		T2	2		T26	1
valid_sources[0x09]	9253	1			T1	5		T2	2		T26	4
valid_sources[0x0a]	6921	1			T1	2		T4	1		T5	2
valid_sources[0x0b]	9863	1			T1	2		T2	7		T26	3
valid_sources[0x0c]	7122	1			T1	3		T2	19		T26	3
valid_sources[0x0d]	13041	1			T1	3		T26	1		T8	1
valid_sources[0x0e]	7435	1			T1	2		T5	2		T2	21
valid_sources[0x0f]	6811	1			T1	4		T5	1		T26	2
valid_sources[0x10]	7069	1			T1	1		T2	1		T9	2
valid_sources[0x11]	7372	1			T1	1		T5	1		T2	4
valid_sources[0x12]	7703	1			T1	5		T2	5		T9	2
valid_sources[0x13]	7162	1			T1	2		T26	1		T27	35
valid_sources[0x14]	11010	1			T1	3		T2	14		T9	6
valid_sources[0x15]	11127	1			T1	1		T2	4		T26	2
valid_sources[0x16]	8371	1			T1	3		T2	28		T8	1
valid_sources[0x17]	20103	1			T1	4		T5	1		T2	33
valid_sources[0x18]	11927	1			T1	3		T2	15		T26	1
valid_sources[0x19]	7281	1			T1	5		T4	1		T2	49
valid_sources[0x1a]	7792	1			T1	6		T2	41		T27	25
valid_sources[0x1b]	8473	1			T1	3		T2	1		T26	1
valid_sources[0x1c]	7138	1			T5	1		T2	5		T26	7
valid_sources[0x1d]	8265	1			T1	1		T5	2		T2	33
valid_sources[0x1e]	9652	1			T1	3		T26	1		T27	20
valid_sources[0x1f]	7261	1			T1	4		T27	12		T11	4
valid_sources[0x20]	7598	1			T1	4		T2	12		T26	4
valid_sources[0x21]	6629	1			T1	2		T2	11		T11	4
valid_sources[0x22]	6946	1			T1	4		T2	17		T26	3
valid_sources[0x23]	6960	1			T1	2		T2	13		T11	3
valid_sources[0x24]	8300	1			T1	3		T2	32		T11	1
valid_sources[0x25]	7586	1			T2	1		T26	3		T11	3
valid_sources[0x26]	6908	1			T1	6		T4	1		T2	10
valid_sources[0x27]	9397	1			T1	1		T2	89		T27	17
valid_sources[0x28]	8200	1			T1	6		T2	24		T11	5
valid_sources[0x29]	6793	1			T1	1		T2	19		T26	6
valid_sources[0x2a]	11182	1			T1	1		T2	18		T8	1
valid_sources[0x2b]	12044	1			T1	5		T2	15		T42	1
valid_sources[0x2c]	12844	1			T1	3		T2	4		T11	3
valid_sources[0x2d]	11758	1			T1	3		T2	16		T11	3
valid_sources[0x2e]	11658	1			T1	2		T2	1		T11	5
valid_sources[0x2f]	23522	1			T1	5		T5	1		T2	24
valid_sources[0x30]	12236	1			T1	1		T27	22		T8	4
valid_sources[0x31]	7498	1			T1	2		T2	40		T27	7
valid_sources[0x32]	15810	1			T1	3		T2	27		T25	8
valid_sources[0x33]	7034	1			T1	2		T26	1		T11	1
valid_sources[0x34]	6966	1			T1	4		T2	24		T26	1
valid_sources[0x35]	6834	1			T2	2		T11	5		T43	1
valid_sources[0x36]	8347	1			T1	9		T2	7		T11	1
valid_sources[0x37]	7424	1			T1	1		T2	4		T9	12
valid_sources[0x38]	7169	1			T1	2		T2	1		T26	4
valid_sources[0x39]	7133	1			T1	3		T2	8		T9	3
valid_sources[0x3a]	7069	1			T1	2		T5	2		T2	27
valid_sources[0x3b]	9555	1			T1	2		T26	1		T11	2
valid_sources[0x3c]	7522	1			T1	4		T2	15		T26	3
valid_sources[0x3d]	7105	1			T1	4		T2	1		T26	2
valid_sources[0x3e]	7893	1			T1	2		T47	9		T34	8
valid_sources[0x3f]	7591	1			T1	2		T2	25		T8	10
valid_sources[0x40]	7411	1			T1	1		T26	3		T27	16
valid_sources[0x41]	7057	1			T1	3		T11	1		T34	11
valid_sources[0x42]	7278	1			T1	1		T4	1		T5	1
valid_sources[0x43]	11472	1			T1	1		T4	1		T11	2
valid_sources[0x44]	6982	1			T1	1		T27	1		T47	3
valid_sources[0x45]	7367	1			T1	6		T2	69		T29	13
valid_sources[0x46]	7474	1			T1	5		T4	1		T26	3
valid_sources[0x47]	7674	1			T1	1		T2	17		T27	34
valid_sources[0x48]	11437	1			T26	1		T27	3		T9	3
valid_sources[0x49]	7019	1			T1	1		T2	21		T26	1
valid_sources[0x4a]	9720	1			T1	1		T2	11		T26	1
valid_sources[0x4b]	15026	1			T1	2		T2	25		T26	4
valid_sources[0x4c]	8054	1			T1	1		T26	1		T28	42
valid_sources[0x4d]	7001	1			T1	1		T2	5		T29	7
valid_sources[0x4e]	8299	1			T2	9		T9	2		T11	6
valid_sources[0x4f]	8258	1			T1	8		T5	1		T26	7
valid_sources[0x50]	7009	1			T1	1		T2	29		T11	5
valid_sources[0x51]	6965	1			T1	5		T5	1		T2	8
valid_sources[0x52]	6702	1			T1	4		T5	1		T26	3
valid_sources[0x53]	7548	1			T1	5		T2	16		T33	18
valid_sources[0x54]	7285	1			T1	1		T42	1		T11	4
valid_sources[0x55]	7036	1			T2	2		T11	7		T34	6
valid_sources[0x56]	7263	1			T1	3		T4	1		T27	7
valid_sources[0x57]	11360	1			T1	2		T2	26		T11	4
valid_sources[0x58]	8254	1			T2	11		T11	1		T34	5
valid_sources[0x59]	11158	1			T1	3		T2	5		T26	6
valid_sources[0x5a]	7012	1			T2	34		T11	7		T34	3
valid_sources[0x5b]	7033	1			T1	2		T2	4		T26	2
valid_sources[0x5c]	9848	1			T1	1		T29	6		T11	10
valid_sources[0x5d]	7370	1			T1	8		T2	2		T9	1
valid_sources[0x5e]	6907	1			T1	2		T5	2		T2	10
valid_sources[0x5f]	17061	1			T1	5		T2	37		T26	2
valid_sources[0x60]	12569	1			T1	7		T26	1		T27	14
valid_sources[0x61]	7273	1			T1	8		T5	1		T2	1
valid_sources[0x62]	11419	1			T1	1		T2	3		T11	3
valid_sources[0x63]	7054	1			T1	2		T2	7		T27	13
valid_sources[0x64]	7308	1			T1	5		T2	35		T11	7
valid_sources[0x65]	7419	1			T1	6		T26	1		T11	3
valid_sources[0x66]	13860	1			T1	4		T2	27		T29	1
valid_sources[0x67]	8674	1			T1	2		T2	12		T26	3
valid_sources[0x68]	8389	1			T1	3		T2	27		T25	22
valid_sources[0x69]	6893	1			T1	3		T4	2		T2	3
valid_sources[0x6a]	8110	1			T1	2		T2	4		T11	5
valid_sources[0x6b]	7117	1			T1	1		T2	14		T26	5
valid_sources[0x6c]	7570	1			T1	2		T42	1		T11	2
valid_sources[0x6d]	11543	1			T1	5		T2	5		T26	1
valid_sources[0x6e]	7076	1			T1	2		T2	32		T11	1
valid_sources[0x6f]	8302	1			T1	2		T2	19		T26	3
valid_sources[0x70]	10713	1			T1	9		T2	4		T25	2
valid_sources[0x71]	7406	1			T1	8		T2	1		T26	1
valid_sources[0x72]	7105	1			T1	2		T11	6		T34	3
valid_sources[0x73]	8237	1			T1	3		T2	14		T26	1
valid_sources[0x74]	11272	1			T1	2		T2	5		T26	2
valid_sources[0x75]	8375	1			T1	2		T2	33		T26	3
valid_sources[0x76]	8994	1			T1	3		T2	34		T26	3
valid_sources[0x77]	7171	1			T1	2		T2	7		T26	1
valid_sources[0x78]	20933	1			T4	1		T26	1		T9	5
valid_sources[0x79]	7998	1			T2	5		T11	3		T43	4
valid_sources[0x7a]	6955	1			T1	2		T26	4		T33	10
valid_sources[0x7b]	10383	1			T1	3		T2	1		T26	5
valid_sources[0x7c]	14462	1			T1	4		T2	15		T26	4
valid_sources[0x7d]	7360	1			T1	1		T42	1		T11	5
valid_sources[0x7e]	7480	1			T2	17		T27	16		T10	48
valid_sources[0x7f]	6851	1			T1	3		T2	15		T9	12
valid_sources[0x80]	12469	1			T1	1		T2	8		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1025116

1

T1

56

T4

4

T5

11

values[0x0]

all_enables

biggest_size

71475

1

T1

113

T4

2

T5

2

values[0x1]

all_enables

biggest_size

52000

1

T1

114

T4

2

T5

2