Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27279	1			T1	6		T2	3		T9	3
auto[PWRUP]	89	1			T17	2		T80	1		T114	1
auto[ONEST_0]	62	1			T80	1		T114	2		T166	1
auto[ONEST_021]	16	1			T17	1		T178	1		T179	1
auto[ONEST_1]	75	1			T13	1		T16	1		T17	1
auto[ONEST_DONE]	4	1			T180	1		T181	1		T182	1
auto[LP_0]	123	1			T13	1		T16	3		T80	1
auto[LP_021]	26	1			T16	2		T17	1		T80	1
auto[LP_1]	136	1			T13	4		T16	2		T80	3
auto[LP_EVAL]	64	1			T17	1		T24	2		T80	1
auto[LP_SLP]	504	1			T13	6		T16	3		T17	5
auto[LP_PWRUP]	29	1			T17	1		T178	1		T84	1
auto[NP_0]	128	1			T13	2		T17	1		T80	1
auto[NP_021]	23	1			T17	1		T183	2		T184	1
auto[NP_1]	157	1			T16	1		T17	2		T80	2
auto[NP_EVAL]	37	1			T13	1		T114	1		T178	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T17

2

T114

2

T178

1

min

26868

1

T1

6

T2

3

T9

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26870	1			T1	6		T2	3		T9	3
pow[0x1]	6	1			T16	1		T169	1		T185	1
pow[0x2]	15	1			T114	1		T184	1		T186	1
pow[0x3]	35	1			T13	1		T16	1		T114	1
pow[0x4]	57	1			T13	1		T16	3		T178	1
pow[0x5]	103	1			T13	2		T16	2		T17	1
pow[0x6]	224	1			T13	3		T16	2		T17	3
pow[0x7]	463	1			T13	3		T16	4		T17	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

177

1

T13

3

T16

2

T17

1

min

26378

1

T1

6

T2

3

T9

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26379	1			T1	6		T2	3		T9	3
pow[0x5]	1	1			T187	1		-	-		-	-
pow[0x7]	4	1			T169	1		T188	1		T185	1
pow[0x8]	4	1			T179	2		T189	1		T190	1
pow[0x9]	12	1			T178	1		T84	1		T184	1
pow[0xa]	18	1			T80	1		T166	1		T183	1
pow[0xb]	34	1			T13	2		T16	1		T80	2
pow[0xc]	56	1			T13	1		T16	1		T17	1
pow[0xd]	120	1			T13	3		T16	2		T17	1
pow[0xe]	291	1			T13	4		T16	5		T17	3
pow[0xf]	561	1			T13	6		T16	4		T17	3