Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2283	1			T1	10		T9	2		T33	2
auto[PWRUP]	119	1			T13	3		T16	2		T17	3
auto[ONEST_0]	93	1			T13	2		T16	2		T17	1
auto[ONEST_021]	16	1			T17	1		T80	1		T84	1
auto[ONEST_1]	75	1			T13	1		T17	1		T40	1
auto[ONEST_DONE]	2	1			T276	1		T346	1		-	-
auto[LP_0]	123	1			T17	1		T80	1		T114	1
auto[LP_021]	28	1			T13	1		T17	1		T80	1
auto[LP_1]	125	1			T13	2		T17	1		T80	2
auto[LP_EVAL]	53	1			T24	1		T114	1		T178	3
auto[LP_SLP]	519	1			T13	7		T16	4		T17	6
auto[LP_PWRUP]	35	1			T16	1		T17	2		T24	1
auto[NP_0]	236	1			T13	3		T14	1		T16	1
auto[NP_021]	46	1			T16	1		T79	1		T114	1
auto[NP_1]	245	1			T14	3		T16	1		T17	4
auto[NP_EVAL]	39	1			T13	1		T16	1		T79	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T16

1

T188

1

T347

1

min

1919

1

T1

10

T9

2

T33

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1933	1			T1	10		T9	2		T33	2
pow[0x1]	3	1			T166	1		T348	1		T349	1
pow[0x2]	25	1			T17	1		T80	1		T114	2
pow[0x3]	46	1			T13	1		T16	1		T114	2
pow[0x4]	57	1			T16	1		T17	2		T114	1
pow[0x5]	147	1			T13	2		T16	1		T17	1
pow[0x6]	262	1			T13	5		T16	1		T17	5
pow[0x7]	504	1			T13	8		T16	4		T17	13

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T13

3

T16

3

T17

6

min

1287

1

T1

10

T9

2

T33

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1291	1			T1	10		T9	2		T33	2
pow[0x1]	14	1			T24	1		T276	1		T305	2
pow[0x2]	48	1			T14	2		T24	1		T39	2
pow[0x3]	56	1			T24	1		T39	2		T89	2
pow[0x4]	46	1			T24	1		T39	2		T195	7
pow[0x6]	1	1			T189	1		-	-		-	-
pow[0x7]	3	1			T114	1		T276	1		T350	1
pow[0x8]	5	1			T114	1		T97	1		T188	1
pow[0x9]	9	1			T16	1		T179	1		T350	1
pow[0xa]	21	1			T17	1		T178	1		T186	1
pow[0xb]	32	1			T24	1		T178	1		T166	1
pow[0xc]	73	1			T13	2		T17	1		T80	2
pow[0xd]	152	1			T13	1		T16	5		T17	2
pow[0xe]	293	1			T13	6		T16	4		T17	3
pow[0xf]	621	1			T13	9		T16	3		T17	16