Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T38,T12,T13
1	Covered	T13,T14,T16

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T38,T12,T13
1	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T12,T39,T57
1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T18
1	0	Covered	T13,T14,T15
1	1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T57,T81
0	1	Covered	T12,T57,T81
1	0	Covered	T12,T39,T57

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T21
1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T22
0	1	Covered	T12,T22,T56
1	0	Covered	T12,T14,T21

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T21
1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T22
0	1	Covered	T12,T22,T56
1	0	Covered	T12,T14,T21

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T12,T21,T22
1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T22
0	1	Covered	T12,T22,T39
1	0	Covered	T12,T21,T39

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T12,T21,T22
1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T22
0	1	Covered	T12,T22,T56
1	0	Covered	T12,T21,T22

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T22,T24
1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T56
0	1	Covered	T14,T22,T56
1	0	Covered	T14,T22,T24

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T12,T21,T22
1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T22
0	1	Covered	T12,T21,T22
1	0	Covered	T12,T21,T22

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T15
1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T21
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T12,T24,T57
1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T18
1	0	Covered	T13,T14,T15
1	1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T24,T57
0	1	Covered	T12,T24,T57
1	0	Covered	T12,T24,T57

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T21
1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T22
0	1	Covered	T12,T21,T22
1	0	Covered	T12,T14,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T21
1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T22
0	1	Covered	T12,T21,T22
1	0	Covered	T12,T14,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T12,T21,T39
1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T39
0	1	Covered	T12,T21,T39
1	0	Covered	T12,T21,T39

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T12,T21,T22
1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T22
0	1	Covered	T12,T21,T22
1	0	Covered	T12,T21,T22

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T22,T24
1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T56
0	1	Covered	T14,T22,T56
1	0	Covered	T14,T22,T24

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T12,T21,T22
1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T22
0	1	Covered	T12,T21,T22
1	0	Covered	T12,T21,T22

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T15
1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T21
1	0	Covered	T12,T13,T14
1	1	Covered	T38,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T12,T13
1	0	1	Covered	T12,T15,T18
1	1	0	Covered	T12,T15,T18
1	1	1	Covered	T12,T13,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T12,T13,T15
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T13,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T12,T13,T15
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T13,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T12,T13
1	0	1	Covered	T12,T15,T18
1	1	0	Covered	T12,T15,T18
1	1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T12,T13
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T15,T18,T20
1	1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T12,T13
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T12,T15,T18
1	1	1	Covered	T12,T15,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T15,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T15,T18

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T12,T13
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T12,T15,T18
1	1	1	Covered	T12,T15,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T15,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T15,T18

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T12,T13
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T12,T14,T15
1	1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T12,T13
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T12,T15,T18
1	1	1	Covered	T12,T15,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T15,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T12,T13
1	0	1	Covered	T12,T15,T18
1	1	0	Covered	T12,T15,T18
1	1	1	Covered	T12,T15,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T15,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T38,T12,T13
1	1	Covered	T12,T15,T18

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T15,T16
1	1	Covered	T12,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T15,T16
1	1	Covered	T12,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T15,T18

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T15,T18

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T15,T18

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T15,T18

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T14,T16
0	1	Covered	T12,T13,T14
0	0	Covered	T38,T12,T13

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T39,T57

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T24,T57

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T14,T21

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T14,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T14,T21

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T14,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T21,T22

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T21,T39

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T21,T22

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T21,T22

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T14,T22,T24

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T14,T22,T24

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T21,T22

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T21,T22

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T12,T13
0	Covered	T12,T14,T15

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32039750	31730010	0	0
gen_filter_match[0].MatchCheck00_A	32039750	8828626	0	0
gen_filter_match[0].MatchCheck01_A	32039750	3037546	0	0
gen_filter_match[0].MatchCheck10_A	32039750	2480270	0	0
gen_filter_match[0].MatchCheck11_A	32039750	17383568	0	0
gen_filter_match[1].MatchCheck00_A	32039750	10621788	0	0
gen_filter_match[1].MatchCheck01_A	32039750	1322864	0	0
gen_filter_match[1].MatchCheck10_A	32039750	1242299	0	0
gen_filter_match[1].MatchCheck11_A	32039750	18543059	0	0
gen_filter_match[2].MatchCheck00_A	32039750	11039334	0	0
gen_filter_match[2].MatchCheck01_A	32039750	597257	0	0
gen_filter_match[2].MatchCheck10_A	32039750	550226	0	0
gen_filter_match[2].MatchCheck11_A	32039750	19543193	0	0
gen_filter_match[3].MatchCheck00_A	32039750	11418805	0	0
gen_filter_match[3].MatchCheck01_A	32039750	547406	0	0
gen_filter_match[3].MatchCheck10_A	32039750	357438	0	0
gen_filter_match[3].MatchCheck11_A	32039750	19406361	0	0
gen_filter_match[4].MatchCheck00_A	32039750	11813347	0	0
gen_filter_match[4].MatchCheck01_A	32039750	33108	0	0
gen_filter_match[4].MatchCheck10_A	32039750	66503	0	0
gen_filter_match[4].MatchCheck11_A	32039750	19817052	0	0
gen_filter_match[5].MatchCheck00_A	32039750	11986746	0	0
gen_filter_match[5].MatchCheck01_A	32039750	32318	0	0
gen_filter_match[5].MatchCheck10_A	32039750	33138	0	0
gen_filter_match[5].MatchCheck11_A	32039750	19677808	0	0
gen_filter_match[6].MatchCheck00_A	32039750	12281609	0	0
gen_filter_match[6].MatchCheck01_A	32039750	67135	0	0
gen_filter_match[6].MatchCheck10_A	32039750	31837	0	0
gen_filter_match[6].MatchCheck11_A	32039750	19349429	0	0
gen_filter_match[7].MatchCheck00_A	32039750	12452711	0	0
gen_filter_match[7].MatchCheck01_A	32039750	57009	0	0
gen_filter_match[7].MatchCheck10_A	32039750	98884	0	0
gen_filter_match[7].MatchCheck11_A	32039750	19121406	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	31730010	0	0
T12	97513	97430	0	0
T13	22456	19318	0	0
T14	24738	24094	0	0
T15	65415	65365	0	0
T16	15406	13511	0	0
T17	22851	18604	0	0
T18	66035	65980	0	0
T19	1145	1061	0	0
T20	65025	64926	0	0
T38	845	9	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	8828626	0	0
T12	97513	3	0	0
T13	22456	19026	0	0
T14	24738	24094	0	0
T15	65415	3	0	0
T16	15406	12073	0	0
T17	22851	18589	0	0
T18	66035	3	0	0
T19	1145	1061	0	0
T20	65025	3	0	0
T38	845	9	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	3037546	0	0
T21	31971	31871	0	0
T22	67635	0	0	0
T23	96272	0	0	0
T24	13836	9678	0	0
T39	21038	1811	0	0
T40	0	23618	0	0
T41	0	33698	0	0
T45	674	0	0	0
T46	100420	0	0	0
T56	33369	0	0	0
T57	65166	0	0	0
T80	14388	0	0	0
T82	0	33379	0	0
T83	0	32925	0	0
T84	0	32026	0	0
T85	0	32883	0	0
T86	0	32088	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	2480270	0	0
T12	97513	31965	0	0
T13	22456	0	0	0
T14	24738	0	0	0
T15	65415	0	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	1	0	0
T19	1145	0	0	0
T20	65025	0	0	0
T21	31971	0	0	0
T22	0	32319	0	0
T81	0	32989	0	0
T87	0	32600	0	0
T88	0	32351	0	0
T89	0	7585	0	0
T90	0	33029	0	0
T91	0	32611	0	0
T92	0	1	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	17383568	0	0
T12	97513	65462	0	0
T13	22456	292	0	0
T14	24738	0	0	0
T15	65415	65362	0	0
T16	15406	1438	0	0
T17	22851	15	0	0
T18	66035	65976	0	0
T19	1145	0	0	0
T20	65025	64923	0	0
T21	31971	0	0	0
T23	0	96200	0	0
T24	0	1155	0	0
T46	0	100341	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	10621788	0	0
T12	97513	3	0	0
T13	22456	19318	0	0
T14	24738	15591	0	0
T15	65415	3	0	0
T16	15406	13511	0	0
T17	22851	18604	0	0
T18	66035	3	0	0
T19	1145	1061	0	0
T20	65025	3	0	0
T38	845	9	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	1322864	0	0
T12	97513	32282	0	0
T13	22456	0	0	0
T14	24738	0	0	0
T15	65415	0	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	0	0	0
T19	1145	0	0	0
T20	65025	0	0	0
T21	31971	0	0	0
T41	0	32700	0	0
T93	0	1	0	0
T94	0	33414	0	0
T95	0	32238	0	0
T96	0	33618	0	0
T97	0	948	0	0
T98	0	32580	0	0
T99	0	32414	0	0
T100	0	32194	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	1242299	0	0
T14	24738	1	0	0
T15	65415	0	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	1	0	0
T19	1145	0	0	0
T20	65025	0	0	0
T21	31971	0	0	0
T22	67635	0	0	0
T39	0	3548	0	0
T45	674	0	0	0
T81	0	31655	0	0
T85	0	32772	0	0
T90	0	65669	0	0
T92	0	1	0	0
T101	0	32394	0	0
T102	0	32480	0	0
T103	0	32692	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	18543059	0	0
T12	97513	65145	0	0
T13	22456	0	0	0
T14	24738	8502	0	0
T15	65415	65362	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	65976	0	0
T19	1145	0	0	0
T20	65025	64923	0	0
T21	31971	31871	0	0
T22	0	64423	0	0
T23	0	96200	0	0
T46	0	100341	0	0
T57	0	65066	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	11039334	0	0
T12	97513	65465	0	0
T13	22456	19318	0	0
T14	24738	590	0	0
T15	65415	3	0	0
T16	15406	13511	0	0
T17	22851	18604	0	0
T18	66035	3	0	0
T19	1145	1061	0	0
T20	65025	3	0	0
T38	845	9	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	597257	0	0
T40	26726	0	0	0
T79	21641	0	0	0
T82	96659	0	0	0
T87	97330	0	0	0
T91	0	33437	0	0
T93	67353	1	0	0
T94	0	32437	0	0
T100	0	1	0	0
T104	0	32873	0	0
T105	0	33455	0	0
T106	0	32142	0	0
T107	0	32940	0	0
T108	0	32076	0	0
T109	0	1	0	0
T110	8398	0	0	0
T111	7925	0	0	0
T112	66169	0	0	0
T113	5420	0	0	0
T114	21355	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	550226	0	0
T14	24738	8505	0	0
T15	65415	0	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	1	0	0
T19	1145	0	0	0
T20	65025	0	0	0
T21	31971	0	0	0
T22	67635	0	0	0
T39	0	13192	0	0
T45	674	0	0	0
T88	0	32908	0	0
T92	0	1	0	0
T115	0	33629	0	0
T116	0	36352	0	0
T117	0	2	0	0
T118	0	33627	0	0
T119	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	19543193	0	0
T12	97513	31965	0	0
T13	22456	0	0	0
T14	24738	14999	0	0
T15	65415	65362	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	65976	0	0
T19	1145	0	0	0
T20	65025	64923	0	0
T21	31971	31871	0	0
T22	0	32104	0	0
T23	0	96200	0	0
T46	0	100341	0	0
T57	0	65066	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	11418805	0	0
T12	97513	3	0	0
T13	22456	19318	0	0
T14	24738	9093	0	0
T15	65415	3	0	0
T16	15406	13511	0	0
T17	22851	18604	0	0
T18	66035	3	0	0
T19	1145	1061	0	0
T20	65025	3	0	0
T38	845	9	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	547406	0	0
T22	67635	32104	0	0
T23	96272	0	0	0
T24	13836	0	0	0
T39	21038	0	0	0
T45	674	0	0	0
T46	100420	0	0	0
T56	33369	0	0	0
T57	65166	0	0	0
T80	14388	0	0	0
T86	113157	32409	0	0
T100	0	1	0	0
T109	0	1	0	0
T120	0	1	0	0
T121	0	31993	0	0
T122	0	32289	0	0
T123	0	2	0	0
T124	0	33397	0	0
T125	0	32522	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	357438	0	0
T14	24738	2	0	0
T15	65415	0	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	1	0	0
T19	1145	0	0	0
T20	65025	0	0	0
T21	31971	0	0	0
T22	67635	0	0	0
T45	674	0	0	0
T82	0	32391	0	0
T92	0	2	0	0
T93	0	1	0	0
T95	0	34458	0	0
T126	0	1	0	0
T127	0	32077	0	0
T128	0	32797	0	0
T129	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	19406361	0	0
T12	97513	97427	0	0
T13	22456	0	0	0
T14	24738	14999	0	0
T15	65415	65362	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	65976	0	0
T19	1145	0	0	0
T20	65025	64923	0	0
T21	31971	31871	0	0
T23	0	96200	0	0
T39	0	16740	0	0
T46	0	100341	0	0
T93	0	67258	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	11813347	0	0
T12	97513	31968	0	0
T13	22456	19318	0	0
T14	24738	15591	0	0
T15	65415	3	0	0
T16	15406	13511	0	0
T17	22851	18604	0	0
T18	66035	3	0	0
T19	1145	1061	0	0
T20	65025	3	0	0
T38	845	9	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	33108	0	0
T96	100191	33092	0	0
T100	0	1	0	0
T105	98251	0	0	0
T109	0	1	0	0
T115	98971	0	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	33009	0	0	0
T137	32900	0	0	0
T138	1172	0	0	0
T139	67041	0	0	0
T140	98603	0	0	0
T141	57619	0	0	0
T142	976	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	66503	0	0
T12	97513	33180	0	0
T13	22456	0	0	0
T14	24738	2	0	0
T15	65415	0	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	1	0	0
T19	1145	0	0	0
T20	65025	0	0	0
T21	31971	0	0	0
T92	0	2	0	0
T93	0	1	0	0
T105	0	1	0	0
T120	0	1	0	0
T126	0	1	0	0
T129	0	1	0	0
T136	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	19817052	0	0
T12	97513	32282	0	0
T13	22456	0	0	0
T14	24738	8501	0	0
T15	65415	65362	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	65976	0	0
T19	1145	0	0	0
T20	65025	64923	0	0
T21	31971	0	0	0
T22	0	32319	0	0
T23	0	96200	0	0
T39	0	5359	0	0
T46	0	100341	0	0
T57	0	31815	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	11986746	0	0
T12	97513	65148	0	0
T13	22456	19318	0	0
T14	24738	591	0	0
T15	65415	3	0	0
T16	15406	13511	0	0
T17	22851	18604	0	0
T18	66035	3	0	0
T19	1145	1061	0	0
T20	65025	3	0	0
T38	845	9	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	32318	0	0
T41	66477	0	0	0
T88	98366	0	0	0
T94	98099	1	0	0
T100	0	1	0	0
T109	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T143	97351	1	0	0
T144	32354	32292	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	1	0	0
T148	33488	0	0	0
T149	99119	0	0	0
T150	32868	0	0	0
T151	732	0	0	0
T152	1224	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	33138	0	0
T14	24738	3	0	0
T15	65415	0	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	2	0	0
T19	1145	0	0	0
T20	65025	0	0	0
T21	31971	0	0	0
T22	67635	0	0	0
T45	674	0	0	0
T92	0	2	0	0
T93	0	1	0	0
T105	0	1	0	0
T117	0	2	0	0
T126	0	1	0	0
T136	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	19677808	0	0
T12	97513	32282	0	0
T13	22456	0	0	0
T14	24738	23500	0	0
T15	65415	65362	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	65975	0	0
T19	1145	0	0	0
T20	65025	64923	0	0
T21	31971	0	0	0
T22	0	32104	0	0
T23	0	96200	0	0
T24	0	9678	0	0
T39	0	3548	0	0
T46	0	100341	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	12281609	0	0
T12	97513	31968	0	0
T13	22456	19318	0	0
T14	24738	15592	0	0
T15	65415	3	0	0
T16	15406	13511	0	0
T17	22851	18604	0	0
T18	66035	4	0	0
T19	1145	1061	0	0
T20	65025	3	0	0
T38	845	9	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	67135	0	0
T106	65432	1	0	0
T109	0	1	0	0
T120	98402	1	0	0
T123	0	3	0	0
T130	0	2	0	0
T143	97351	1	0	0
T155	0	31762	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	35352	0	0
T159	1929	0	0	0
T160	33400	0	0	0
T161	99254	0	0	0
T162	32148	0	0	0
T163	65784	0	0	0
T164	67451	0	0	0
T165	67376	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	31837	0	0
T14	24738	2	0	0
T15	65415	0	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	1	0	0
T19	1145	0	0	0
T20	65025	0	0	0
T21	31971	0	0	0
T22	67635	0	0	0
T45	674	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T105	0	1	0	0
T126	0	1	0	0
T129	0	1	0	0
T136	0	1	0	0
T166	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	19349429	0	0
T12	97513	65462	0	0
T13	22456	0	0	0
T14	24738	8500	0	0
T15	65415	65362	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	65975	0	0
T19	1145	0	0	0
T20	65025	64923	0	0
T21	31971	31871	0	0
T22	0	32319	0	0
T23	0	96200	0	0
T39	0	5359	0	0
T46	0	100341	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	12452711	0	0
T12	97513	33183	0	0
T13	22456	19318	0	0
T14	24738	24094	0	0
T15	65415	3	0	0
T16	15406	13511	0	0
T17	22851	18604	0	0
T18	66035	4	0	0
T19	1145	1061	0	0
T20	65025	3	0	0
T38	845	9	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	57009	0	0
T100	0	1	0	0
T101	97422	1	0	0
T104	66755	0	0	0
T109	0	1	0	0
T120	0	1	0	0
T131	0	1	0	0
T133	0	1	0	0
T143	0	1	0	0
T156	0	1	0	0
T167	0	1	0	0
T168	0	5755	0	0
T169	22930	0	0	0
T170	7069	0	0	0
T171	32892	0	0	0
T172	780	0	0	0
T173	68039	0	0	0
T174	98740	0	0	0
T175	1317	0	0	0
T176	5495	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	98884	0	0
T18	66035	1	0	0
T19	1145	0	0	0
T20	65025	0	0	0
T21	31971	0	0	0
T22	67635	0	0	0
T23	96272	0	0	0
T24	13836	0	0	0
T45	674	0	0	0
T46	100420	0	0	0
T56	33369	0	0	0
T84	0	1	0	0
T92	0	1	0	0
T101	0	1	0	0
T105	0	1	0	0
T126	0	1	0	0
T136	0	1	0	0
T139	0	1	0	0
T141	0	33199	0	0
T177	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32039750	19121406	0	0
T12	97513	64247	0	0
T13	22456	0	0	0
T14	24738	0	0	0
T15	65415	65362	0	0
T16	15406	0	0	0
T17	22851	0	0	0
T18	66035	65975	0	0
T19	1145	0	0	0
T20	65025	64923	0	0
T21	31971	0	0	0
T22	0	32104	0	0
T23	0	96200	0	0
T24	0	9678	0	0
T39	0	5359	0	0
T46	0	100341	0	0
T56	0	33284	0	0