Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6828	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2598	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2601	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2763	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2810	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2746	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2517	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2709	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2549	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2635	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2743	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2580	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2797	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2584	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2570	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2575	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2709	0	0
adc_en_ctl_rd_A	2147483647	1948	0	0
adc_fsm_rst_rd_A	2147483647	1788	0	0
adc_intr_ctl_rd_A	2147483647	2074	0	0
adc_lp_sample_ctl_rd_A	2147483647	1847	0	0
adc_pd_ctl_rd_A	2147483647	2526	0	0
adc_sample_ctl_rd_A	2147483647	1792	0	0
adc_wakeup_ctl_rd_A	2147483647	1821	0	0
intr_enable_rd_A	2147483647	2371	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6828	0	0
T1	134060	1	0	0
T2	272767	0	0	0
T3	9802	0	0	0
T4	24954	0	0	0
T5	45814	0	0	0
T25	21395	505	0	0
T26	13782	469	0	0
T27	14788	428	0	0
T28	21251	0	0	0
T29	55195	542	0	0
T35	0	1	0	0
T58	0	337	0	0
T61	0	46	0	0
T62	0	445	0	0
T63	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2598	0	0
T2	272767	189	0	0
T3	9802	4	0	0
T6	0	16	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	27	0	0
T30	0	4	0	0
T32	15805	0	0	0
T33	47352	5	0	0
T34	0	152	0	0
T44	0	57	0	0
T58	0	30	0	0
T60	0	131	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2601	0	0
T2	272767	208	0	0
T3	9802	13	0	0
T6	0	11	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	20	0	0
T30	0	20	0	0
T32	15805	0	0	0
T33	47352	10	0	0
T34	0	226	0	0
T44	0	85	0	0
T58	0	12	0	0
T60	0	148	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2763	0	0
T2	272767	232	0	0
T3	9802	9	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	36	0	0
T30	0	20	0	0
T32	15805	0	0	0
T33	47352	17	0	0
T34	0	207	0	0
T36	0	202	0	0
T44	0	49	0	0
T58	0	31	0	0
T60	0	146	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2810	0	0
T2	272767	179	0	0
T3	9802	7	0	0
T6	0	20	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	31	0	0
T30	0	23	0	0
T32	15805	0	0	0
T33	47352	5	0	0
T34	0	200	0	0
T44	0	74	0	0
T58	0	37	0	0
T60	0	166	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2746	0	0
T2	272767	178	0	0
T3	9802	14	0	0
T6	0	9	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	6	0	0
T30	0	18	0	0
T32	15805	0	0	0
T33	47352	19	0	0
T34	0	171	0	0
T44	0	112	0	0
T58	0	32	0	0
T60	0	182	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2517	0	0
T2	272767	188	0	0
T3	9802	5	0	0
T6	0	9	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	4	0	0
T30	0	5	0	0
T32	15805	0	0	0
T33	47352	10	0	0
T34	0	148	0	0
T44	0	76	0	0
T58	0	15	0	0
T60	0	119	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2709	0	0
T2	272767	200	0	0
T3	9802	9	0	0
T6	0	10	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	1	0	0
T30	0	22	0	0
T32	15805	0	0	0
T33	47352	7	0	0
T34	0	178	0	0
T44	0	122	0	0
T58	0	19	0	0
T60	0	212	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2549	0	0
T2	272767	169	0	0
T3	9802	20	0	0
T6	0	30	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	11	0	0
T30	0	8	0	0
T32	15805	0	0	0
T33	47352	9	0	0
T34	0	165	0	0
T44	0	79	0	0
T58	0	16	0	0
T60	0	212	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2635	0	0
T2	272767	204	0	0
T3	9802	3	0	0
T6	0	10	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	5	0	0
T30	0	10	0	0
T32	15805	0	0	0
T33	47352	14	0	0
T34	0	148	0	0
T44	0	99	0	0
T58	0	37	0	0
T60	0	174	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2743	0	0
T2	272767	190	0	0
T3	9802	8	0	0
T6	0	11	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	20	0	0
T30	0	32	0	0
T32	15805	0	0	0
T33	47352	7	0	0
T34	0	249	0	0
T44	0	77	0	0
T58	0	20	0	0
T60	0	132	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2580	0	0
T2	272767	204	0	0
T3	9802	9	0	0
T6	0	10	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	9	0	0
T30	0	8	0	0
T32	15805	0	0	0
T33	47352	7	0	0
T34	0	218	0	0
T44	0	78	0	0
T58	0	8	0	0
T60	0	181	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2797	0	0
T2	272767	227	0	0
T3	9802	11	0	0
T6	0	3	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	34	0	0
T30	0	21	0	0
T32	15805	0	0	0
T33	47352	4	0	0
T34	0	174	0	0
T44	0	117	0	0
T58	0	32	0	0
T60	0	131	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2584	0	0
T2	272767	173	0	0
T3	9802	16	0	0
T6	0	8	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	24	0	0
T30	0	28	0	0
T32	15805	0	0	0
T33	47352	8	0	0
T34	0	172	0	0
T44	0	87	0	0
T58	0	38	0	0
T60	0	149	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2570	0	0
T2	272767	173	0	0
T3	9802	15	0	0
T6	0	6	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	14	0	0
T30	0	15	0	0
T32	15805	0	0	0
T33	47352	8	0	0
T34	0	212	0	0
T44	0	68	0	0
T58	0	9	0	0
T60	0	193	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2575	0	0
T2	272767	236	0	0
T3	9802	9	0	0
T6	0	16	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	11	0	0
T30	0	8	0	0
T32	15805	0	0	0
T33	47352	12	0	0
T34	0	212	0	0
T44	0	48	0	0
T58	0	21	0	0
T60	0	134	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2709	0	0
T2	272767	242	0	0
T3	9802	10	0	0
T6	0	9	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	18	0	0
T30	0	24	0	0
T32	15805	0	0	0
T33	47352	3	0	0
T34	0	161	0	0
T44	0	67	0	0
T58	0	28	0	0
T60	0	169	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1948	0	0
T2	272767	162	0	0
T3	9802	17	0	0
T6	0	2	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	2	0	0
T30	0	9	0	0
T32	15805	0	0	0
T33	47352	7	0	0
T34	0	65	0	0
T44	0	42	0	0
T58	0	48	0	0
T60	0	90	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1788	0	0
T2	272767	209	0	0
T3	9802	7	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	8	0	0
T30	0	1	0	0
T32	15805	0	0	0
T33	47352	12	0	0
T34	0	68	0	0
T36	0	204	0	0
T44	0	22	0	0
T58	0	12	0	0
T60	0	47	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2074	0	0
T2	272767	209	0	0
T3	9802	2	0	0
T6	0	6	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	2	0	0
T30	0	7	0	0
T32	15805	0	0	0
T33	47352	5	0	0
T34	0	69	0	0
T44	0	37	0	0
T58	0	15	0	0
T60	0	59	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T2	272767	214	0	0
T3	9802	7	0	0
T6	0	6	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	13	0	0
T30	0	2	0	0
T32	15805	0	0	0
T33	47352	10	0	0
T34	0	74	0	0
T44	0	16	0	0
T58	0	8	0	0
T60	0	68	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2526	0	0
T2	272767	190	0	0
T3	9802	11	0	0
T6	0	4	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	14	0	0
T30	0	20	0	0
T32	15805	0	0	0
T33	47352	3	0	0
T34	0	180	0	0
T44	0	68	0	0
T58	0	19	0	0
T60	0	136	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1792	0	0
T2	272767	172	0	0
T3	9802	2	0	0
T6	0	4	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	1	0	0
T30	0	7	0	0
T32	15805	0	0	0
T33	47352	1	0	0
T34	0	47	0	0
T44	0	35	0	0
T58	0	16	0	0
T60	0	69	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1821	0	0
T2	272767	197	0	0
T3	9802	5	0	0
T6	0	8	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	14	0	0
T30	0	1	0	0
T32	15805	0	0	0
T33	47352	4	0	0
T34	0	68	0	0
T44	0	51	0	0
T58	0	10	0	0
T60	0	74	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2371	0	0
T2	272767	200	0	0
T3	9802	8	0	0
T4	24954	6	0	0
T5	45814	0	0	0
T9	12898	0	0	0
T25	21395	0	0	0
T26	13782	0	0	0
T27	14788	0	0	0
T28	21251	0	0	0
T29	55195	12	0	0
T30	0	7	0	0
T33	0	13	0	0
T34	0	56	0	0
T44	0	46	0	0
T58	0	8	0	0
T60	0	74	0	0