Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1189519	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1144661

1

T1

276

T2

93

T5

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2053538	1			T1	495		T2	104		T5	19
values[0x0]	139769	1			T1	135		T2	39		T5	10
values[0x1]	140873	1			T1	143		T2	29		T5	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	958192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1375988

1

T1

443

T2

115

T5

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7370	1			T1	3		T2	2		T4	4
valid_sources[0x01]	7077	1			T4	13		T6	1		T10	2
valid_sources[0x02]	11228	1			T1	7		T26	2		T6	1
valid_sources[0x03]	9211	1			T2	3		T4	2		T6	4
valid_sources[0x04]	10697	1			T1	7		T4	10		T6	1
valid_sources[0x05]	8482	1			T1	6		T2	1		T4	3
valid_sources[0x06]	7724	1			T1	3		T4	3		T27	1
valid_sources[0x07]	7859	1			T2	4		T4	2		T26	2
valid_sources[0x08]	6807	1			T1	2		T6	1		T10	5
valid_sources[0x09]	6880	1			T2	1		T6	3		T10	1
valid_sources[0x0a]	6664	1			T1	2		T2	4		T6	2
valid_sources[0x0b]	6712	1			T4	1		T6	1		T10	4
valid_sources[0x0c]	7718	1			T1	6		T2	1		T25	1
valid_sources[0x0d]	7880	1			T2	2		T6	7		T10	4
valid_sources[0x0e]	8636	1			T1	1		T4	2		T26	1
valid_sources[0x0f]	6879	1			T1	2		T2	1		T6	4
valid_sources[0x10]	7933	1			T4	1		T6	2		T10	5
valid_sources[0x11]	7831	1			T2	1		T5	4		T6	6
valid_sources[0x12]	6660	1			T1	6		T2	2		T6	3
valid_sources[0x13]	7467	1			T4	4		T6	4		T10	7
valid_sources[0x14]	6933	1			T4	3		T26	1		T6	3
valid_sources[0x15]	7630	1			T1	3		T6	4		T10	3
valid_sources[0x16]	6901	1			T1	8		T24	1		T4	2
valid_sources[0x17]	8877	1			T26	1		T6	1		T40	6
valid_sources[0x18]	6550	1			T1	5		T2	1		T26	1
valid_sources[0x19]	6809	1			T1	5		T2	2		T6	1
valid_sources[0x1a]	12006	1			T4	7		T6	2		T10	5
valid_sources[0x1b]	7014	1			T2	2		T26	1		T10	1
valid_sources[0x1c]	8840	1			T1	2		T2	3		T4	13
valid_sources[0x1d]	6931	1			T2	2		T24	2		T6	2
valid_sources[0x1e]	9505	1			T6	7		T9	1		T10	2
valid_sources[0x1f]	9239	1			T1	13		T2	3		T4	14
valid_sources[0x20]	11457	1			T1	1		T4	1		T26	3
valid_sources[0x21]	8524	1			T1	2		T2	2		T4	1
valid_sources[0x22]	6788	1			T1	3		T2	1		T5	7
valid_sources[0x23]	7703	1			T24	1		T4	1		T9	1
valid_sources[0x24]	9517	1			T1	1		T4	3		T26	3
valid_sources[0x25]	7967	1			T1	1		T26	1		T6	5
valid_sources[0x26]	6517	1			T2	1		T4	10		T6	3
valid_sources[0x27]	16788	1			T1	8		T27	6		T9	9
valid_sources[0x28]	7603	1			T1	7		T26	2		T6	3
valid_sources[0x29]	8277	1			T1	5		T4	6		T6	1
valid_sources[0x2a]	7028	1			T1	5		T2	2		T24	1
valid_sources[0x2b]	11312	1			T2	1		T4	5		T26	2
valid_sources[0x2c]	6690	1			T2	1		T26	1		T6	6
valid_sources[0x2d]	16820	1			T1	2		T2	1		T4	1
valid_sources[0x2e]	11629	1			T2	1		T4	2		T6	3
valid_sources[0x2f]	6725	1			T2	1		T4	8		T6	3
valid_sources[0x30]	6780	1			T1	4		T4	10		T25	1
valid_sources[0x31]	7824	1			T26	1		T6	1		T10	5
valid_sources[0x32]	9336	1			T2	1		T6	1		T10	2
valid_sources[0x33]	9242	1			T1	1		T4	1		T40	3
valid_sources[0x34]	23863	1			T1	1		T4	1		T27	1
valid_sources[0x35]	9105	1			T1	8		T2	1		T6	1
valid_sources[0x36]	6847	1			T1	7		T2	1		T27	2
valid_sources[0x37]	6793	1			T4	3		T6	3		T10	9
valid_sources[0x38]	6848	1			T1	4		T4	7		T6	5
valid_sources[0x39]	6220	1			T1	9		T24	1		T4	5
valid_sources[0x3a]	7027	1			T1	11		T26	1		T6	2
valid_sources[0x3b]	6944	1			T1	5		T4	5		T27	1
valid_sources[0x3c]	7786	1			T2	1		T24	1		T27	4
valid_sources[0x3d]	6372	1			T1	1		T4	10		T27	2
valid_sources[0x3e]	6941	1			T1	1		T24	1		T6	10
valid_sources[0x3f]	6936	1			T1	2		T25	1		T6	5
valid_sources[0x40]	11063	1			T4	14		T26	1		T6	2
valid_sources[0x41]	7124	1			T1	2		T6	4		T9	3
valid_sources[0x42]	16363	1			T2	1		T26	1		T6	2
valid_sources[0x43]	11219	1			T4	4		T6	7		T10	10
valid_sources[0x44]	6767	1			T4	2		T6	1		T10	3
valid_sources[0x45]	6768	1			T2	1		T26	1		T6	4
valid_sources[0x46]	7857	1			T1	14		T2	2		T6	1
valid_sources[0x47]	10721	1			T4	4		T6	5		T10	2
valid_sources[0x48]	7256	1			T4	1		T6	1		T10	2
valid_sources[0x49]	15187	1			T1	2		T4	2		T6	2
valid_sources[0x4a]	9313	1			T1	18		T2	1		T24	1
valid_sources[0x4b]	7358	1			T25	1		T6	1		T10	4
valid_sources[0x4c]	11112	1			T1	5		T4	3		T6	6
valid_sources[0x4d]	11308	1			T25	2		T27	1		T6	1
valid_sources[0x4e]	6813	1			T2	5		T4	2		T6	2
valid_sources[0x4f]	6674	1			T1	7		T2	1		T4	15
valid_sources[0x50]	10221	1			T1	3		T4	4		T25	1
valid_sources[0x51]	23992	1			T6	3		T10	2		T40	1
valid_sources[0x52]	9832	1			T1	10		T4	5		T6	1
valid_sources[0x53]	6883	1			T1	1		T24	1		T4	3
valid_sources[0x54]	15210	1			T1	1		T2	2		T4	21
valid_sources[0x55]	6845	1			T2	1		T4	5		T6	1
valid_sources[0x56]	6916	1			T1	1		T4	3		T26	2
valid_sources[0x57]	8538	1			T1	5		T2	1		T4	5
valid_sources[0x58]	7198	1			T1	4		T2	2		T6	3
valid_sources[0x59]	7570	1			T4	2		T26	1		T9	3
valid_sources[0x5a]	9523	1			T1	6		T6	4		T10	5
valid_sources[0x5b]	6762	1			T2	1		T4	16		T26	1
valid_sources[0x5c]	7781	1			T1	4		T4	12		T6	7
valid_sources[0x5d]	9278	1			T1	5		T26	2		T6	1
valid_sources[0x5e]	10855	1			T2	1		T4	5		T6	4
valid_sources[0x5f]	13543	1			T1	1		T2	1		T4	1
valid_sources[0x60]	7200	1			T1	7		T24	1		T4	3
valid_sources[0x61]	7689	1			T1	20		T40	2		T41	2
valid_sources[0x62]	9209	1			T1	8		T4	2		T6	2
valid_sources[0x63]	7588	1			T1	9		T6	1		T10	2
valid_sources[0x64]	6665	1			T1	4		T26	2		T6	3
valid_sources[0x65]	10710	1			T2	2		T6	1		T9	1
valid_sources[0x66]	6534	1			T24	1		T26	6		T6	1
valid_sources[0x67]	13060	1			T2	2		T4	7		T6	2
valid_sources[0x68]	9475	1			T4	4		T6	2		T10	2
valid_sources[0x69]	7269	1			T1	4		T4	6		T26	1
valid_sources[0x6a]	6583	1			T1	1		T6	4		T10	6
valid_sources[0x6b]	16841	1			T1	6		T2	1		T6	6
valid_sources[0x6c]	6855	1			T1	5		T2	1		T4	1
valid_sources[0x6d]	16461	1			T2	3		T26	1		T28	42
valid_sources[0x6e]	7798	1			T1	2		T26	1		T27	3
valid_sources[0x6f]	11989	1			T1	1		T2	1		T5	11
valid_sources[0x70]	7016	1			T1	6		T2	1		T24	2
valid_sources[0x71]	13241	1			T1	2		T2	4		T10	6
valid_sources[0x72]	11302	1			T1	4		T4	4		T25	1
valid_sources[0x73]	7479	1			T5	2		T4	4		T10	4
valid_sources[0x74]	7481	1			T4	1		T26	2		T6	1
valid_sources[0x75]	8610	1			T1	1		T4	2		T6	4
valid_sources[0x76]	7169	1			T1	1		T2	1		T25	1
valid_sources[0x77]	28763	1			T1	6		T2	1		T4	4
valid_sources[0x78]	6886	1			T2	4		T4	11		T6	2
valid_sources[0x79]	6663	1			T1	10		T3	25		T6	1
valid_sources[0x7a]	6308	1			T1	1		T5	1		T10	2
valid_sources[0x7b]	6807	1			T1	5		T24	2		T26	3
valid_sources[0x7c]	8017	1			T1	1		T4	3		T26	1
valid_sources[0x7d]	7324	1			T6	4		T40	2		T7	1
valid_sources[0x7e]	6417	1			T4	8		T26	2		T6	1
valid_sources[0x7f]	6604	1			T4	5		T26	1		T6	3
valid_sources[0x80]	7452	1			T1	4		T2	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1022468

1

T1

60

T2

38

T5

10

values[0x0]

all_enables

biggest_size

70972

1

T1

103

T2

32

T5

6

values[0x1]

all_enables

biggest_size

51221

1

T1

113

T2

23

T5

1