Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
82.22	82.22	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	82.22	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
82.22	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	8	37	82.22

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	2	15	88.24	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	2	15	88.24

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ONEST_DONE]	0	1	1
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27755	1			T1	11		T2	1		T4	51
auto[PWRUP]	81	1			T14	1		T93	1		T53	2
auto[ONEST_0]	68	1			T14	1		T37	1		T93	2
auto[ONEST_021]	17	1			T183	2		T184	1		T185	1
auto[ONEST_1]	70	1			T93	1		T53	1		T56	1
auto[LP_0]	98	1			T93	3		T53	1		T56	1
auto[LP_021]	39	1			T14	1		T56	1		T184	1
auto[LP_1]	124	1			T14	5		T93	2		T53	2
auto[LP_EVAL]	58	1			T14	2		T37	1		T93	1
auto[LP_SLP]	453	1			T14	11		T37	2		T93	7
auto[LP_PWRUP]	22	1			T56	1		T186	1		T187	2
auto[NP_0]	131	1			T14	2		T37	2		T93	1
auto[NP_021]	32	1			T14	1		T183	1		T134	1
auto[NP_1]	136	1			T14	1		T22	1		T37	3
auto[NP_EVAL]	25	1			T184	1		T130	1		T186	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T187

1

T125

1

T188

1

min

27321

1

T1

11

T2

1

T4

51

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27325	1			T1	11		T2	1		T4	51
pow[0x1]	4	1			T189	1		T190	1		T191	1
pow[0x2]	9	1			T93	1		T192	1		T193	1
pow[0x3]	26	1			T183	3		T130	1		T194	1
pow[0x4]	65	1			T37	1		T93	1		T53	1
pow[0x5]	110	1			T14	6		T22	1		T37	2
pow[0x6]	214	1			T14	1		T22	1		T37	2
pow[0x7]	467	1			T14	3		T22	1		T37	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

163

1

T14

1

T93

1

T53

3

min

26887

1

T1

11

T2

1

T4

51

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26887	1			T1	11		T2	1		T4	51
pow[0x7]	1	1			T195	1		-	-		-	-
pow[0x8]	6	1			T186	1		T196	1		T197	1
pow[0x9]	8	1			T134	1		T194	1		T198	2
pow[0xa]	11	1			T130	1		T190	1		T199	1
pow[0xb]	32	1			T56	1		T183	1		T184	1
pow[0xc]	58	1			T93	1		T56	1		T183	2
pow[0xd]	113	1			T14	1		T37	1		T93	1
pow[0xe]	260	1			T14	6		T22	1		T37	4
pow[0xf]	529	1			T14	14		T22	1		T37	7