Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	2	15	88.24	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	2	15	88.24

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ONEST_DONE]	0	1	1
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2044	1			T1	10		T2	2		T9	2
auto[PWRUP]	116	1			T14	1		T22	1		T37	2
auto[ONEST_0]	65	1			T53	1		T183	1		T134	2
auto[ONEST_021]	17	1			T56	1		T345	1		T194	2
auto[ONEST_1]	69	1			T14	1		T93	1		T53	1
auto[LP_0]	96	1			T14	1		T22	1		T37	2
auto[LP_021]	28	1			T37	1		T187	1		T189	1
auto[LP_1]	123	1			T14	3		T37	2		T93	2
auto[LP_EVAL]	46	1			T14	1		T37	1		T107	1
auto[LP_SLP]	454	1			T14	6		T15	1		T22	1
auto[LP_PWRUP]	22	1			T184	3		T130	1		T186	1
auto[NP_0]	176	1			T22	3		T37	2		T91	1
auto[NP_021]	41	1			T14	1		T22	1		T37	1
auto[NP_1]	198	1			T14	1		T15	2		T22	2
auto[NP_EVAL]	33	1			T22	1		T91	1		T183	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

2

1

T199

1

T346

1

-

-

min

1757

1

T1

10

T2

2

T9

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1762	1			T1	10		T2	2		T9	2
pow[0x1]	9	1			T14	1		T134	1		T347	1
pow[0x2]	21	1			T37	1		T134	1		T184	2
pow[0x3]	33	1			T93	1		T56	1		T183	1
pow[0x4]	52	1			T93	1		T53	2		T183	1
pow[0x5]	116	1			T14	3		T93	3		T53	1
pow[0x6]	207	1			T14	3		T37	5		T93	2
pow[0x7]	462	1			T14	6		T22	1		T37	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

171

1

T14

1

T22

1

T37

3

min

1232

1

T1

10

T2

2

T9

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1237	1			T1	10		T2	2		T9	2
pow[0x1]	15	1			T91	2		T258	4		T307	1
pow[0x2]	16	1			T271	2		T226	1		T300	1
pow[0x3]	36	1			T22	2		T107	2		T260	6
pow[0x4]	63	1			T15	1		T22	3		T91	1
pow[0x6]	1	1			T134	1		-	-		-	-
pow[0x7]	3	1			T348	1		T349	1		T350	1
pow[0x8]	6	1			T134	1		T189	1		T351	1
pow[0x9]	14	1			T130	1		T186	1		T248	1
pow[0xa]	14	1			T56	1		T134	1		T130	1
pow[0xb]	28	1			T14	1		T184	1		T130	2
pow[0xc]	59	1			T93	1		T56	2		T134	1
pow[0xd]	113	1			T14	5		T37	1		T53	2
pow[0xe]	252	1			T14	3		T37	2		T93	4
pow[0xf]	493	1			T14	4		T22	1		T37	10