Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1141995	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1096983

1

T5

11

T1

2260

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1962823	1			T5	11		T1	1791		T6	10
values[0x0]	137872	1			T5	5		T1	883		T6	7
values[0x1]	138283	1			T5	8		T1	909		T6	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	920744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1318234

1

T5

14

T1

2467

T6

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6466	1			T1	17		T9	7		T7	2
valid_sources[0x01]	6669	1			T1	8		T9	18		T7	1
valid_sources[0x02]	6738	1			T1	17		T9	9		T7	1
valid_sources[0x03]	9352	1			T1	15		T9	3		T7	1
valid_sources[0x04]	10931	1			T1	24		T2	1		T9	3
valid_sources[0x05]	7636	1			T1	33		T8	13		T9	12
valid_sources[0x06]	15263	1			T1	13		T9	6		T7	1
valid_sources[0x07]	6479	1			T1	3		T9	1		T10	7
valid_sources[0x08]	7738	1			T1	10		T9	4		T7	2
valid_sources[0x09]	6670	1			T1	13		T9	5		T7	1
valid_sources[0x0a]	6830	1			T1	22		T2	8		T9	11
valid_sources[0x0b]	7837	1			T1	35		T9	5		T7	3
valid_sources[0x0c]	12054	1			T1	3		T9	3		T7	1
valid_sources[0x0d]	6628	1			T1	6		T9	1		T7	1
valid_sources[0x0e]	7757	1			T1	20		T9	5		T7	2
valid_sources[0x0f]	12201	1			T1	9		T2	8		T4	128
valid_sources[0x10]	6486	1			T1	8		T9	11		T10	4
valid_sources[0x11]	12503	1			T1	11		T9	7		T10	5
valid_sources[0x12]	6800	1			T1	5		T9	6		T7	3
valid_sources[0x13]	11730	1			T1	16		T9	4		T7	1
valid_sources[0x14]	6616	1			T1	20		T9	10		T10	7
valid_sources[0x15]	7488	1			T1	14		T9	6		T10	3
valid_sources[0x16]	7634	1			T5	24		T1	14		T4	128
valid_sources[0x17]	9335	1			T1	14		T9	3		T7	1
valid_sources[0x18]	6926	1			T1	20		T3	3		T8	14
valid_sources[0x19]	6588	1			T1	5		T9	15		T7	2
valid_sources[0x1a]	10878	1			T1	22		T9	6		T7	3
valid_sources[0x1b]	9072	1			T1	10		T9	7		T7	1
valid_sources[0x1c]	6867	1			T1	10		T9	7		T7	1
valid_sources[0x1d]	6497	1			T1	13		T9	3		T7	3
valid_sources[0x1e]	7500	1			T1	16		T9	2		T7	2
valid_sources[0x1f]	12411	1			T1	8		T9	7		T10	8
valid_sources[0x20]	6309	1			T1	4		T9	15		T7	3
valid_sources[0x21]	9624	1			T1	15		T3	17		T9	3
valid_sources[0x22]	6714	1			T1	10		T9	2		T7	4
valid_sources[0x23]	10925	1			T1	5		T9	4		T10	9
valid_sources[0x24]	6844	1			T1	15		T9	3		T7	1
valid_sources[0x25]	11036	1			T1	15		T9	6		T7	1
valid_sources[0x26]	6672	1			T1	21		T9	2		T7	1
valid_sources[0x27]	6798	1			T1	13		T9	9		T7	2
valid_sources[0x28]	7220	1			T1	15		T9	6		T10	6
valid_sources[0x29]	6628	1			T1	9		T9	8		T7	3
valid_sources[0x2a]	6711	1			T1	3		T9	10		T7	3
valid_sources[0x2b]	11015	1			T1	18		T8	8		T9	9
valid_sources[0x2c]	6791	1			T1	26		T9	7		T7	1
valid_sources[0x2d]	6784	1			T1	5		T2	16		T9	8
valid_sources[0x2e]	7751	1			T1	8		T9	7		T10	11
valid_sources[0x2f]	11178	1			T1	26		T9	2		T7	2
valid_sources[0x30]	6663	1			T1	12		T9	5		T10	7
valid_sources[0x31]	12191	1			T1	17		T8	9		T9	5
valid_sources[0x32]	7273	1			T1	17		T9	9		T7	4
valid_sources[0x33]	6794	1			T1	1		T9	8		T10	6
valid_sources[0x34]	15399	1			T1	6		T9	4		T10	3
valid_sources[0x35]	7163	1			T1	12		T9	11		T7	1
valid_sources[0x36]	6583	1			T1	21		T9	1		T7	2
valid_sources[0x37]	7501	1			T1	24		T8	9		T9	6
valid_sources[0x38]	9561	1			T1	20		T9	9		T7	1
valid_sources[0x39]	11232	1			T1	19		T2	1		T9	5
valid_sources[0x3a]	11177	1			T1	7		T2	4		T9	9
valid_sources[0x3b]	6470	1			T1	8		T9	8		T10	8
valid_sources[0x3c]	6784	1			T1	9		T9	7		T7	3
valid_sources[0x3d]	7708	1			T1	15		T4	128		T9	4
valid_sources[0x3e]	12703	1			T1	11		T2	3		T9	1
valid_sources[0x3f]	7865	1			T1	27		T4	128		T9	1
valid_sources[0x40]	6844	1			T1	15		T7	2		T10	5
valid_sources[0x41]	7942	1			T1	4		T3	2		T9	1
valid_sources[0x42]	15608	1			T1	22		T9	7		T7	1
valid_sources[0x43]	17182	1			T1	7		T2	2		T4	128
valid_sources[0x44]	6432	1			T1	19		T9	8		T7	1
valid_sources[0x45]	11116	1			T1	15		T9	6		T7	1
valid_sources[0x46]	8810	1			T1	5		T2	1		T4	128
valid_sources[0x47]	6959	1			T1	7		T9	2		T10	7
valid_sources[0x48]	6640	1			T1	20		T9	2		T7	1
valid_sources[0x49]	8427	1			T1	20		T2	5		T9	16
valid_sources[0x4a]	6681	1			T1	7		T3	4		T9	9
valid_sources[0x4b]	7896	1			T1	6		T2	4		T9	7
valid_sources[0x4c]	6845	1			T1	10		T9	6		T7	4
valid_sources[0x4d]	7727	1			T1	11		T9	8		T7	1
valid_sources[0x4e]	11169	1			T1	19		T9	10		T10	9
valid_sources[0x4f]	13734	1			T1	22		T2	5		T9	6
valid_sources[0x50]	7396	1			T1	11		T9	5		T7	1
valid_sources[0x51]	11010	1			T1	3		T9	4		T7	3
valid_sources[0x52]	6910	1			T1	29		T9	4		T7	1
valid_sources[0x53]	6127	1			T1	11		T9	5		T7	1
valid_sources[0x54]	8335	1			T1	17		T9	5		T10	7
valid_sources[0x55]	12559	1			T1	7		T2	1		T9	5
valid_sources[0x56]	9557	1			T1	6		T9	5		T7	1
valid_sources[0x57]	11979	1			T1	21		T2	1		T9	13
valid_sources[0x58]	13028	1			T1	11		T9	10		T10	5
valid_sources[0x59]	16041	1			T1	9		T9	9		T7	1
valid_sources[0x5a]	7530	1			T1	12		T9	10		T7	2
valid_sources[0x5b]	6936	1			T1	7		T9	3		T7	4
valid_sources[0x5c]	6901	1			T1	14		T9	9		T7	1
valid_sources[0x5d]	13873	1			T1	16		T9	7		T7	3
valid_sources[0x5e]	9275	1			T1	18		T9	21		T7	1
valid_sources[0x5f]	22190	1			T1	26		T9	5		T10	4
valid_sources[0x60]	10745	1			T1	11		T9	5		T10	7
valid_sources[0x61]	7234	1			T1	15		T2	2		T9	2
valid_sources[0x62]	6714	1			T1	5		T2	1		T9	3
valid_sources[0x63]	6396	1			T1	1		T9	5		T7	4
valid_sources[0x64]	6888	1			T1	26		T3	3		T9	3
valid_sources[0x65]	6895	1			T1	8		T9	2		T7	2
valid_sources[0x66]	20658	1			T1	9		T9	2		T10	6
valid_sources[0x67]	7855	1			T1	33		T9	6		T7	3
valid_sources[0x68]	7032	1			T1	4		T2	3		T9	3
valid_sources[0x69]	6609	1			T1	26		T9	4		T7	1
valid_sources[0x6a]	6801	1			T1	21		T9	10		T7	2
valid_sources[0x6b]	7802	1			T1	10		T9	1		T10	7
valid_sources[0x6c]	6950	1			T1	1		T9	4		T7	2
valid_sources[0x6d]	7325	1			T1	13		T2	4		T9	4
valid_sources[0x6e]	7853	1			T1	11		T9	3		T10	7
valid_sources[0x6f]	8285	1			T1	20		T9	4		T7	2
valid_sources[0x70]	6813	1			T1	9		T9	6		T10	12
valid_sources[0x71]	11304	1			T1	1		T2	3		T4	124
valid_sources[0x72]	14999	1			T1	17		T9	17		T7	1
valid_sources[0x73]	6925	1			T1	11		T4	128		T9	3
valid_sources[0x74]	10968	1			T1	18		T9	8		T7	2
valid_sources[0x75]	6625	1			T1	18		T9	6		T7	1
valid_sources[0x76]	8861	1			T1	21		T9	6		T7	1
valid_sources[0x77]	7121	1			T1	22		T9	4		T10	8
valid_sources[0x78]	7348	1			T1	4		T4	128		T9	6
valid_sources[0x79]	6454	1			T1	15		T9	12		T7	2
valid_sources[0x7a]	6763	1			T1	29		T2	3		T9	3
valid_sources[0x7b]	11492	1			T1	7		T4	256		T9	7
valid_sources[0x7c]	7727	1			T1	13		T4	128		T9	6
valid_sources[0x7d]	7610	1			T1	15		T2	1		T9	6
valid_sources[0x7e]	10341	1			T1	34		T2	5		T9	17
valid_sources[0x7f]	15190	1			T1	4		T2	3		T9	8
valid_sources[0x80]	14442	1			T1	2		T2	2		T9	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

978959

1

T5

6

T1

887

T6

5

values[0x0]

all_enables

biggest_size

68650

1

T5

2

T1

709

T6

2

values[0x1]

all_enables

biggest_size

49374

1

T5

3

T1

664

T2

23