Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29095	1			T1	4		T3	24		T4	3
auto[PWRUP]	113	1			T29	1		T30	1		T31	3
auto[ONEST_0]	74	1			T175	1		T176	1		T177	1
auto[ONEST_021]	20	1			T31	1		T177	1		T178	1
auto[ONEST_1]	84	1			T18	2		T29	1		T31	3
auto[ONEST_DONE]	3	1			T179	1		T180	1		T181	1
auto[LP_0]	123	1			T175	3		T152	2		T176	3
auto[LP_021]	25	1			T31	1		T175	3		T182	1
auto[LP_1]	117	1			T29	1		T30	4		T31	6
auto[LP_EVAL]	51	1			T31	1		T176	2		T177	1
auto[LP_SLP]	525	1			T18	2		T29	3		T30	11
auto[LP_PWRUP]	26	1			T29	1		T31	2		T183	1
auto[NP_0]	149	1			T29	5		T30	2		T31	3
auto[NP_021]	26	1			T31	1		T152	1		T182	1
auto[NP_1]	131	1			T18	1		T29	1		T89	1
auto[NP_EVAL]	37	1			T18	1		T175	1		T176	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T184

1

T185

1

T186

1

min

28624

1

T1

4

T3

24

T4

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28630	1			T1	4		T3	24		T4	3
pow[0x1]	8	1			T178	2		T187	1		T188	1
pow[0x2]	19	1			T30	1		T152	1		T177	1
pow[0x3]	37	1			T175	1		T152	1		T122	1
pow[0x4]	54	1			T30	2		T31	3		T152	1
pow[0x5]	117	1			T18	1		T29	3		T30	2
pow[0x6]	264	1			T18	1		T29	1		T30	2
pow[0x7]	489	1			T18	3		T29	5		T30	12

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

187

1

T18

1

T30

5

T31

2

min

28102

1

T1

4

T3

24

T4

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28102	1			T1	4		T3	24		T4	3
pow[0x5]	1	1			T189	1		-	-		-	-
pow[0x7]	2	1			T175	1		T190	1		-	-
pow[0x8]	6	1			T184	1		T191	1		T192	1
pow[0x9]	9	1			T152	1		T184	1		T193	1
pow[0xa]	22	1			T30	3		T175	1		T178	2
pow[0xb]	37	1			T30	1		T31	2		T152	1
pow[0xc]	64	1			T30	3		T152	2		T182	2
pow[0xd]	163	1			T18	1		T29	3		T30	4
pow[0xe]	286	1			T18	2		T30	5		T31	6
pow[0xf]	578	1			T18	1		T29	3		T30	11