Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2223	1			T2	1		T9	20		T10	20
auto[PWRUP]	146	1			T18	2		T29	1		T88	1
auto[ONEST_0]	80	1			T31	1		T175	2		T177	2
auto[ONEST_021]	19	1			T176	2		T187	1		T338	1
auto[ONEST_1]	102	1			T29	1		T30	3		T89	1
auto[ONEST_DONE]	5	1			T152	1		T190	1		T251	1
auto[LP_0]	128	1			T18	1		T30	1		T31	2
auto[LP_021]	23	1			T29	1		T175	1		T122	1
auto[LP_1]	133	1			T18	1		T29	1		T30	1
auto[LP_EVAL]	67	1			T18	4		T31	1		T175	2
auto[LP_SLP]	515	1			T18	4		T29	2		T88	3
auto[LP_PWRUP]	31	1			T18	1		T30	1		T89	1
auto[NP_0]	215	1			T18	5		T85	3		T88	1
auto[NP_021]	55	1			T18	1		T29	1		T89	1
auto[NP_1]	209	1			T18	1		T85	1		T29	1
auto[NP_EVAL]	29	1			T18	3		T88	1		T176	1
auto[NP_DONE]	2	1			T339	1		T340	1		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

2

1

T180

1

T341

1

-

-

min

1891

1

T2

1

T9

20

T10

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1898	1			T2	1		T9	20		T10	20
pow[0x1]	7	1			T116	1		T251	1		T342	1
pow[0x2]	17	1			T29	1		T179	1		T190	1
pow[0x3]	36	1			T29	1		T152	1		T176	1
pow[0x4]	60	1			T29	2		T31	1		T176	3
pow[0x5]	123	1			T18	1		T29	1		T30	1
pow[0x6]	242	1			T18	4		T30	1		T31	5
pow[0x7]	542	1			T18	4		T29	3		T30	11

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

213

1

T18

1

T30

3

T31

4

min

1266

1

T2

1

T9

20

T10

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x8]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1270	1			T2	1		T9	20		T10	20
pow[0x1]	11	1			T291	1		T317	1		T333	2
pow[0x2]	26	1			T18	1		T85	1		T116	1
pow[0x3]	60	1			T85	1		T89	1		T122	1
pow[0x4]	59	1			T18	3		T85	2		T88	1
pow[0x5]	1	1			T343	1		-	-		-	-
pow[0x6]	1	1			T177	1		-	-		-	-
pow[0x7]	2	1			T152	1		T344	1		-	-
pow[0x9]	10	1			T176	1		T119	1		T201	1
pow[0xa]	13	1			T30	1		T175	1		T152	1
pow[0xb]	32	1			T31	1		T175	4		T152	1
pow[0xc]	70	1			T30	1		T31	1		T182	3
pow[0xd]	148	1			T29	1		T30	2		T89	1
pow[0xe]	299	1			T18	3		T29	1		T30	11
pow[0xf]	562	1			T18	4		T29	3		T30	6