Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T18,T28,T29

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T18
0	1	Covered	T13,T14,T18
1	0	Covered	T13,T14,T18

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T13,T18,T19
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T18,T19
0	1	Covered	T13,T18,T19
1	0	Covered	T13,T18,T19

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T18
0	1	Covered	T13,T14,T18
1	0	Covered	T13,T14,T18

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T15,T16
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T19
0	1	Covered	T13,T14,T19
1	0	Covered	T13,T14,T18

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T14,T18,T19
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T14,T18,T19
1	0	Covered	T14,T18,T19

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T19
0	1	Covered	T14,T19,T20
1	0	Covered	T13,T14,T18

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T18
0	1	Covered	T13,T14,T18
1	0	Covered	T13,T14,T18

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T20
1	0	Covered	T14,T18,T20
1	1	Covered	T13,T14,T15

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T15,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T19
0	1	Covered	T13,T14,T19
1	0	Covered	T13,T14,T18

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T13,T18,T19
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T18,T19
0	1	Covered	T13,T18,T19
1	0	Covered	T13,T18,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T15,T16
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T18
0	1	Covered	T13,T14,T19
1	0	Covered	T13,T14,T18

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T15,T16
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T19
0	1	Covered	T13,T14,T19
1	0	Covered	T13,T14,T18

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T14,T18,T19
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T14,T19,T20
1	0	Covered	T14,T18,T19

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T19
0	1	Covered	T13,T14,T19
1	0	Covered	T13,T14,T18

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T18
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T18
0	1	Covered	T13,T14,T18
1	0	Covered	T13,T14,T18

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T20
1	0	Covered	T14,T18,T20
1	1	Covered	T13,T14,T15

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T14,T15,T16
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T15,T16,T17
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T13,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T15,T16

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T15,T16

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T14,T15
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T15
1	0	1	Covered	T13,T14,T15
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T15,T16

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T28,T29
0	1	Covered	T13,T14,T15
0	0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T18,T19

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T18,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T18,T19

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T14,T18,T19

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T18

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T13,T14,T15

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	31172096	30861390	0	0
gen_filter_match[0].MatchCheck00_A	31172096	9310381	0	0
gen_filter_match[0].MatchCheck01_A	31172096	2418605	0	0
gen_filter_match[0].MatchCheck10_A	31172096	2509871	0	0
gen_filter_match[0].MatchCheck11_A	31172096	16622533	0	0
gen_filter_match[1].MatchCheck00_A	31172096	10548300	0	0
gen_filter_match[1].MatchCheck01_A	31172096	1414698	0	0
gen_filter_match[1].MatchCheck10_A	31172096	992464	0	0
gen_filter_match[1].MatchCheck11_A	31172096	17905928	0	0
gen_filter_match[2].MatchCheck00_A	31172096	10997358	0	0
gen_filter_match[2].MatchCheck01_A	31172096	713333	0	0
gen_filter_match[2].MatchCheck10_A	31172096	363259	0	0
gen_filter_match[2].MatchCheck11_A	31172096	18787440	0	0
gen_filter_match[3].MatchCheck00_A	31172096	12182421	0	0
gen_filter_match[3].MatchCheck01_A	31172096	171761	0	0
gen_filter_match[3].MatchCheck10_A	31172096	201218	0	0
gen_filter_match[3].MatchCheck11_A	31172096	18305990	0	0
gen_filter_match[4].MatchCheck00_A	31172096	11562523	0	0
gen_filter_match[4].MatchCheck01_A	31172096	66535	0	0
gen_filter_match[4].MatchCheck10_A	31172096	64610	0	0
gen_filter_match[4].MatchCheck11_A	31172096	19167722	0	0
gen_filter_match[5].MatchCheck00_A	31172096	11188703	0	0
gen_filter_match[5].MatchCheck01_A	31172096	66089	0	0
gen_filter_match[5].MatchCheck10_A	31172096	75	0	0
gen_filter_match[5].MatchCheck11_A	31172096	19606523	0	0
gen_filter_match[6].MatchCheck00_A	31172096	12259610	0	0
gen_filter_match[6].MatchCheck01_A	31172096	35089	0	0
gen_filter_match[6].MatchCheck10_A	31172096	32873	0	0
gen_filter_match[6].MatchCheck11_A	31172096	18533818	0	0
gen_filter_match[7].MatchCheck00_A	31172096	11517805	0	0
gen_filter_match[7].MatchCheck01_A	31172096	65766	0	0
gen_filter_match[7].MatchCheck10_A	31172096	98973	0	0
gen_filter_match[7].MatchCheck11_A	31172096	19178846	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	30861390	0	0
T13	66165	66089	0	0
T14	64666	64616	0	0
T15	32968	32881	0	0
T16	98464	98405	0	0
T17	98631	98539	0	0
T18	40292	37657	0	0
T19	104233	104147	0	0
T20	66334	66235	0	0
T21	33120	33061	0	0
T22	99103	99014	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	9310381	0	0
T13	66165	32931	0	0
T14	64666	31777	0	0
T15	32968	3	0	0
T16	98464	3	0	0
T17	98631	3	0	0
T18	40292	19631	0	0
T19	104233	72254	0	0
T20	66334	32838	0	0
T21	33120	33061	0	0
T22	99103	34248	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	2418605	0	0
T22	99103	32339	0	0
T28	1164	0	0	0
T32	138655	0	0	0
T33	32910	0	0	0
T85	28100	27666	0	0
T94	32948	0	0	0
T95	66885	0	0	0
T96	0	33648	0	0
T97	0	33147	0	0
T98	0	32302	0	0
T99	0	33210	0	0
T100	0	32687	0	0
T101	0	32816	0	0
T102	0	33789	0	0
T103	0	7471	0	0
T104	65585	0	0	0
T105	65477	0	0	0
T106	96679	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	2509871	0	0
T13	66165	33158	0	0
T14	64666	0	0	0
T15	32968	0	0	0
T16	98464	0	0	0
T17	98631	0	0	0
T18	40292	0	0	0
T19	104233	0	0	0
T20	66334	33397	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T99	0	32893	0	0
T105	0	32448	0	0
T107	0	32671	0	0
T108	0	33457	0	0
T109	0	33091	0	0
T110	0	33763	0	0
T111	0	35129	0	0
T112	0	3	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	16622533	0	0
T14	64666	32839	0	0
T15	32968	32878	0	0
T16	98464	98402	0	0
T17	98631	98536	0	0
T18	40292	18026	0	0
T19	104233	31893	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	32427	0	0
T32	0	99311	0	0
T33	32910	0	0	0
T94	0	32848	0	0
T95	0	66788	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	10548300	0	0
T13	66165	3	0	0
T14	64666	31777	0	0
T15	32968	3	0	0
T16	98464	3	0	0
T17	98631	3	0	0
T18	40292	20227	0	0
T19	104233	67983	0	0
T20	66334	66235	0	0
T21	33120	4	0	0
T22	99103	3	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	1414698	0	0
T22	99103	32427	0	0
T28	1164	0	0	0
T32	138655	65508	0	0
T33	32910	0	0	0
T85	28100	0	0	0
T94	32948	0	0	0
T95	66885	0	0	0
T100	0	32633	0	0
T104	65585	0	0	0
T105	65477	0	0	0
T106	96679	0	0	0
T109	0	33201	0	0
T112	0	3	0	0
T113	0	32823	0	0
T114	0	33362	0	0
T115	0	31506	0	0
T116	0	6709	0	0
T117	0	32782	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	992464	0	0
T18	40292	1	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T32	138655	0	0	0
T33	32910	0	0	0
T85	28100	0	0	0
T94	32948	0	0	0
T95	66885	0	0	0
T100	0	33705	0	0
T104	0	32503	0	0
T109	0	1	0	0
T112	0	3	0	0
T113	0	32447	0	0
T118	0	39794	0	0
T119	0	7	0	0
T120	0	1	0	0
T121	0	32327	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	17905928	0	0
T13	66165	66086	0	0
T14	64666	32839	0	0
T15	32968	32878	0	0
T16	98464	98402	0	0
T17	98631	98536	0	0
T18	40292	17429	0	0
T19	104233	36164	0	0
T20	66334	0	0	0
T21	33120	33057	0	0
T22	99103	66584	0	0
T33	0	32831	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	10997358	0	0
T13	66165	66089	0	0
T14	64666	3	0	0
T15	32968	3	0	0
T16	98464	3	0	0
T17	98631	3	0	0
T18	40292	13927	0	0
T19	104233	104147	0	0
T20	66334	32838	0	0
T21	33120	4	0	0
T22	99103	66675	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	713333	0	0
T14	64666	31774	0	0
T15	32968	0	0	0
T16	98464	0	0	0
T17	98631	0	0	0
T18	40292	0	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T33	32910	0	0	0
T106	0	32193	0	0
T109	0	1	0	0
T113	0	33419	0	0
T121	0	1	0	0
T122	0	19765	0	0
T123	0	2	0	0
T124	0	33291	0	0
T125	0	32616	0	0
T126	0	32375	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	363259	0	0
T18	40292	5	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T32	138655	0	0	0
T33	32910	0	0	0
T85	28100	0	0	0
T94	32948	0	0	0
T95	66885	0	0	0
T102	0	32327	0	0
T109	0	1	0	0
T114	0	1	0	0
T119	0	7	0	0
T120	0	1	0	0
T121	0	1	0	0
T123	0	2	0	0
T127	0	1	0	0
T128	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	18787440	0	0
T14	64666	32839	0	0
T15	32968	32878	0	0
T16	98464	98402	0	0
T17	98631	98536	0	0
T18	40292	23725	0	0
T19	104233	0	0	0
T20	66334	33397	0	0
T21	33120	33057	0	0
T22	99103	32339	0	0
T32	0	99311	0	0
T33	32910	32831	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	12182421	0	0
T13	66165	33160	0	0
T14	64666	3	0	0
T15	32968	3	0	0
T16	98464	3	0	0
T17	98631	3	0	0
T18	40292	31357	0	0
T19	104233	36168	0	0
T20	66334	33401	0	0
T21	33120	33061	0	0
T22	99103	99014	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	171761	0	0
T13	66165	1	0	0
T14	64666	0	0	0
T15	32968	0	0	0
T16	98464	0	0	0
T17	98631	0	0	0
T18	40292	0	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T32	0	33868	0	0
T120	0	1	0	0
T121	0	1	0	0
T129	0	32266	0	0
T130	0	32489	0	0
T131	0	1	0	0
T132	0	32439	0	0
T133	0	1	0	0
T134	0	33575	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	201218	0	0
T13	66165	1	0	0
T14	64666	0	0	0
T15	32968	0	0	0
T16	98464	0	0	0
T17	98631	0	0	0
T18	40292	3	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T112	0	3	0	0
T120	0	1	0	0
T121	0	1	0	0
T123	0	2	0	0
T127	0	1	0	0
T128	0	1	0	0
T135	0	1	0	0
T136	0	34221	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	18305990	0	0
T13	66165	32927	0	0
T14	64666	64613	0	0
T15	32968	32878	0	0
T16	98464	98402	0	0
T17	98631	98536	0	0
T18	40292	6297	0	0
T19	104233	67979	0	0
T20	66334	32834	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T32	0	65091	0	0
T33	0	32831	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	11562523	0	0
T13	66165	33160	0	0
T14	64666	64616	0	0
T15	32968	3	0	0
T16	98464	3	0	0
T17	98631	3	0	0
T18	40292	13927	0	0
T19	104233	72254	0	0
T20	66334	4	0	0
T21	33120	33061	0	0
T22	99103	32430	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	66535	0	0
T13	66165	1	0	0
T14	64666	0	0	0
T15	32968	0	0	0
T16	98464	0	0	0
T17	98631	0	0	0
T18	40292	0	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T112	0	3	0	0
T123	0	2	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	33413	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	3	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	64610	0	0
T13	66165	1	0	0
T14	64666	0	0	0
T15	32968	0	0	0
T16	98464	1	0	0
T17	98631	0	0	0
T18	40292	5	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T109	0	1	0	0
T112	0	3	0	0
T119	0	7	0	0
T127	0	1	0	0
T135	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	19167722	0	0
T13	66165	32927	0	0
T14	64666	0	0	0
T15	32968	32878	0	0
T16	98464	98401	0	0
T17	98631	98536	0	0
T18	40292	23725	0	0
T19	104233	31893	0	0
T20	66334	66231	0	0
T21	33120	0	0	0
T22	99103	66584	0	0
T32	0	32578	0	0
T33	0	32831	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	11188703	0	0
T13	66165	3	0	0
T14	64666	32842	0	0
T15	32968	3	0	0
T16	98464	3	0	0
T17	98631	3	0	0
T18	40292	13927	0	0
T19	104233	104147	0	0
T20	66334	66235	0	0
T21	33120	4	0	0
T22	99103	32342	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	66089	0	0
T28	1164	0	0	0
T29	13639	0	0	0
T90	37796	0	0	0
T105	65477	32974	0	0
T106	96679	0	0	0
T109	66369	1	0	0
T121	0	1	0	0
T145	0	33108	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	792	0	0	0
T151	33393	0	0	0
T152	18820	0	0	0
T153	1063	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	75	0	0
T13	66165	1	0	0
T14	64666	0	0	0
T15	32968	0	0	0
T16	98464	1	0	0
T17	98631	0	0	0
T18	40292	5	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T122	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	19606523	0	0
T13	66165	66085	0	0
T14	64666	31774	0	0
T15	32968	32878	0	0
T16	98464	98401	0	0
T17	98631	98536	0	0
T18	40292	23725	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	33057	0	0
T22	99103	66672	0	0
T32	0	98959	0	0
T33	0	32831	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	12259610	0	0
T13	66165	3	0	0
T14	64666	31777	0	0
T15	32968	3	0	0
T16	98464	3	0	0
T17	98631	3	0	0
T18	40292	37657	0	0
T19	104233	67983	0	0
T20	66334	4	0	0
T21	33120	4	0	0
T22	99103	34248	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	35089	0	0
T101	65469	0	0	0
T102	99110	0	0	0
T112	65355	3	0	0
T127	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T154	0	1	0	0
T155	0	1934	0	0
T156	0	1	0	0
T157	0	33145	0	0
T158	0	2	0	0
T159	66850	0	0	0
T160	1096	0	0	0
T161	97466	0	0	0
T162	65915	0	0	0
T163	8731	0	0	0
T164	96248	0	0	0
T165	64911	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	32873	0	0
T13	66165	1	0	0
T14	64666	0	0	0
T15	32968	0	0	0
T16	98464	1	0	0
T17	98631	0	0	0
T18	40292	0	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T109	0	1	0	0
T112	0	3	0	0
T119	0	6	0	0
T122	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	18533818	0	0
T13	66165	66085	0	0
T14	64666	32839	0	0
T15	32968	32878	0	0
T16	98464	98401	0	0
T17	98631	98536	0	0
T18	40292	0	0	0
T19	104233	36164	0	0
T20	66334	66231	0	0
T21	33120	33057	0	0
T22	99103	64766	0	0
T33	0	32831	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	11517805	0	0
T13	66165	33160	0	0
T14	64666	31777	0	0
T15	32968	3	0	0
T16	98464	3	0	0
T17	98631	3	0	0
T18	40292	37657	0	0
T19	104233	72254	0	0
T20	66334	33401	0	0
T21	33120	33061	0	0
T22	99103	3	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	65766	0	0
T13	66165	1	0	0
T14	64666	0	0	0
T15	32968	0	0	0
T16	98464	0	0	0
T17	98631	0	0	0
T18	40292	0	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T108	0	1	0	0
T123	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T154	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	33014	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	98973	0	0
T13	66165	1	0	0
T14	64666	0	0	0
T15	32968	0	0	0
T16	98464	1	0	0
T17	98631	0	0	0
T18	40292	0	0	0
T19	104233	0	0	0
T20	66334	0	0	0
T21	33120	0	0	0
T22	99103	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T114	0	1	0	0
T122	0	1	0	0
T127	0	1	0	0
T135	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31172096	19178846	0	0
T13	66165	32927	0	0
T14	64666	32839	0	0
T15	32968	32878	0	0
T16	98464	98401	0	0
T17	98631	98536	0	0
T18	40292	0	0	0
T19	104233	31893	0	0
T20	66334	32834	0	0
T21	33120	0	0	0
T22	99103	99011	0	0
T32	0	33868	0	0
T94	0	32848	0	0